3402aac7d9
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/ArmLib.h>
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#include <Drivers/PL310L2Cache.h>
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#include <Library/PcdLib.h>
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#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)
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#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)
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// Initialize PL320 L2 Cache Controller
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VOID
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L2x0CacheInit (
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IN UINTN L2x0Base,
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IN UINT32 L2x0TagLatencies,
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IN UINT32 L2x0DataLatencies,
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IN UINT32 L2x0AuxValue,
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IN UINT32 L2x0AuxMask,
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IN BOOLEAN CacheEnabled
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)
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{
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UINT32 Data;
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UINT32 Revision;
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UINT32 Aux;
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UINT32 PfCtl;
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UINT32 PwrCtl;
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// Check if L2x0 is present and is an ARM implementation
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Data = L2x0ReadReg(L2X0_CACHEID);
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if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {
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ASSERT(0);
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return;
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}
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// Check if L2x0 is PL310
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if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {
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ASSERT(0);
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return;
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}
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// RTL release
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Revision = Data & 0x3F;
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// Check if L2x0 is already enabled then we disable it
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Data = L2x0ReadReg(L2X0_CTRL);
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if (Data & L2X0_CTRL_ENABLED) {
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L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);
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}
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//
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// Set up global configurations
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//
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// Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO
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Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;
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// Use AWCACHE attributes for WA
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Aux |= L2x0_AUXCTRL_AW_AWCACHE;
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// Use default Size
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Data = L2x0ReadReg(L2X0_AUXCTRL);
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Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;
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// Use default associativity
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Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;
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// Enabled I & D Prefetch
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Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;
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if (Revision >= 5) {
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// Prefetch Offset Register
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PfCtl = L2x0ReadReg(L2X0_PFCTRL);
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// - Prefetch increment set to 0
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// - Prefetch dropping off
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// - Double linefills off
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L2x0WriteReg(L2X0_PFCTRL, PfCtl);
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// Power Control Register - L2X0_PWRCTRL
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PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);
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// - Standby when idle off
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// - Dynamic clock gating off
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// - Nc,NC-shared dropping off
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L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);
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}
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if (Revision >= 2) {
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L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);
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L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);
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} else {
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// PL310 old style latency is not supported yet
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ASSERT(0);
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}
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// Set the platform specific values
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Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;
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// Write Auxiliary value
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L2x0WriteReg(L2X0_AUXCTRL, Aux);
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//
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// Invalidate all entries in cache
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//
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L2x0WriteReg(L2X0_INVWAY, 0xffff);
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// Poll cache maintenance register until invalidate operation is complete
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while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);
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// Write to the Lockdown D and Lockdown I Register 9 if required
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// - Not required
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// Clear any residual raw interrupts
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L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);
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// Enable the cache
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if (CacheEnabled) {
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L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);
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}
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}
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