9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/** @file
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AsmFlushCacheLine function
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/**
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Flushes a cache line from all the instruction and data caches within the
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coherency domain of the CPU.
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Flushed the cache line specified by LinearAddress, and returns LinearAddress.
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This function is only available on IA-32 and x64.
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@param LinearAddress The address of the cache line to flush. If the CPU is
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in a physical addressing mode, then LinearAddress is a
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physical address. If the CPU is in a virtual
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addressing mode, then LinearAddress is a virtual
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address.
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@return LinearAddress
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**/
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VOID *
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EFIAPI
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AsmFlushCacheLine (
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IN VOID *LinearAddress
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)
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{
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//
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// If the CPU does not support CLFLUSH instruction,
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// then promote flush range to flush entire cache.
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//
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_asm {
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mov eax, 1
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cpuid
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test edx, BIT19
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jz NoClflush
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mov eax, dword ptr [LinearAddress]
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clflush [eax]
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jmp Done
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NoClflush:
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wbinvd
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Done:
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}
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return LinearAddress;
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}
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