7601b251fd
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
36 lines
707 B
C
36 lines
707 B
C
/** @file
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CPU get interrupt state function for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
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/**
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Retrieves the current CPU interrupt state.
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Returns TRUE is interrupts are currently enabled. Otherwise
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returns FALSE.
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@retval TRUE CPU interrupts are enabled.
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@retval FALSE CPU interrupts are disabled.
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**/
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BOOLEAN
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EFIAPI
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GetInterruptState (
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VOID
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)
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{
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unsigned long RetValue;
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RetValue = RiscVGetSupervisorModeInterrupts ();
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return RetValue? TRUE: FALSE;
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}
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