eab2678815
The ARM architecture version 8 deprecates all uses of the IT instruction except cases where it is followed by a single narrow instruction. So replace any occurrences with equivalent sequences that adhere to the new rules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
149 lines
5.7 KiB
ArmAsm
149 lines
5.7 KiB
ArmAsm
// Copyright (c) 2010-2011, Linaro Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// * Neither the name of Linaro Limited nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Written by Dave Gilbert <david.gilbert@linaro.org>
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//
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// This memchr routine is optimised on a Cortex-A9 and should work on
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// all ARMv7 processors. It has a fast past for short sizes, and has
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// an optimised path for large data sets; the worst case is finding the
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// match early in a large data set.
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//
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// 2011-02-07 david.gilbert@linaro.org
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// Extracted from local git a5b438d861
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// 2011-07-14 david.gilbert@linaro.org
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// Import endianness fix from local git ea786f1b
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// 2011-12-07 david.gilbert@linaro.org
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// Removed unneeded cbz from align loop
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// this lets us check a flag in a 00/ff byte easily in either endianness
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#define CHARTSTMASK(c) 1<<(c*8)
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.text
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.thumb
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.syntax unified
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.type ASM_PFX(InternalMemScanMem8), %function
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ASM_GLOBAL ASM_PFX(InternalMemScanMem8)
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ASM_PFX(InternalMemScanMem8):
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// r0 = start of memory to scan
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// r1 = length
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// r2 = character to look for
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// returns r0 = pointer to character or NULL if not found
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uxtb r2, r2 // Don't think we can trust the caller to actually pass a char
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cmp r1, #16 // If it's short don't bother with anything clever
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blt 20f
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tst r0, #7 // If it's already aligned skip the next bit
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beq 10f
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// Work up to an aligned point
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5:
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ldrb r3, [r0],#1
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subs r1, r1, #1
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cmp r3, r2
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beq 50f // If it matches exit found
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tst r0, #7
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bne 5b // If not aligned yet then do next byte
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10:
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// At this point, we are aligned, we know we have at least 8 bytes to work with
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push {r4-r7}
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orr r2, r2, r2, lsl #8 // expand the match word across to all bytes
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orr r2, r2, r2, lsl #16
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bic r4, r1, #7 // Number of double words to work with
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mvns r7, #0 // all F's
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movs r3, #0
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15:
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ldmia r0!, {r5,r6}
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subs r4, r4, #8
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eor r5, r5, r2 // Get it so that r5,r6 have 00's where the bytes match the target
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eor r6, r6, r2
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uadd8 r5, r5, r7 // Parallel add 0xff - sets the GE bits for anything that wasn't 0
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sel r5, r3, r7 // bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
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uadd8 r6, r6, r7 // Parallel add 0xff - sets the GE bits for anything that wasn't 0
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sel r6, r5, r7 // chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
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cbnz r6, 60f
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bne 15b // (Flags from the subs above) If not run out of bytes then go around again
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pop {r4-r7}
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and r2, r2, #0xff // Get r2 back to a single character from the expansion above
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and r1, r1, #7 // Leave the count remaining as the number after the double words have been done
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20:
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cbz r1, 40f // 0 length or hit the end already then not found
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21: // Post aligned section, or just a short call
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ldrb r3, [r0], #1
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subs r1, r1, #1
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eor r3, r3, r2 // r3 = 0 if match - doesn't break flags from sub
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cbz r3, 50f
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bne 21b // on r1 flags
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40:
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movs r0, #0 // not found
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bx lr
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50:
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subs r0, r0, #1 // found
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bx lr
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60: // We're here because the fast path found a hit - now we have to track down exactly which word it was
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// r0 points to the start of the double word after the one that was tested
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// r5 has the 00/ff pattern for the first word, r6 has the chained value
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subs r0, r0, #3
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cmp r5, #0
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it eq
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moveq.n r5, r6 // the end is in the 2nd word
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it ne
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subne.n r0, r0, #4 // or 2nd byte of 1st word
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// r0 currently points to the 3rd byte of the word containing the hit
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tst r5, #CHARTSTMASK(0) // 1st character
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bne 61f
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adds r0, r0, #1
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tst r5, #CHARTSTMASK(1) // 2nd character
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bne 61f
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adds r0, r0 ,#1
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tst r5, #(3 << 15) // 2nd & 3rd character
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// If not the 3rd must be the last one
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it eq
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addeq.n r0, r0, #1
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61:
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pop {r4-r7}
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subs r0, r0, #1
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bx lr
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