9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
/** @file
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Internal function to get spin lock alignment.
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Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseSynchronizationLibInternals.h"
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/**
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Internal function to retrieve the architecture specific spin lock alignment
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requirements for optimal spin lock performance.
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@return The architecture specific spin lock alignment.
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**/
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UINTN
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InternalGetSpinLockProperties (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEbx;
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UINTN FamilyId;
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UINTN ModelId;
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UINTN CacheLineSize;
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//
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// Retrieve CPUID Version Information
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//
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AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL);
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//
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// EBX: Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size)
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//
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CacheLineSize = ((RegEbx >> 8) & 0xff) * 8;
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//
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// Retrieve CPU Family and Model
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//
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if (FamilyId == 0x0f) {
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//
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// In processors based on Intel NetBurst microarchitecture, use two cache lines
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//
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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if (ModelId <= 0x04 || ModelId == 0x06) {
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CacheLineSize *= 2;
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}
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}
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if (CacheLineSize < 32) {
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CacheLineSize = 32;
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}
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return CacheLineSize;
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}
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