8fc06b6e19
If a device which support both features SR-IOV/ARI has multi
functions, which maybe support 8-255. After enable ARI forwarding in
the root port and ARI Capable Hierarchy in the SR-IOV PF0.
The device will support and expose multi functions(0-255) with ARI ID routing.
In next device loop in below for() code, actually it still be in the
same SR-IOV device, and just some PF which is over 8 or higher
one(n*8), PciAllocateBusNumber() will allocate bus
number(ReservedBusNum - TempReservedBusNum)) for this PF. if reset
TempReservedBusNum as 0 in this case,it will allocate wrong bus number
for this PF because TempReservedBusNum should be total previous PF's
reserved bus numbers.
code:
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
TempReservedBusNum = 0;
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
//
// Check to see whether a pci device is present
//
Status = PciDevicePresent (
PciRootBridgeIo,
&Pci,
StartBusNumber,
Device,
Func
);
...
Status = PciAllocateBusNumber (PciDevice, *SubBusNumber,
(UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);
The solution is add a new flag IsAriEnabled to help handle this case.
if ARI is enabled, then TempReservedBusNum will not be reset again
during all functions(1-255) scan with checking flag IsAriEnabled.
Signed-off-by: Foster Nong <foster.nong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
395 lines
13 KiB
C
395 lines
13 KiB
C
/** @file
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Header files and data structures needed by PCI Bus module.
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Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_PCI_BUS_H_
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#define _EFI_PCI_BUS_H_
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#include <PiDxe.h>
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#include <Protocol/LoadedImage.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciIo.h>
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#include <Protocol/LoadFile2.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/PciHotPlugRequest.h>
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#include <Protocol/DevicePath.h>
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#include <Protocol/PciPlatform.h>
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#include <Protocol/PciHotPlugInit.h>
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#include <Protocol/Decompress.h>
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#include <Protocol/BusSpecificDriverOverride.h>
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#include <Protocol/IncompatiblePciDeviceSupport.h>
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#include <Protocol/PciOverride.h>
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#include <Protocol/PciEnumerationComplete.h>
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#include <Protocol/IoMmu.h>
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#include <Protocol/DeviceSecurity.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiDriverEntryPoint.h>
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#include <Library/BaseLib.h>
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#include <Library/UefiLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/ReportStatusCodeLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/PeImage.h>
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#include <IndustryStandard/Acpi.h>
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typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
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typedef struct _PCI_BAR PCI_BAR;
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#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
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#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
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#define EFI_PCI_IOV_POLICY_ARI 0x0001
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#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
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#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
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typedef enum {
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PciBarTypeUnknown = 0,
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PciBarTypeIo16,
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PciBarTypeIo32,
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PciBarTypeMem32,
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PciBarTypePMem32,
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PciBarTypeMem64,
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PciBarTypePMem64,
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PciBarTypeOpRom,
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PciBarTypeIo,
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PciBarTypeMem,
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PciBarTypeMaxType
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} PCI_BAR_TYPE;
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#include "ComponentName.h"
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#include "PciIo.h"
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#include "PciCommand.h"
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#include "PciDeviceSupport.h"
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#include "PciEnumerator.h"
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#include "PciEnumeratorSupport.h"
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#include "PciDriverOverride.h"
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#include "PciRomTable.h"
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#include "PciOptionRomSupport.h"
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#include "PciPowerManagement.h"
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#include "PciHotPlugSupport.h"
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#include "PciLib.h"
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#define VGABASE1 0x3B0
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#define VGALIMIT1 0x3BB
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#define VGABASE2 0x3C0
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#define VGALIMIT2 0x3DF
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#define ISABASE 0x100
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#define ISALIMIT 0x3FF
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//
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// PCI BAR parameters
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//
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struct _PCI_BAR {
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UINT64 BaseAddress;
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UINT64 Length;
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UINT64 Alignment;
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PCI_BAR_TYPE BarType;
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BOOLEAN BarTypeFixed;
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UINT16 Offset;
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};
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//
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// defined in PCI Card Specification, 8.0
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//
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#define PCI_CARD_MEMORY_BASE_0 0x1C
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#define PCI_CARD_MEMORY_LIMIT_0 0x20
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#define PCI_CARD_MEMORY_BASE_1 0x24
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#define PCI_CARD_MEMORY_LIMIT_1 0x28
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#define PCI_CARD_IO_BASE_0_LOWER 0x2C
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#define PCI_CARD_IO_BASE_0_UPPER 0x2E
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#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
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#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
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#define PCI_CARD_IO_BASE_1_LOWER 0x34
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#define PCI_CARD_IO_BASE_1_UPPER 0x36
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#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
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#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
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#define PCI_CARD_BRIDGE_CONTROL 0x3E
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#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
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#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
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#define RB_IO_RANGE 1
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#define RB_MEM32_RANGE 2
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#define RB_PMEM32_RANGE 3
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#define RB_MEM64_RANGE 4
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#define RB_PMEM64_RANGE 5
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#define PPB_BAR_0 0
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#define PPB_BAR_1 1
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#define PPB_IO_RANGE 2
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#define PPB_MEM32_RANGE 3
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#define PPB_PMEM32_RANGE 4
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#define PPB_PMEM64_RANGE 5
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#define PPB_MEM64_RANGE 0xFF
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#define P2C_BAR_0 0
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#define P2C_MEM_1 1
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#define P2C_MEM_2 2
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#define P2C_IO_1 3
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#define P2C_IO_2 4
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#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
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#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
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#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
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#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
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#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
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#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
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#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
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#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
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//
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// Define option for attribute
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//
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#define EFI_SET_SUPPORTS 0
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#define EFI_SET_ATTRIBUTES 1
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#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
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struct _PCI_IO_DEVICE {
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UINT32 Signature;
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EFI_HANDLE Handle;
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EFI_PCI_IO_PROTOCOL PciIo;
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LIST_ENTRY Link;
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EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
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EFI_LOAD_FILE2_PROTOCOL LoadFile2;
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//
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// PCI configuration space header type
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//
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PCI_TYPE00 Pci;
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//
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// Bus number, Device number, Function number
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//
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UINT8 BusNumber;
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UINT8 DeviceNumber;
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UINT8 FunctionNumber;
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//
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// BAR for this PCI Device
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//
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PCI_BAR PciBar[PCI_MAX_BAR];
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//
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// The bridge device this pci device is subject to
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//
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PCI_IO_DEVICE *Parent;
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//
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// A linked list for children Pci Device if it is bridge device
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//
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LIST_ENTRY ChildList;
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//
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// TRUE if the PCI bus driver creates the handle for this PCI device
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//
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BOOLEAN Registered;
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//
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// TRUE if the PCI bus driver successfully allocates the resource required by
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// this PCI device
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//
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BOOLEAN Allocated;
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//
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// The attribute this PCI device currently set
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//
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UINT64 Attributes;
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//
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// The attributes this PCI device actually supports
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//
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UINT64 Supports;
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//
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// The resource decode the bridge supports
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//
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UINT32 Decodes;
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//
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// TRUE if the ROM image is from the PCI Option ROM BAR
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//
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BOOLEAN EmbeddedRom;
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//
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// The OptionRom Size
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//
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UINT32 RomSize;
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//
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// TRUE if all OpROM (in device or in platform specific position) have been processed
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//
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BOOLEAN AllOpRomProcessed;
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//
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// TRUE if there is any EFI driver in the OptionRom
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//
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BOOLEAN BusOverride;
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//
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// A list tracking reserved resource on a bridge device
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//
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LIST_ENTRY ReservedResourceList;
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//
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// A list tracking image handle of platform specific overriding driver
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//
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LIST_ENTRY OptionRomDriverList;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
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EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
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//
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// Bus number ranges for a PCI Root Bridge device
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//
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
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BOOLEAN IsPciExp;
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BOOLEAN IsAriEnabled;
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//
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// For SR-IOV
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//
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UINT8 PciExpressCapabilityOffset;
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UINT32 AriCapabilityOffset;
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UINT32 SrIovCapabilityOffset;
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UINT32 MrIovCapabilityOffset;
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PCI_BAR VfPciBar[PCI_MAX_BAR];
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UINT32 SystemPageSize;
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UINT16 InitialVFs;
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UINT16 ReservedBusNum;
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//
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// Per PCI to PCI Bridge spec, I/O window is 4K aligned,
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// but some chipsets support non-standard I/O window alignments less than 4K.
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// This field is used to support this case.
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//
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UINT16 BridgeIoAlignment;
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UINT32 ResizableBarOffset;
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UINT32 ResizableBarNumber;
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};
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#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
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CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
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#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
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CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
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#define PCI_IO_DEVICE_FROM_LINK(a) \
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CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
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#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
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CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
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//
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// Global Variables
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//
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extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
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extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
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extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
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extern BOOLEAN gFullEnumeration;
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extern UINTN gPciHostBridgeNumber;
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extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
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extern UINT64 gAllOne;
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extern UINT64 gAllZero;
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extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
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extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
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extern BOOLEAN mReserveIsaAliases;
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extern BOOLEAN mReserveVgaAliases;
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/**
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Macro that checks whether device is a GFX device.
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@param _p Specified device.
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@retval TRUE Device is a GFX device.
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@retval FALSE Device is not a GFX device.
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**/
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#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
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/**
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Test to see if this driver supports ControllerHandle. Any ControllerHandle
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than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
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@param This Protocol instance pointer.
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@param Controller Handle of device to test.
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@param RemainingDevicePath Optional parameter use to pick a specific child
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device to start.
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@retval EFI_SUCCESS This driver supports this device.
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@retval EFI_ALREADY_STARTED This driver is already running on this device.
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@retval other This driver does not support this device.
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**/
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EFI_STATUS
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EFIAPI
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PciBusDriverBindingSupported (
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IN EFI_DRIVER_BINDING_PROTOCOL *This,
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IN EFI_HANDLE Controller,
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IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
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);
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/**
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Start this driver on ControllerHandle and enumerate Pci bus and start
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all device under PCI bus.
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@param This Protocol instance pointer.
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@param Controller Handle of device to bind driver to.
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@param RemainingDevicePath Optional parameter use to pick a specific child
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device to start.
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@retval EFI_SUCCESS This driver is added to ControllerHandle.
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@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
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@retval other This driver does not support this device.
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**/
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EFI_STATUS
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EFIAPI
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PciBusDriverBindingStart (
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IN EFI_DRIVER_BINDING_PROTOCOL *This,
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IN EFI_HANDLE Controller,
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IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
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);
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/**
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Stop this driver on ControllerHandle. Support stopping any child handles
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created by this driver.
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@param This Protocol instance pointer.
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@param Controller Handle of device to stop driver on.
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@param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of
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children is zero stop the entire bus driver.
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@param ChildHandleBuffer List of Child Handles to Stop.
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@retval EFI_SUCCESS This driver is removed ControllerHandle.
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@retval other This driver was not removed from this device.
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**/
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EFI_STATUS
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EFIAPI
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PciBusDriverBindingStop (
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IN EFI_DRIVER_BINDING_PROTOCOL *This,
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IN EFI_HANDLE Controller,
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IN UINTN NumberOfChildren,
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IN EFI_HANDLE *ChildHandleBuffer
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);
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#endif
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