91c38d4e94
Replace tabs by spaces for indentation to comply to EDK2 coding standards. Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf", "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg, BeagleBoardPkg or Omap35xxPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
337 lines
12 KiB
C
337 lines
12 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef _PL341DMC_H_
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#define _PL341DMC_H_
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typedef struct {
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UINTN HasQos; // has QoS registers
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UINTN MaxChip; // number of memory chips accessible
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BOOLEAN IsUserCfg;
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UINT32 User0Cfg;
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UINT32 User2Cfg;
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UINT32 RefreshPeriod;
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UINT32 CasLatency;
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UINT32 WriteLatency;
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UINT32 t_mrd;
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UINT32 t_ras;
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UINT32 t_rc;
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UINT32 t_rcd;
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UINT32 t_rfc;
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UINT32 t_rp;
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UINT32 t_rrd;
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UINT32 t_wr;
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UINT32 t_wtr;
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UINT32 t_xp;
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UINT32 t_xsr;
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UINT32 t_esr;
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UINT32 MemoryCfg;
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UINT32 MemoryCfg2;
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UINT32 MemoryCfg3;
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UINT32 ChipCfg0;
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UINT32 ChipCfg1;
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UINT32 ChipCfg2;
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UINT32 ChipCfg3;
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UINT32 t_faw;
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UINT32 t_data_en;
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UINT32 t_wdata_en;
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UINT32 ModeReg;
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UINT32 ExtModeReg;
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} PL341_DMC_CONFIG;
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/* Memory config bit fields */
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#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
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#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
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#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
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#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
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#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
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#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
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#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
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#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
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#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
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#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
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#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
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#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
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#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
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#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
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#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
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#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
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#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
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#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
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#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
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#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
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#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
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#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
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#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
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#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
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#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
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#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
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#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
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#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
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//
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// DMC Configuration Register Map
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//
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#define DMC_STATUS_REG 0x00
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#define DMC_COMMAND_REG 0x04
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#define DMC_DIRECT_CMD_REG 0x08
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#define DMC_MEMORY_CONFIG_REG 0x0C
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#define DMC_REFRESH_PRD_REG 0x10
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#define DMC_CAS_LATENCY_REG 0x14
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#define DMC_WRITE_LATENCY_REG 0x18
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#define DMC_T_MRD_REG 0x1C
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#define DMC_T_RAS_REG 0x20
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#define DMC_T_RC_REG 0x24
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#define DMC_T_RCD_REG 0x28
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#define DMC_T_RFC_REG 0x2C
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#define DMC_T_RP_REG 0x30
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#define DMC_T_RRD_REG 0x34
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#define DMC_T_WR_REG 0x38
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#define DMC_T_WTR_REG 0x3C
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#define DMC_T_XP_REG 0x40
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#define DMC_T_XSR_REG 0x44
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#define DMC_T_ESR_REG 0x48
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#define DMC_MEMORY_CFG2_REG 0x4C
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#define DMC_MEMORY_CFG3_REG 0x50
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#define DMC_T_FAW_REG 0x54
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#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
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#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
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// Returns the state of the memory controller:
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#define DMC_STATUS_CONFIG 0x0
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#define DMC_STATUS_READY 0x1
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#define DMC_STATUS_PAUSED 0x2
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#define DMC_STATUS_LOWPOWER 0x3
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// Changes the state of the memory controller:
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#define DMC_COMMAND_GO 0x0
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#define DMC_COMMAND_SLEEP 0x1
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#define DMC_COMMAND_WAKEUP 0x2
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#define DMC_COMMAND_PAUSE 0x3
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#define DMC_COMMAND_CONFIGURE 0x4
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#define DMC_COMMAND_ACTIVEPAUSE 0x7
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// Determines the command required
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#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
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#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
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#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
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#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
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#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
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//
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// AXI ID configuration register map
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//
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#define DMC_ID_0_CFG_REG 0x100
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#define DMC_ID_1_CFG_REG 0x104
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#define DMC_ID_2_CFG_REG 0x108
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#define DMC_ID_3_CFG_REG 0x10C
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#define DMC_ID_4_CFG_REG 0x110
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#define DMC_ID_5_CFG_REG 0x114
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#define DMC_ID_6_CFG_REG 0x118
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#define DMC_ID_7_CFG_REG 0x11C
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#define DMC_ID_8_CFG_REG 0x120
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#define DMC_ID_9_CFG_REG 0x124
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#define DMC_ID_10_CFG_REG 0x128
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#define DMC_ID_11_CFG_REG 0x12C
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#define DMC_ID_12_CFG_REG 0x130
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#define DMC_ID_13_CFG_REG 0x134
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#define DMC_ID_14_CFG_REG 0x138
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#define DMC_ID_15_CFG_REG 0x13C
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// Set the QoS
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#define DMC_ID_CFG_QOS_DISABLE 0
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#define DMC_ID_CFG_QOS_ENABLE 1
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#define DMC_ID_CFG_QOS_MIN 2
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//
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// Chip configuration register map
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//
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#define DMC_CHIP_0_CFG_REG 0x200
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#define DMC_CHIP_1_CFG_REG 0x204
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#define DMC_CHIP_2_CFG_REG 0x208
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#define DMC_CHIP_3_CFG_REG 0x20C
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//
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// User Defined Pins
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//
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#define DMC_USER_STATUS_REG 0x300
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#define DMC_USER_0_CFG_REG 0x304
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#define DMC_USER_1_CFG_REG 0x308
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#define DMC_FEATURE_CRTL_REG 0x30C
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#define DMC_USER_2_CFG_REG 0x310
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//
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// PHY Register Settings
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//
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#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
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#define PHY_PTM_IOTERM 0xE04
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#define PHY_PTM_PLL_EN 0xe0c
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#define PHY_PTM_PLL_RANGE 0xe18
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#define PHY_PTM_FEEBACK_DIV 0xe1c
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#define PHY_PTM_RCLK_DIV 0xe20
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#define PHY_PTM_LOCK_STATUS 0xe28
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#define PHY_PTM_INIT_DONE 0xe34
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#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
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#define PHY_PTM_SQU_TRAINING 0xee8
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#define PHY_PTM_SQU_STAT 0xeec
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// ==============================================================================
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// PIPD 40G DDR2/DDR3 PHY Register definitions
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//
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// Offsets from APB Base Address
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// ==============================================================================
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#define PHY_BYTE0_OFFSET 0x000
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#define PHY_BYTE1_OFFSET 0x200
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#define PHY_BYTE2_OFFSET 0x400
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#define PHY_BYTE3_OFFSET 0x600
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#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
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#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
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#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
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#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
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#define PHY_BYTE0_IOSTR_OFFSET 0x004
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#define PHY_BYTE1_IOSTR_OFFSET 0x204
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#define PHY_BYTE2_IOSTR_OFFSET 0x404
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#define PHY_BYTE3_IOSTR_OFFSET 0x604
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;//--------------------------------------------------------------------------
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// DFI Clock ranges:
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#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
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#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
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#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
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#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
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#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
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#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
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#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
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#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
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//--------------------------------------------------------------------------
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// PLL Range
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#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
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#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
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#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
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#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
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#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
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#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
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#define TC_UIOLHNC_MASK 0x000003C0
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#define TC_UIOLHNC_SHIFT 0x6
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#define TC_UIOLHPC_MASK 0x0000003F
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#define TC_UIOLHPC_SHIFT 0x2
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#define TC_UIOHOCT_MASK 0x2
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#define TC_UIOHOCT_SHIFT 0x1
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#define TC_UIOHSTOP_SHIFT 0x0
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#define TC_UIOLHXC_VALUE 0x4
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#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
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#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
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//--------------------------------------
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// JEDEC DDR2 Device Register definitions and settings
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//--------------------------------------
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#define DDR_MODESET_SHFT 14
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#define DDR_MODESET_MR 0x0 ;// Mode register
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#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
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#define DDR_MODESET_EMR2 0x2
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#define DDR_MODESET_EMR3 0x3
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//
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// Extended Mode Register settings
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//
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#define DDR_EMR_OCD_MASK 0x0000380
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#define DDR_EMR_OCD_SHIFT 0x7
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#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
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#define DDR_EMR_RTT_SHIFT 0x2
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#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
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#define DDR_EMR_ODS_SHIFT 0x0001
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// Termination Values:
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#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
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#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
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#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
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// Output Drive Strength Values:
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#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
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#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
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// OCD values
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#define DDR_EMR_OCD_DEFAULT 0x7
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#define DDR_EMR_OCD_NS 0x0
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#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
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#define DDR_SDRAM_START_ADDR 0x10000000
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// ----------------------------------------
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// PHY IOTERM values
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// ----------------------------------------
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#define PHY_PTM_IOTERM_OFF 0x0
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#define PHY_PTM_IOTERM_150R 0x1
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#define PHY_PTM_IOTERM_75R 0x2
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#define PHY_PTM_IOTERM_50R 0x3
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#define PHY_BYTE_IOSTR_60OHM 0x0
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#define PHY_BYTE_IOSTR_40OHM 0x1
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#define PHY_BYTE_IOSTR_30OHM 0x2
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#define PHY_BYTE_IOSTR_30AOHM 0x3
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#define DDR2_MR_BURST_LENGTH_4 (2)
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#define DDR2_MR_BURST_LENGTH_8 (3)
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#define DDR2_MR_DLL_RESET (1 << 8)
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#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
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#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
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#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
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#define DDR2_MR_WR_CYCLES_2 (1 << 9)
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#define DDR2_MR_WR_CYCLES_3 (2 << 9)
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#define DDR2_MR_WR_CYCLES_4 (3 << 9)
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#define DDR2_MR_WR_CYCLES_5 (4 << 9)
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#define DDR2_MR_WR_CYCLES_6 (5 << 9)
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VOID
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PL341DmcInit (
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IN UINTN DmcBase,
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IN PL341_DMC_CONFIG* DmcConfig
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);
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VOID PL341DmcPhyInit (
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IN UINTN DmcPhyBase
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);
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VOID PL341DmcTrainPHY (
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IN UINTN DmcPhyBase
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);
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#endif /* _PL341DMC_H_ */
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