1a99203052
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781 Provides sample code to include FSPT_ARCH_UPD initial values with UPD header revision set to 2. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/** @file
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Sample to provide TempRamInitParams data.
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Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/PcdLib.h>
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#include <FspEas.h>
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typedef struct {
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UINT32 MicrocodeRegionBase;
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UINT32 MicrocodeRegionSize;
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UINT32 CodeRegionBase;
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UINT32 CodeRegionSize;
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} FSPT_CORE_UPD;
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typedef struct {
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FSP_UPD_HEADER FspUpdHeader;
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//
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// If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
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//
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FSPT_ARCH_UPD FsptArchUpd;
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FSPT_CORE_UPD FsptCoreUpd;
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} FSPT_UPD_CORE_DATA;
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GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
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{
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0x4450555F54505346,
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//
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// UPD header revision must be equal or greater than 2 when the structure is compliant with FSP spec 2.2.
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//
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0x02,
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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}
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},
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//
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// If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
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//
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{
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0x01,
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{
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0x00, 0x00, 0x00
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},
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0x00000020,
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0x00000000,
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{
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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}
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},
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{
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((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
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((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),
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FixedPcdGet32 (PcdFlashCodeCacheAddress),
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FixedPcdGet32 (PcdFlashCodeCacheSize),
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}
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};
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