e5efcf8be8
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiPayloadPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
171 lines
3.8 KiB
C
171 lines
3.8 KiB
C
/** @file
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Copyright (c) 2017-2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SpiCommon.h"
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/**
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Acquire SPI MMIO BAR.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@retval Return SPI BAR Address
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**/
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UINT32
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AcquireSpiBar0 (
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IN UINTN PchSpiBase
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)
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{
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return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
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}
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/**
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Release SPI MMIO BAR. Do nothing.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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**/
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VOID
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ReleaseSpiBar0 (
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IN UINTN PchSpiBase
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)
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{
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}
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/**
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This function is to enable/disable BIOS Write Protect in SMM phase.
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@param[in] EnableSmmSts Flag to Enable/disable Bios write protect
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**/
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VOID
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CpuSmmDisableBiosWriteProtect (
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IN BOOLEAN EnableSmmSts
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)
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{
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UINT32 Data32;
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if (EnableSmmSts) {
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//
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// Disable BIOS Write Protect in SMM phase.
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//
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Data32 = MmioRead32 ((UINTN)(0xFED30880)) | (UINT32)(BIT0);
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AsmWriteMsr32 (0x000001FE, Data32);
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} else {
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//
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// Enable BIOS Write Protect in SMM phase
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//
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Data32 = MmioRead32 ((UINTN)(0xFED30880)) & (UINT32)(~BIT0);
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AsmWriteMsr32 (0x000001FE, Data32);
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}
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//
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// Read FED30880h back to ensure the setting went through.
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//
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Data32 = MmioRead32 (0xFED30880);
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}
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/**
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This function is a hook for Spi to disable BIOS Write Protect.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
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@retval EFI_SUCCESS The protocol instance was properly initialized
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@retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
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**/
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EFI_STATUS
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EFIAPI
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DisableBiosWriteProtect (
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IN UINTN PchSpiBase,
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IN UINT8 CpuSmmBwp
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)
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{
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//
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// Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
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//
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MmioOr8 (PchSpiBase + R_SPI_BCR + 1, (B_SPI_BCR_SYNC_SS >> 8));
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//
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// Enable the access to the BIOS space for both read and write cycles
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//
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MmioOr8 (PchSpiBase + R_SPI_BCR, B_SPI_BCR_BIOSWE);
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if (CpuSmmBwp != 0) {
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CpuSmmDisableBiosWriteProtect (TRUE);
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}
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return EFI_SUCCESS;
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}
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/**
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This function is a hook for Spi to enable BIOS Write Protect.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
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**/
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VOID
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EFIAPI
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EnableBiosWriteProtect (
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IN UINTN PchSpiBase,
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IN UINT8 CpuSmmBwp
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)
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{
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//
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// Disable the access to the BIOS space for write cycles
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//
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MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8)(~B_SPI_BCR_BIOSWE));
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if (CpuSmmBwp != 0) {
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CpuSmmDisableBiosWriteProtect (FALSE);
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}
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}
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/**
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This function disables SPI Prefetching and caching,
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and returns previous BIOS Control Register value before disabling.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@retval Previous BIOS Control Register value
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**/
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UINT8
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SaveAndDisableSpiPrefetchCache (
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IN UINTN PchSpiBase
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)
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{
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UINT8 BiosCtlSave;
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BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
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MmioAndThenOr32 (
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PchSpiBase + R_SPI_BCR, \
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(UINT32)(~B_SPI_BCR_SRC), \
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(UINT32)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)
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);
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return BiosCtlSave;
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}
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/**
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This function updates BIOS Control Register with the given value.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@param[in] BiosCtlValue BIOS Control Register Value to be updated
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**/
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VOID
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SetSpiBiosControlRegister (
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IN UINTN PchSpiBase,
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IN UINT8 BiosCtlValue
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)
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{
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MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);
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}
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