69da506c92
RegisterCpuInterruptHandler did not allow setting exception handlers for anything beyond the timer IRQ. Beyond that, it didn't meet the spec around handling of inputs. RiscVSupervisorModeTrapHandler now will invoke set handlers for both exceptions and interrupts. Two arrays of handlers are maintained - one for exceptions and one for interrupts. For unhandled traps, RiscVSupervisorModeTrapHandler dumps state using the now implemented DumpCpuContext. For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped PC address (SEPC), just like on AArch64 (ELR). This is necessary for X86EmulatorPkg to work as it allows a trap handler to return execution to a different place. Add SSTATUS/STVAL as well, at least for debugging purposes. There is no value in hiding this. Fix nested exception handling. Handler code should not be saving SIE (the value is saved in SSTATUS.SPIE) or directly restored (that's done by SRET). Save and restore the entire SSTATUS and STVAL, too. Cc: Daniel Schaefer <git@danielschaefer.me> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
112 lines
2.6 KiB
C
112 lines
2.6 KiB
C
/** @file
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RISC-V Exception Handler library definition file.
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Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
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#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
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#include <Register/RiscV64/RiscVImpl.h>
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/**
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Trap Handler for S-mode
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**/
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VOID
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SupervisorModeTrap (
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VOID
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);
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//
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// Index of SMode trap register
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//
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#define SMODE_TRAP_REGS_zero 0
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#define SMODE_TRAP_REGS_ra 1
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#define SMODE_TRAP_REGS_sp 2
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#define SMODE_TRAP_REGS_gp 3
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#define SMODE_TRAP_REGS_tp 4
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#define SMODE_TRAP_REGS_t0 5
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#define SMODE_TRAP_REGS_t1 6
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#define SMODE_TRAP_REGS_t2 7
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#define SMODE_TRAP_REGS_s0 8
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#define SMODE_TRAP_REGS_s1 9
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#define SMODE_TRAP_REGS_a0 10
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#define SMODE_TRAP_REGS_a1 11
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#define SMODE_TRAP_REGS_a2 12
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#define SMODE_TRAP_REGS_a3 13
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#define SMODE_TRAP_REGS_a4 14
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#define SMODE_TRAP_REGS_a5 15
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#define SMODE_TRAP_REGS_a6 16
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#define SMODE_TRAP_REGS_a7 17
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#define SMODE_TRAP_REGS_s2 18
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#define SMODE_TRAP_REGS_s3 19
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#define SMODE_TRAP_REGS_s4 20
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#define SMODE_TRAP_REGS_s5 21
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#define SMODE_TRAP_REGS_s6 22
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#define SMODE_TRAP_REGS_s7 23
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#define SMODE_TRAP_REGS_s8 24
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#define SMODE_TRAP_REGS_s9 25
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#define SMODE_TRAP_REGS_s10 26
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#define SMODE_TRAP_REGS_s11 27
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#define SMODE_TRAP_REGS_t3 28
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#define SMODE_TRAP_REGS_t4 29
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#define SMODE_TRAP_REGS_t5 30
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#define SMODE_TRAP_REGS_t6 31
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#define SMODE_TRAP_REGS_sepc 32
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#define SMODE_TRAP_REGS_sstatus 33
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#define SMODE_TRAP_REGS_stval 34
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#define SMODE_TRAP_REGS_last 35
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#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
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#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
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#pragma pack(1)
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typedef struct {
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//
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// Below follow the format of EFI_SYSTEM_CONTEXT.
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//
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UINT64 zero;
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UINT64 ra;
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UINT64 sp;
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UINT64 gp;
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UINT64 tp;
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UINT64 t0;
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UINT64 t1;
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UINT64 t2;
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UINT64 s0;
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UINT64 s1;
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UINT64 a0;
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UINT64 a1;
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UINT64 a2;
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UINT64 a3;
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UINT64 a4;
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UINT64 a5;
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UINT64 a6;
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UINT64 a7;
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UINT64 s2;
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UINT64 s3;
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UINT64 s4;
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UINT64 s5;
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UINT64 s6;
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UINT64 s7;
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UINT64 s8;
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UINT64 s9;
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UINT64 s10;
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UINT64 s11;
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UINT64 t3;
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UINT64 t4;
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UINT64 t5;
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UINT64 t6;
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UINT64 sepc;
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UINT64 sstatus;
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UINT64 stval;
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} SMODE_TRAP_REGISTERS;
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#pragma pack()
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#endif
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