3402aac7d9
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
153 lines
4.6 KiB
NASM
153 lines
4.6 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT ExceptionHandlersStart
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EXPORT ExceptionHandlersEnd
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EXPORT CommonExceptionEntry
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EXPORT AsmCommonExceptionEntry
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IMPORT CommonCExceptionHandler
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PRESERVE8
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AREA DxeExceptionHandlers, CODE, READONLY
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ExceptionHandlersStart
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Reset
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b ResetEntry
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UndefinedInstruction
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b UndefinedInstructionEntry
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SoftwareInterrupt
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b SoftwareInterruptEntry
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PrefetchAbort
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b PrefetchAbortEntry
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DataAbort
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b DataAbortEntry
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ReservedException
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b ReservedExceptionEntry
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Irq
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b IrqEntry
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Fiq
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b FiqEntry
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ResetEntry
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stmfd SP!,{R0-R1}
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mov R0,#0
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ldr R1,CommonExceptionEntry
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bx R1
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UndefinedInstructionEntry
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stmfd SP!,{R0-R1}
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mov R0,#1
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ldr R1,CommonExceptionEntry
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bx R1
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SoftwareInterruptEntry
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stmfd SP!,{R0-R1}
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mov R0,#2
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ldr R1,CommonExceptionEntry
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bx R1
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PrefetchAbortEntry
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stmfd SP!,{R0-R1}
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mov R0,#3
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SUB LR,LR,#4
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ldr R1,CommonExceptionEntry
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bx R1
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DataAbortEntry
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stmfd SP!,{R0-R1}
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mov R0,#4
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SUB LR,LR,#8
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ldr R1,CommonExceptionEntry
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bx R1
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ReservedExceptionEntry
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stmfd SP!,{R0-R1}
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mov R0,#5
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ldr R1,CommonExceptionEntry
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bx R1
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IrqEntry
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stmfd SP!,{R0-R1}
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mov R0,#6
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SUB LR,LR,#4
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ldr R1,CommonExceptionEntry
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bx R1
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FiqEntry
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stmfd SP!,{R0-R1}
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mov R0,#7
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SUB LR,LR,#4
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ldr R1,CommonExceptionEntry
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bx R1
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CommonExceptionEntry
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dcd 0x12345678
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ExceptionHandlersEnd
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AsmCommonExceptionEntry
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mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
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stmfd SP!,{R1} ; Store the IFAR
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mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
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stmfd SP!,{R1} ; Store the IFSR
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mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
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stmfd SP!,{R1} ; Store the DFAR
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mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
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stmfd SP!,{R1} ; Store the DFSR
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mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
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stmfd SP!,{R1} ; Store the SPSR
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stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
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stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
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nop ; Required by ARM architecture
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SUB SP,SP,#0x08 ; Adjust stack pointer
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stmfd SP!,{R2-R12} ; Store general purpose registers
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ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
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ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
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stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
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mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
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sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
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blx CommonCExceptionHandler ; Call exception handler
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add SP,SP,#4 ; Adjust SP back to where we were
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ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
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MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
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ldmfd SP!,{R0-R12} ; Restore general purpose registers
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ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
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nop ; Required by ARM architecture
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add SP,SP,#0x08 ; Adjust stack pointer
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ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
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add SP,SP,#0x1C ; Clear out the remaining stack space
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movs PC,LR ; Return from exception
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END
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