3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
168 lines
6.1 KiB
C
168 lines
6.1 KiB
C
/**
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**/
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/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchPlatformPolicy.h
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@brief
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PCH policy PPI produced by a platform driver specifying various
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expected PCH settings. This PPI is consumed by the PCH PEI modules.
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**/
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#ifndef PCH_PLATFORM_POLICY_H_
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#define PCH_PLATFORM_POLICY_H_
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//
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// External include files do NOT need to be explicitly specified in real EDKII
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// environment
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//
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#include "PchRegs.h"
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//
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#define PCH_PLATFORM_POLICY_PPI_GUID \
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{ \
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0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \
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}
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extern EFI_GUID gPchPlatformPolicyPpiGuid;
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///
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/// Forward reference for ANSI C compatibility
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///
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typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
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///
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/// PPI revision number
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/// Any backwards compatible changes to this PPI will result in an update in the revision number
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/// Major changes will require publication of a new PPI
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///
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/// Revision 1: Original version
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///
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#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1
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#define PCH_PLATFORM_POLICY_PPI_REVISION_2 2
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#define PCH_PLATFORM_POLICY_PPI_REVISION_3 3
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#define PCH_PLATFORM_POLICY_PPI_REVISION_4 4
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#define PCH_PLATFORM_POLICY_PPI_REVISION_5 5
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//
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// Generic definitions for device enabling/disabling used by PCH code.
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//
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#define PCH_DEVICE_ENABLE 1
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#define PCH_DEVICE_DISABLE 0
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typedef struct {
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UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!!
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UINT8 MchTempReadEnable : 1;
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UINT8 PchTempReadEnable : 1;
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UINT8 CpuEnergyReadEnable : 1;
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UINT8 CpuTempReadEnable : 1;
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UINT8 Cpu2TempReadEnable : 1;
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UINT8 TsOnDimmEnable : 1;
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UINT8 Dimm1TempReadEnable : 1;
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UINT8 Dimm2TempReadEnable : 1;
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UINT8 Dimm3TempReadEnable : 1;
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UINT8 Dimm4TempReadEnable : 1;
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UINT8 Rsvdbits : 5;
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} PCH_THERMAL_REPORT_CONTROL;
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//
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// ---------------------------- HPET Config -----------------------------
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//
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typedef struct {
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BOOLEAN Enable; /// Determines if enable HPET function
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UINT32 Base; /// The HPET base address
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} PCH_HPET_CONFIG;
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///
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/// ---------------------------- SATA Config -----------------------------
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///
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typedef enum {
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PchSataModeIde,
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PchSataModeAhci,
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PchSataModeRaid,
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PchSataModeMax
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} PCH_SATA_MODE;
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///
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/// ---------------------------- PCI Express Config -----------------------------
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///
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typedef enum {
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PchPcieAuto,
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PchPcieGen1,
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PchPcieGen2
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} PCH_PCIE_SPEED;
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typedef struct {
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PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
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} PCH_PCIE_CONFIG;
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///
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/// ---------------------------- IO APIC Config -----------------------------
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///
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typedef struct {
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UINT8 IoApicId;
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} PCH_IOAPIC_CONFIG;
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///
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/// --------------------- Low Power Input Output Config ------------------------
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///
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typedef struct {
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UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled
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UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled
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UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled
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UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled
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UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled
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UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled
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UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled
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UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled
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UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled
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UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled
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UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled
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UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled
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UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled
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UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled
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UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled
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UINT8 Rsvdbits : 2;
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} PEI_PCH_LPSS_CONFIG;
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///
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/// ------------ General PCH Platform Policy PPI definition ------------
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///
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struct _PCH_PLATFORM_POLICY_PPI {
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UINT8 Revision;
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UINT8 BusNumber; // Bus Number of the PCH device
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UINT32 SpiBase; // SPI Base Address.
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UINT32 PmcBase; // PMC Base Address.
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UINT32 SmbmBase; // SMB Memory Base Address.
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UINT32 IoBase; // IO Base Address.
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UINT32 IlbBase; // Intel Legacy Block Base Address.
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UINT32 PUnitBase; // PUnit Base Address.
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UINT32 Rcba; // Root Complex Base Address.
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UINT32 MphyBase; // MPHY Base Address.
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UINT16 AcpiBase; // ACPI I/O Base address.
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UINT16 GpioBase; // GPIO Base address
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PCH_HPET_CONFIG *HpetConfig;
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PCH_SATA_MODE SataMode;
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PCH_PCIE_CONFIG *PcieConfig;
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PCH_IOAPIC_CONFIG *IoApicConfig;
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PEI_PCH_LPSS_CONFIG *LpssConfig;
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BOOLEAN EnableRmh; // Determines if enable USB RMH function
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BOOLEAN EhciPllCfgEnable;
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};
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#endif
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