7601b251fd
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
56 lines
1.4 KiB
ArmAsm
56 lines
1.4 KiB
ArmAsm
//------------------------------------------------------------------------------
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//
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// Set/Long jump for RISC-V
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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# define REG_S sd
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# define REG_L ld
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# define SZREG 8
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.align 3
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.globl SetJump
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SetJump:
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REG_S ra, 0*SZREG(a0)
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REG_S s0, 1*SZREG(a0)
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REG_S s1, 2*SZREG(a0)
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REG_S s2, 3*SZREG(a0)
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REG_S s3, 4*SZREG(a0)
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REG_S s4, 5*SZREG(a0)
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REG_S s5, 6*SZREG(a0)
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REG_S s6, 7*SZREG(a0)
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REG_S s7, 8*SZREG(a0)
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REG_S s8, 9*SZREG(a0)
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REG_S s9, 10*SZREG(a0)
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REG_S s10, 11*SZREG(a0)
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REG_S s11, 12*SZREG(a0)
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REG_S sp, 13*SZREG(a0)
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li a0, 0
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ret
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.globl InternalLongJump
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InternalLongJump:
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REG_L ra, 0*SZREG(a0)
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REG_L s0, 1*SZREG(a0)
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REG_L s1, 2*SZREG(a0)
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REG_L s2, 3*SZREG(a0)
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REG_L s3, 4*SZREG(a0)
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REG_L s4, 5*SZREG(a0)
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REG_L s5, 6*SZREG(a0)
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REG_L s6, 7*SZREG(a0)
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REG_L s7, 8*SZREG(a0)
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REG_L s8, 9*SZREG(a0)
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REG_L s9, 10*SZREG(a0)
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REG_L s10, 11*SZREG(a0)
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REG_L s11, 12*SZREG(a0)
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REG_L sp, 13*SZREG(a0)
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add a0, s0, 0
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add a1, s1, 0
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add a2, s2, 0
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add a3, s3, 0
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ret
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