2f88bd3a12
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
260 lines
9.0 KiB
C
260 lines
9.0 KiB
C
/** @file
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This file defines the Legacy SPI Controller Protocol.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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This Protocol was introduced in UEFI PI Specification 1.6.
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**/
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#ifndef __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
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#define __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
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///
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/// Note: The UEFI PI 1.6 specification uses the character 'l' in the GUID
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/// definition. This definition assumes it was supposed to be '1'.
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///
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/// Global ID for the Legacy SPI Controller Protocol
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///
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#define EFI_LEGACY_SPI_CONTROLLER_GUID \
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{ 0x39136fc7, 0x1a11, 0x49de, \
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{ 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}
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typedef
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struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;
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/**
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Set the erase block opcode.
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This routine must be called at or below TPL_NOTIFY.
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The menu table contains SPI transaction opcodes which are accessible after
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the legacy SPI flash controller's configuration is locked. The board layer
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specifies the erase block size for the SPI NOR flash part. The SPI NOR flash
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peripheral driver selects the erase block opcode which matches the erase
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block size and uses this API to load the opcode into the opcode menu table.
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@param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
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structure.
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@param[in] EraseBlockOpcode Erase block opcode to be placed into the opcode
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menu table.
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@retval EFI_SUCCESS The opcode menu table was updated
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@retval EFI_ACCESS_ERROR The SPI controller is locked
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**/
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typedef EFI_STATUS
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
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IN UINT8 EraseBlockOpcode
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);
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/**
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Set the write status prefix opcode.
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This routine must be called at or below TPL_NOTIFY.
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The prefix table contains SPI transaction write prefix opcodes which are
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accessible after the legacy SPI flash controller's configuration is locked.
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The board layer specifies the write status prefix opcode for the SPI NOR
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flash part. The SPI NOR flash peripheral driver uses this API to load the
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opcode into the prefix table.
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@param[in] This Pointer to an
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
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@param[in] WriteStatusPrefix Prefix opcode for the write status command.
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@retval EFI_SUCCESS The prefix table was updated
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@retval EFI_ACCESS_ERROR The SPI controller is locked
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
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IN UINT8 WriteStatusPrefix
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);
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/**
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Set the BIOS base address.
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This routine must be called at or below TPL_NOTIFY.
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The BIOS base address works with the protect range registers to protect
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portions of the SPI NOR flash from erase and write operat ions. The BIOS
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calls this API prior to passing control to the OS loader.
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@param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
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structure.
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@param[in] BiosBaseAddress The BIOS base address.
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@retval EFI_SUCCESS The BIOS base address was properly set
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@retval EFI_ACCESS_ERROR The SPI controller is locked
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@retval EFI_INVALID_PARAMETER The BIOS base address is greater than
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This->Maxi.mumOffset
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@retval EFI_UNSUPPORTED The BIOS base address was already set
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**/
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typedef EFI_STATUS
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
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IN UINT32 BiosBaseAddress
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);
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/**
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Clear the SPI protect range registers.
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This routine must be called at or below TPL_NOTIFY.
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The BIOS uses this routine to set an initial condition on the SPI protect
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range registers.
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@param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
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@retval EFI_SUCCESS The registers were successfully cleared
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@retval EFI_ACCESS_ERROR The SPI controller is locked
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This
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);
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/**
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Determine if the SPI range is protected.
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This routine must be called at or below TPL_NOTIFY.
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The BIOS uses this routine to verify a range in the SPI is protected.
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@param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
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structure.
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@param[in] BiosAddress Address within a 4 KiB block to start protecting.
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@param[in] BytesToProtect The number of 4 KiB blocks to protect.
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@retval TRUE The range is protected
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@retval FALSE The range is not protected
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**/
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typedef
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BOOLEAN
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
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IN UINT32 BiosAddress,
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IN UINT32 BlocksToProtect
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);
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/**
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Set the next protect range register.
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This routine must be called at or below TPL_NOTIFY.
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The BIOS sets the protect range register to prevent write and erase
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operations to a portion of the SPI NOR flash device.
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@param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
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structure.
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@param[in] BiosAddress Address within a 4 KiB block to start protecting.
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@param[in] BlocksToProtect The number of 4 KiB blocks to protect.
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@retval EFI_SUCCESS The register was successfully updated
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@retval EFI_ACCESS_ERROR The SPI controller is locked
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@retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or
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BlocksToProtect * 4 KiB
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> This->MaximumRangeBytes, or
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BiosAddress - This->BiosBaseAddress
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+ (BlocksToProtect * 4 KiB)
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> This->MaximumRangeBytes
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@retval EFI_OUT_OF_RESOURCES No protect range register available
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@retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS base
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address is not set
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
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IN UINT32 BiosAddress,
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IN UINT32 BlocksToProtect
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);
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/**
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Lock the SPI controller configuration.
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This routine must be called at or below TPL_NOTIFY.
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This routine locks the SPI controller's configuration so that the software
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is no longer able to update:
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* Prefix table
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* Opcode menu
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* Opcode type table
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* BIOS base address
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* Protect range registers
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@param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
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@retval EFI_SUCCESS The SPI controller was successfully locked
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@retval EFI_ALREADY_STARTED The SPI controller was already locked
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**/
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typedef EFI_STATUS
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(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER)(
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IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This
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);
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///
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/// Support the extra features of the legacy SPI flash controller.
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///
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struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL {
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///
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/// Maximum offset from the BIOS base address that is able to be protected.
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///
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UINT32 MaximumOffset;
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///
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/// Maximum number of bytes that can be protected by one range register.
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///
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UINT32 MaximumRangeBytes;
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///
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/// The number of registers available for protecting the BIOS.
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///
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UINT32 RangeRegisterCount;
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///
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/// Set the erase block opcode.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;
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///
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/// Set the write status prefix opcode.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;
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///
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/// Set the BIOS base address.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;
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///
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/// Clear the SPI protect range registers.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;
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///
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/// Determine if the SPI range is protected.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;
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///
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/// Set the next protect range register.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;
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///
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/// Lock the SPI controller configuration.
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///
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EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;
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};
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extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;
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#endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
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