git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@5758 6f19259b-4bc3-4df7-8a09-765794883524
		
			
				
	
	
		
			146 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			146 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /** @file
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| 
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|   The definition for UHCI driver model and HC protocol routines.
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| 
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| Copyright (c) 2004 - 2007, Intel Corporation
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| All rights reserved. This program and the accompanying materials
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| are licensed and made available under the terms and conditions of the BSD License
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| which accompanies this distribution.  The full text of the license may be found at
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| http://opensource.org/licenses/bsd-license.php
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| 
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| THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 
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| **/
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| 
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| #ifndef _EFI_UHCI_H_
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| #define _EFI_UHCI_H_
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| 
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| 
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| #include <Uefi.h>
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| 
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| #include <Protocol/Usb2HostController.h>
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| #include <Protocol/UsbHostController.h>
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| #include <Protocol/PciIo.h>
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| 
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| #include <Library/DebugLib.h>
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| #include <Library/BaseMemoryLib.h>
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| #include <Library/UefiDriverEntryPoint.h>
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| #include <Library/UefiBootServicesTableLib.h>
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| #include <Library/UefiLib.h>
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| #include <Library/BaseLib.h>
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| #include <Library/MemoryAllocationLib.h>
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| #include <Library/PcdLib.h>
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| 
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| #include <IndustryStandard/Pci22.h>
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| 
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| typedef struct _USB_HC_DEV  USB_HC_DEV;
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| 
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| #include "UsbHcMem.h"
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| #include "UhciQueue.h"
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| #include "UhciReg.h"
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| #include "UhciSched.h"
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| #include "UhciDebug.h"
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| 
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| typedef enum {
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|   UHC_1_MICROSECOND             = 1,
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|   UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,
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|   UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,
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| 
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|   //
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|   // UHCI register operation timeout, set by experience
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|   //
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|   UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,
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| 
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|   //
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|   // Wait for force global resume(FGR) complete, refers to
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|   // specification[UHCI11-2.1.1]
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|   //
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|   UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,
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| 
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|   //
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|   // Wait for roothub port reset and recovery, reset stall
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|   // is set by experience, and recovery stall refers to
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|   // specification[UHCI11-2.1.1]
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|   //
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|   UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,
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|   UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,
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| 
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|   //
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|   // Sync and Async transfer polling interval, set by experience,
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|   // and the unit of Async is 100us.
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|   //
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|   UHC_SYNC_POLL_INTERVAL        = 50 * UHC_1_MICROSECOND,
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|   UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL
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| }UHC_TIMEOUT_EXPERIENCE_VALUE;
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| 
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| 
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| //
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| // UHC raises TPL to TPL_NOTIFY to serialize all its operations
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| // to protect shared data structures.
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| //
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| #define  UHCI_TPL                     TPL_NOTIFY
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| 
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| #define  USB_HC_DEV_SIGNATURE         EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
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| 
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| #pragma pack(1)
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| typedef struct {
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|   UINT8               PI;
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|   UINT8               SubClassCode;
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|   UINT8               BaseCode;
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| } USB_CLASSC;
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| #pragma pack()
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| 
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| #define UHC_FROM_USB2_HC_PROTO(This)  CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
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| 
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| //
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| // USB_HC_DEV support the UHCI hardware controller. It schedules
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| // the asynchronous interrupt transfer with the same method as
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| // EHCI: a reversed tree structure. For synchronous interrupt,
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| // control and bulk transfer, it uses three static queue head to
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| // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is
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| // for LOW speed control transfer, and FsCtrlBulkQh is for FULL
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| // speed control or bulk transfer. This is because FULL speed contrl
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| // or bulk transfer can reclaim the unused bandwidth. Some USB
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| // device requires this bandwidth reclamation capability.
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| //
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| struct _USB_HC_DEV {
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|   UINT32                    Signature;
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|   EFI_USB2_HC_PROTOCOL      Usb2Hc;
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|   EFI_PCI_IO_PROTOCOL       *PciIo;
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|   UINT64                    OriginalPciAttributes;
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| 
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|   //
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|   // Schedule data structures
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|   //
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|   UINT32                    *FrameBase;
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|   UHCI_QH_SW                *SyncIntQh;
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|   UHCI_QH_SW                *CtrlQh;
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|   UHCI_QH_SW                *BulkQh;
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| 
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|   //
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|   // Structures to maintain asynchronus interrupt transfers.
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|   // When asynchronous interrutp transfer is unlinked from
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|   // the frame list, the hardware may still hold a pointer
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|   // to it. To synchronize with hardware, its resoureces are
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|   // released in two steps using Recycle and RecycleWait.
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|   // Check the asynchronous interrupt management routines.
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|   //
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|   LIST_ENTRY                AsyncIntList;
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|   EFI_EVENT                 AsyncIntMonitor;
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|   UHCI_ASYNC_REQUEST        *Recycle;
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|   UHCI_ASYNC_REQUEST        *RecycleWait;
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| 
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| 
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|   UINTN                     RootPorts;
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|   USBHC_MEM_POOL            *MemPool;
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|   EFI_UNICODE_STRING_TABLE  *CtrlNameTable;
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|   VOID                      *FrameMapping;
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| };
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| 
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| extern EFI_DRIVER_BINDING_PROTOCOL   gUhciDriverBinding;
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| extern EFI_COMPONENT_NAME_PROTOCOL   gUhciComponentName;
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| extern EFI_COMPONENT_NAME2_PROTOCOL  gUhciComponentName2;
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| 
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| #endif
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