3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PlatformBaseAddresses.h
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Abstract:
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Revision History
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++*/
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#ifndef _PLATFORM_BASE_ADDRESSES_H
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#define _PLATFORM_BASE_ADDRESSES_H
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//
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// Define some fixed platform device location information
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//
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//
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// Define platform base
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//
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//
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// SIO
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//
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#define SIO_BASE_ADDRESS 0x0680
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#define SIO_MONITORING_BASE_ADDRESS 0x0290
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#define SIO_BASE_MASK 0xFFF0
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#define WINDBOND_ECIR_BASE_ADDRESS 0x0810
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#define SIO_MAILBOX_BASE_ADDRESS 0x0360 // Used by EC controller
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#define SIO_EC_CHANNEL2 0x62 // Used by EC controller for offset 0x62 and 0x66
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//
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// South Cluster
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//
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#define ACPI_BASE_ADDRESS 0x0400
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#define GPIO_BASE_ADDRESS 0x0500
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#define SMBUS_BUS_DEV_FUNC 0x1F0300
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#define SMBUS_BASE_ADDRESS 0xEFA0 // SMBus IO Base Address
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#define SPI_BASE_ADDRESS 0xFED01000 // SPI Memory Base Address
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#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
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#define SMBM_BASE_ADDRESS 0xFED04000 // SMBus Memory Base Address
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#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
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#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address
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#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base Address
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#define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address
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#define MPHY_BASE_ADDRESS 0xFEF00000 // MPHY Memory Base Address
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#define PUNIT_BASE_ADDRESS 0xFED05000 // PUnit Memory Base Address
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//
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// GPIO GROUP OFFSET
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//
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#define GPIO_SCORE_OFFSET 0x0000
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#define GPIO_NCORE_OFFSET 0x1000
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#define GPIO_SSUS_OFFSET 0x2000
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//
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// MCH/CPU
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//
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#define DMI_BASE_ADDRESS 0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10
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#define EP_BASE_ADDRESS 0xFED19000
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#define MC_MMIO_BASE 0xFED14000 // Base Address for MMIO registers
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//
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// TPM
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//
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#define TPM_BASE_ADDRESS 0xFED40000 // Base address for TPM
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//
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// Local and I/O APIC addresses.
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//
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#define IO_APIC_ADDRESS 0xFEC00000
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#define IIO_IOAPIC_ADDRESS 0xFEC90000
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#define LOCAL_APIC_ADDRESS 0xFEE00000
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#endif
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