97eedf5dfb
Fix various typos in comments and documentation. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
336 lines
9.0 KiB
NASM
336 lines
9.0 KiB
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SecEntry.asm
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;
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; Abstract:
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;
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; This is the code that goes from real-mode to protected mode.
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; It consumes the reset vector, calls TempRamInit API from FSP binary.
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;
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;------------------------------------------------------------------------------
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#include "Fsp.h"
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SECTION .text
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extern ASM_PFX(CallPeiCoreEntryPoint)
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extern ASM_PFX(FsptUpdDataPtr)
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; Pcds
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extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
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;----------------------------------------------------------------------------
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;
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; Procedure: _ModuleEntryPoint
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;
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; Input: None
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;
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; Output: None
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;
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; Destroys: Assume all registers
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;
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; Description:
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;
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; Transition to non-paged flat-model protected mode from a
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; hard-coded GDT that provides exactly two descriptors.
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; This is a bare bones transition to protected mode only
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; used for a while in PEI and possibly DXE.
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;
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; After enabling protected mode, a far jump is executed to
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; transfer to PEI using the newly loaded GDT.
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;
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; Return: None
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;
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; MMX Usage:
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; MM0 = BIST State
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; MM5 = Save time-stamp counter value high32bit
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; MM6 = Save time-stamp counter value low32bit.
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;
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;----------------------------------------------------------------------------
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BITS 16
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align 4
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global ASM_PFX(ModuleEntryPoint)
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ASM_PFX(ModuleEntryPoint):
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fninit ; clear any pending Floating point exceptions
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;
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; Store the BIST value in mm0
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;
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movd mm0, eax
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;
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; Save time-stamp counter value
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; rdtsc load 64bit time-stamp counter to EDX:EAX
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;
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rdtsc
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movd mm5, edx
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movd mm6, eax
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;
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; Load the GDT table in GdtDesc
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;
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mov esi, GdtDesc
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DB 66h
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lgdt [cs:si]
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;
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; Transition to 16 bit protected mode
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;
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mov eax, cr0 ; Get control register 0
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or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
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mov cr0, eax ; Activate protected mode
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mov eax, cr4 ; Get control register 4
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or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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mov cr4, eax
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;
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; Now we're in 16 bit protected mode
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; Set up the selectors for 32 bit protected mode entry
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;
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mov ax, SYS_DATA_SEL
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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;
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; Transition to Flat 32 bit protected mode
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; The jump to a far pointer causes the transition to 32 bit mode
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;
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mov esi, ProtectedModeEntryLinearAddress
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jmp dword far [cs:si]
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;----------------------------------------------------------------------------
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;
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; Procedure: ProtectedModeEntryPoint
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;
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; Input: None
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;
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; Output: None
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;
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; Destroys: Assume all registers
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;
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; Description:
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;
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; This function handles:
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; Call two basic APIs from FSP binary
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; Initializes stack with some early data (BIST, PEI entry, etc)
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;
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; Return: None
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;
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;----------------------------------------------------------------------------
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BITS 32
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align 4
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ProtectedModeEntryPoint:
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; Find the fsp info header
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mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
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mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
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cmp eax, FVH_SIGINATURE_VALID_VALUE
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jnz FspHeaderNotFound
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xor eax, eax
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mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
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cmp ax, 0
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jnz FspFvExtHeaderExist
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xor eax, eax
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mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
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add edi, eax
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jmp FspCheckFfsHeader
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FspFvExtHeaderExist:
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add edi, eax
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mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
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add edi, eax
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; Round up to 8 byte alignment
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mov eax, edi
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and al, 07h
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jz FspCheckFfsHeader
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and edi, 0FFFFFFF8h
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add edi, 08h
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FspCheckFfsHeader:
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; Check the ffs guid
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mov eax, dword [edi]
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cmp eax, FSP_HEADER_GUID_DWORD1
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jnz FspHeaderNotFound
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mov eax, dword [edi + 4]
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cmp eax, FSP_HEADER_GUID_DWORD2
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jnz FspHeaderNotFound
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mov eax, dword [edi + 8]
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cmp eax, FSP_HEADER_GUID_DWORD3
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jnz FspHeaderNotFound
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mov eax, dword [edi + 0Ch]
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cmp eax, FSP_HEADER_GUID_DWORD4
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jnz FspHeaderNotFound
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add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
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; Check the section type as raw section
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mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
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cmp al, 019h
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jnz FspHeaderNotFound
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add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
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jmp FspHeaderFound
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FspHeaderNotFound:
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jmp $
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FspHeaderFound:
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; Get the fsp TempRamInit Api address
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mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
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add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
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; Setup the hardcode stack
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mov esp, TempRamInitStack
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; Call the fsp TempRamInit Api
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jmp eax
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TempRamInitDone:
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cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
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je CallSecFspInit ;If microcode not found, don't hang, but continue.
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cmp eax, 0 ;Check if EFI_SUCCESS returned.
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jnz FspApiFailed
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; ECX: start of range
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; EDX: end of range
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CallSecFspInit:
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xor eax, eax
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mov esp, edx
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; Align the stack at DWORD
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add esp, 3
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and esp, 0FFFFFFFCh
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push edx
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push ecx
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push eax ; zero - no hob list yet
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call ASM_PFX(CallPeiCoreEntryPoint)
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FspApiFailed:
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jmp $
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align 10h
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TempRamInitStack:
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DD TempRamInitDone
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DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
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;
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; ROM-based Global-Descriptor Table for the Tiano PEI Phase
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;
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align 16
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global ASM_PFX(BootGdtTable)
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;
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; GDT[0]: 0x00: Null entry, never used.
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;
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NULL_SEL EQU $ - GDT_BASE ; Selector [0]
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GDT_BASE:
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ASM_PFX(BootGdtTable):
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DD 0
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DD 0
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;
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; Linear data segment descriptor
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;
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LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
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DW 0FFFFh ; limit 0xFFFFF
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DW 0 ; base 0
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DB 0
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DB 092h ; present, ring 0, data, expand-up, writable
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DB 0CFh ; page-granular, 32-bit
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DB 0
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;
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; Linear code segment descriptor
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;
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LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
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DW 0FFFFh ; limit 0xFFFFF
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DW 0 ; base 0
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DB 0
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DB 09Bh ; present, ring 0, data, expand-up, not-writable
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DB 0CFh ; page-granular, 32-bit
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DB 0
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;
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; System data segment descriptor
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;
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SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
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DW 0FFFFh ; limit 0xFFFFF
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DW 0 ; base 0
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DB 0
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DB 093h ; present, ring 0, data, expand-up, not-writable
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DB 0CFh ; page-granular, 32-bit
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DB 0
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;
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; System code segment descriptor
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;
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SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
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DW 0FFFFh ; limit 0xFFFFF
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DW 0 ; base 0
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DB 0
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DB 09Ah ; present, ring 0, data, expand-up, writable
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DB 0CFh ; page-granular, 32-bit
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DB 0
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;
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; Spare segment descriptor
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;
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SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
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DW 0FFFFh ; limit 0xFFFFF
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DW 0 ; base 0
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DB 0Eh ; Changed from F000 to E000.
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DB 09Bh ; present, ring 0, code, expand-up, writable
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DB 00h ; byte-granular, 16-bit
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DB 0
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;
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; Spare segment descriptor
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;
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SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
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DW 0FFFFh ; limit 0xFFFF
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DW 0 ; base 0
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DB 0
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DB 093h ; present, ring 0, data, expand-up, not-writable
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DB 00h ; byte-granular, 16-bit
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DB 0
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;
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; Spare segment descriptor
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;
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SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
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DW 0 ; limit 0
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DW 0 ; base 0
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DB 0
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DB 0 ; present, ring 0, data, expand-up, writable
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DB 0 ; page-granular, 32-bit
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DB 0
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GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
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;
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; GDT Descriptor
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;
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GdtDesc: ; GDT descriptor
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DW GDT_SIZE - 1 ; GDT limit
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DD GDT_BASE ; GDT base address
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ProtectedModeEntryLinearAddress:
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ProtectedModeEntryLinear:
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DD ProtectedModeEntryPoint ; Offset of our 32 bit code
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DW LINEAR_CODE_SEL
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