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The ARM architecture provides no reliable way to clean or invalidate the entire data cache at runtime. The reason is that such maintenance requires the use of set/way maintenance operations, which are suitable only for the kind of maintenance that is carried out when the cache is taken offline entirely. So ASSERT () when any of the CacheMaintenanceLib whole data cache routines are invoked rather than pretending we can do anything meaningful here. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18756 6f19259b-4bc3-4df7-8a09-765794883524