Ard Biesheuvel f977e6500a ArmCacheMaintenanceLib: disallow whole D-cache maintenance operations
The ARM architecture provides no reliable way to clean or invalidate
the entire data cache at runtime. The reason is that such maintenance
requires the use of set/way maintenance operations, which are suitable
only for the kind of maintenance that is carried out when the cache is
taken offline entirely.

So ASSERT () when any of the CacheMaintenanceLib whole data cache routines
are invoked rather than pretending we can do anything meaningful here.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18756 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:27:36 +00:00

122 lines
2.6 KiB
C

/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
VOID
CacheRangeOperation (
IN VOID *Start,
IN UINTN Length,
IN LINE_OPERATION LineOperation
)
{
UINTN ArmCacheLineLength = ArmDataCacheLineLength();
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
ArmDataSynchronizationBarrier ();
}
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
ArmInvalidateInstructionCache();
}
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
ASSERT (FALSE);
}
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
ArmInvalidateInstructionCache ();
return Address;
}
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
ASSERT (FALSE);
}
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);
return Address;
}
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
ASSERT (FALSE);
}
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);
return Address;
}
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);
return Address;
}