Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
		
			
				
	
	
		
			130 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			130 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /** @file
 | |
| 
 | |
| Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
 | |
| 
 | |
| This program and the accompanying materials
 | |
| are licensed and made available under the terms and conditions
 | |
| of the BSD License which accompanies this distribution.  The
 | |
| full text of the license may be found at
 | |
| http://opensource.org/licenses/bsd-license.php
 | |
| 
 | |
| THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 | |
| WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 | |
| 
 | |
| **/
 | |
| 
 | |
| #ifndef _CAPSULE_PEIM_H_
 | |
| #define _CAPSULE_PEIM_H_
 | |
| 
 | |
| #include <PiPei.h>
 | |
| #include <Uefi/UefiSpec.h>
 | |
| 
 | |
| #include <Ppi/Capsule.h>
 | |
| #include <Ppi/LoadFile.h>
 | |
| #include <Ppi/ReadOnlyVariable2.h>
 | |
| #include <Guid/CapsuleVendor.h>
 | |
| 
 | |
| #include <Library/BaseLib.h>
 | |
| #include <Library/DebugLib.h>
 | |
| #include <Library/PeimEntryPoint.h>
 | |
| #include <Library/PeiServicesLib.h>
 | |
| #include <Library/BaseMemoryLib.h>
 | |
| #include <Library/HobLib.h>
 | |
| #include <Library/PeiServicesTablePointerLib.h>
 | |
| #include <Library/PrintLib.h>
 | |
| #include <Library/PeCoffLib.h>
 | |
| #include <Library/PeCoffGetEntryPointLib.h>
 | |
| #include <Library/PcdLib.h>
 | |
| #include <Library/ReportStatusCodeLib.h>
 | |
| #include <Library/DebugAgentLib.h>
 | |
| #include <IndustryStandard/PeImage.h>
 | |
| #include "Common/CommonHeader.h"
 | |
| 
 | |
| #ifdef MDE_CPU_IA32 
 | |
| 
 | |
| #pragma pack(1)
 | |
| 
 | |
| //
 | |
| // Page-Map Level-4 Offset (PML4) and
 | |
| // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
 | |
| //
 | |
| 
 | |
| typedef union {
 | |
|   struct {
 | |
|     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 | |
|     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 | |
|     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 | |
|     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 | |
|     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 | |
|     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 | |
|     UINT64  Reserved:1;               // Reserved
 | |
|     UINT64  MustBeZero:2;             // Must Be Zero
 | |
|     UINT64  Available:3;              // Available for use by system software
 | |
|     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
 | |
|     UINT64  AvabilableHigh:11;        // Available for use by system software
 | |
|     UINT64  Nx:1;                     // No Execute bit
 | |
|   } Bits;
 | |
|   UINT64    Uint64;
 | |
| } PAGE_MAP_AND_DIRECTORY_POINTER;
 | |
| 
 | |
| //
 | |
| // Page Table Entry 2MB
 | |
| //
 | |
| typedef union {
 | |
|   struct {
 | |
|     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 | |
|     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 | |
|     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 | |
|     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 | |
|     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 | |
|     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 | |
|     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 | |
|     UINT64  MustBe1:1;                // Must be 1 
 | |
|     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 | |
|     UINT64  Available:3;              // Available for use by system software
 | |
|     UINT64  PAT:1;                    //
 | |
|     UINT64  MustBeZero:8;             // Must be zero;
 | |
|     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
 | |
|     UINT64  AvabilableHigh:11;        // Available for use by system software
 | |
|     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 | |
|   } Bits;
 | |
|   UINT64    Uint64;
 | |
| } PAGE_TABLE_ENTRY;
 | |
| 
 | |
| //
 | |
| // Page Table Entry 1GB
 | |
| //
 | |
| typedef union {
 | |
|   struct {
 | |
|     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 | |
|     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 | |
|     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 | |
|     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 | |
|     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 | |
|     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 | |
|     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 | |
|     UINT64  MustBe1:1;                // Must be 1 
 | |
|     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 | |
|     UINT64  Available:3;              // Available for use by system software
 | |
|     UINT64  PAT:1;                    //
 | |
|     UINT64  MustBeZero:17;            // Must be zero;
 | |
|     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 | |
|     UINT64  AvabilableHigh:11;        // Available for use by system software
 | |
|     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 | |
|   } Bits;
 | |
|   UINT64    Uint64;
 | |
| } PAGE_TABLE_1G_ENTRY;
 | |
| 
 | |
| #pragma pack()
 | |
| 
 | |
| typedef
 | |
| EFI_STATUS
 | |
| (*COALESCE_ENTRY) (
 | |
|   SWITCH_32_TO_64_CONTEXT       *EntrypointContext,
 | |
|   SWITCH_64_TO_32_CONTEXT       *ReturnContext
 | |
|   );
 | |
| 
 | |
| #endif
 | |
| 
 | |
| #endif
 |