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gaze17: Define SLP_S0# to CPU_C10_GATE#

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gaze17 does not connect SLP_S0# to the EC, so continue using
CPU_C10_GATE# for S0ix detection.

Fixes: 4b888ae9a501 ("board/system76/common: use SLP_S0# pin for modern standby detection")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-08-08 09:02:30 -06:00
committed by Tim Crawford
parent cc3effb6a4
commit 5cf57d69b9
4 changed files with 4 additions and 0 deletions
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1
src/board/system76/gaze17-3050/gpio.c
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@ -25,6 +25,7 @@ struct Gpio __code PCH_DPWROK_EC = GPIO(H, 4);
struct Gpio __code PCH_PWROK_EC = GPIO(F, 3); struct Gpio __code PCH_PWROK_EC = GPIO(F, 3);
struct Gpio __code PWR_BTN_N = GPIO(D, 5); struct Gpio __code PWR_BTN_N = GPIO(D, 5);
struct Gpio __code PWR_SW_N = GPIO(B, 3); struct Gpio __code PWR_SW_N = GPIO(B, 3);
struct Gpio __code SLP_S0_N = GPIO(C, 6); // XXX: Really CPU_C10_GATE#
struct Gpio __code SLP_SUS_N = GPIO(J, 4); struct Gpio __code SLP_SUS_N = GPIO(J, 4);
struct Gpio __code SUSB_N_PCH = GPIO(H, 6); struct Gpio __code SUSB_N_PCH = GPIO(H, 6);
struct Gpio __code SUSC_N_PCH = GPIO(H, 1); struct Gpio __code SUSC_N_PCH = GPIO(H, 1);

1
src/board/system76/gaze17-3050/include/board/gpio.h
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@ -32,6 +32,7 @@ extern struct Gpio __code PCH_PWROK_EC;
#define HAVE_PM_PWROK 0 #define HAVE_PM_PWROK 0
extern struct Gpio __code PWR_BTN_N; extern struct Gpio __code PWR_BTN_N;
extern struct Gpio __code PWR_SW_N; extern struct Gpio __code PWR_SW_N;
extern struct Gpio __code SLP_S0_N;
extern struct Gpio __code SLP_SUS_N; extern struct Gpio __code SLP_SUS_N;
#define HAVE_SUS_PWR_ACK 0 #define HAVE_SUS_PWR_ACK 0
extern struct Gpio __code SUSB_N_PCH; extern struct Gpio __code SUSB_N_PCH;

1
src/board/system76/gaze17-3060/gpio.c
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@ -25,6 +25,7 @@ struct Gpio __code PCH_DPWROK_EC = GPIO(F, 3);
struct Gpio __code PCH_PWROK_EC = GPIO(C, 6); struct Gpio __code PCH_PWROK_EC = GPIO(C, 6);
struct Gpio __code PWR_BTN_N = GPIO(D, 5); struct Gpio __code PWR_BTN_N = GPIO(D, 5);
struct Gpio __code PWR_SW_N = GPIO(B, 3); struct Gpio __code PWR_SW_N = GPIO(B, 3);
struct Gpio __code SLP_S0_N = GPIO(J, 2); // XXX: Really CPU_C10_GATE#
struct Gpio __code SLP_SUS_N = GPIO(J, 7); struct Gpio __code SLP_SUS_N = GPIO(J, 7);
struct Gpio __code SUSB_N_PCH = GPIO(H, 6); struct Gpio __code SUSB_N_PCH = GPIO(H, 6);
struct Gpio __code SUSC_N_PCH = GPIO(H, 1); struct Gpio __code SUSC_N_PCH = GPIO(H, 1);

1
src/board/system76/gaze17-3060/include/board/gpio.h
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@ -32,6 +32,7 @@ extern struct Gpio __code PCH_PWROK_EC;
#define HAVE_PM_PWROK 0 #define HAVE_PM_PWROK 0
extern struct Gpio __code PWR_BTN_N; extern struct Gpio __code PWR_BTN_N;
extern struct Gpio __code PWR_SW_N; extern struct Gpio __code PWR_SW_N;
extern struct Gpio __code SLP_S0_N;
extern struct Gpio __code SLP_SUS_N; extern struct Gpio __code SLP_SUS_N;
#define HAVE_SUS_PWR_ACK 0 #define HAVE_SUS_PWR_ACK 0
extern struct Gpio __code SUSB_N_PCH; extern struct Gpio __code SUSB_N_PCH;