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Use BIT macro

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Mostly done with the cocci script. macro.h was then added manually.
This commit is contained in:
Tim Crawford 2021-02-24 07:52:42 -07:00 committed by Jeremy Soller
parent 9a3ecba010
commit 720af4b2b0
36 changed files with 188 additions and 154 deletions
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21
src/arch/avr/i2c.c
View File

@ -6,6 +6,7 @@
#include <board/cpu.h>
#include <common/i2c.h>
#include <common/macro.h>
#define TIMEOUT (F_CPU/1000)
@ -15,10 +16,10 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) {
// reset TWI control register
TWCR = 0;
// transmit START condition
TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
TWCR = BIT(TWINT) | BIT(TWSTA) | BIT(TWEN);
// wait for end of transmission
count = TIMEOUT;
while(!(TWCR & (1<<TWINT)) && count > 0) count -= 1;
while(!(TWCR & BIT(TWINT)) && count > 0) count -= 1;
if (count == 0) return -1;
// check if the start condition was successfully transmitted
@ -27,10 +28,10 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) {
// load slave addr into data register
TWDR = ((addr << 1) | read);
// start transmission of addr
TWCR = (1<<TWINT) | (1<<TWEN);
TWCR = BIT(TWINT) | BIT(TWEN);
// wait for end of transmission
count = TIMEOUT;
while(!(TWCR & (1<<TWINT)) && count > 0) count -= 1;
while(!(TWCR & BIT(TWINT)) && count > 0) count -= 1;
if (count == 0) return -1;
// check if the device has acknowledged the READ / WRITE mode
@ -42,7 +43,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) {
void i2c_stop(struct I2C * i2c) {
// transmit STOP condition
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
TWCR = BIT(TWINT) | BIT(TWEN) | BIT(TWSTO);
}
int i2c_write(struct I2C * i2c, uint8_t * data, int length) {
@ -51,10 +52,10 @@ int i2c_write(struct I2C * i2c, uint8_t * data, int length) {
// load data into data register
TWDR = data[i];
// start transmission of data
TWCR = (1<<TWINT) | (1<<TWEN);
TWCR = BIT(TWINT) | BIT(TWEN);
// wait for end of transmission
uint32_t count = TIMEOUT;
while(!(TWCR & (1<<TWINT)) && count > 0) count -= 1;
while(!(TWCR & BIT(TWINT)) && count > 0) count -= 1;
// timed out
if (count == 0) return -1;
// failed to receive ack
@ -69,14 +70,14 @@ int i2c_read(struct I2C * i2c, uint8_t * data, int length) {
for (i = 0; i < length; i++) {
if ((i + 1) < length) {
// start TWI module and acknowledge data after reception
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWEA);
TWCR = BIT(TWINT) | BIT(TWEN) | BIT(TWEA);
} else {
// start receiving without acknowledging reception
TWCR = (1<<TWINT) | (1<<TWEN);
TWCR = BIT(TWINT) | BIT(TWEN);
}
// wait for end of transmission
uint32_t count = TIMEOUT;
while(!(TWCR & (1<<TWINT)) && count > 0) count -= 1;
while(!(TWCR & BIT(TWINT)) && count > 0) count -= 1;
if (count == 0) return -1;
// return received data from TWDR
data[i] = TWDR;

15
src/arch/avr/i2c_slave.c
View File

@ -9,6 +9,7 @@
#include <board/cpu.h>
#include <arch/i2c_slave.h>
#include <common/macro.h>
static void (* volatile i2c_slave_new_cb)() = NULL;
static void (* volatile i2c_slave_recv_cb)(uint8_t) = NULL;
@ -28,7 +29,7 @@ void i2c_slave_init(uint8_t address, void (*new_cb)(), void (*recv_cb)(uint8_t),
// load address into TWI address register
TWAR = (address << 1);
// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
TWCR = (1<<TWIE) | (1<<TWEA) | (1<<TWINT) | (1<<TWEN);
TWCR = BIT(TWIE) | BIT(TWEA) | BIT(TWINT) | BIT(TWEN);
// set interrupts
sei();
@ -39,7 +40,7 @@ void i2c_slave_stop(){
cli();
// clear acknowledge and enable bits
TWCR &= ~((1<<TWEA) | (1<<TWEN));
TWCR &= ~(BIT(TWEA) | BIT(TWEN));
// clear address
TWAR = 0;
// remove callbacks
@ -59,14 +60,14 @@ ISR(TWI_vect) {
if (i2c_slave_new_cb != NULL) {
i2c_slave_new_cb();
}
TWCR = (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
TWCR = BIT(TWIE) | BIT(TWINT) | BIT(TWEA) | BIT(TWEN);
break;
case TW_SR_DATA_ACK:
// received data from master, call the receive callback
if(i2c_slave_send_cb != NULL){
i2c_slave_recv_cb(TWDR);
}
TWCR = (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
TWCR = BIT(TWIE) | BIT(TWINT) | BIT(TWEA) | BIT(TWEN);
break;
case TW_ST_SLA_ACK:
case TW_ST_DATA_ACK:
@ -74,16 +75,16 @@ ISR(TWI_vect) {
if(i2c_slave_recv_cb != NULL) {
TWDR = i2c_slave_send_cb();
}
TWCR = (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
TWCR = BIT(TWIE) | BIT(TWINT) | BIT(TWEA) | BIT(TWEN);
break;
case TW_BUS_ERROR:
// some sort of erroneous state, prepare TWI to be readdressed
printf("TWI_vect bus error\n");
TWCR = 0;
TWCR = (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
TWCR = BIT(TWIE) | BIT(TWINT) | BIT(TWEA) | BIT(TWEN);
break;
default:
TWCR = (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
TWCR = BIT(TWIE) | BIT(TWINT) | BIT(TWEA) | BIT(TWEN);
break;
}
}

4
src/arch/avr/include/arch/gpio.h
View File

@ -3,6 +3,8 @@
#ifndef _ARCH_GPIO_H
#define _ARCH_GPIO_H
#include <common/macro.h>
#include <avr/io.h>
#include <stdbool.h>
#include <stdint.h>
@ -18,7 +20,7 @@ struct Gpio {
.pin = &PIN ## BLOCK, \
.ddr = &DDR ## BLOCK, \
.port = &PORT ## BLOCK, \
.value = (1 << NUMBER), \
.value = BIT(NUMBER), \
}
bool gpio_get(struct Gpio * gpio);

10
src/board/system76/addw1/gpio.c
View File

@ -46,20 +46,20 @@ void gpio_init() {
// Set GPIO data
// SYS_FAN
GPDRA = (1 << 3);
GPDRA = BIT(3);
GPDRB = 0x00;
GPDRC = 0x00;
// PWR_BTN#, SCI#, SMI#
GPDRD = (1 << 5) | (1 << 4) | (1 << 3);
GPDRD = BIT(5) | BIT(4) | BIT(3);
GPDRE = 0x00;
// H_PECI
GPDRF = (1 << 6);
GPDRF = BIT(6);
// AIRPLAN_LED#
GPDRG = (1 << 6);
GPDRG = BIT(6);
GPDRH = 0x00;
GPDRI = 0x00;
// LED_CAP#, LED_NUM#, LED_SCROLL#, KBC_MUTE#
GPDRJ = (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1);
GPDRJ = BIT(5) | BIT(4) | BIT(3) | BIT(1);
// Set GPIO control
// EC_PWM_LEDKB_P

16
src/board/system76/addw2/gpio.c
View File

@ -42,28 +42,28 @@ void gpio_init() {
// Enable LPC reset on GPD2
GCR = 0x04;
// Enable SMBus channel 4
GCR15 = (1 << 4);
GCR15 = BIT(4);
// Set GPF2 and GPF3 to 3.3V
GCR20 = 0;
// Set GPIO data
GPDRA = 0x00;
// XLP_OUT, PWR_SW#
GPDRB = (1 << 4) | (1 << 3);
GPDRB = BIT(4) | BIT(3);
GPDRC = 0x00;
// PWR_BTN#, SCI#, SMI#
GPDRD = (1 << 5) | (1 << 4) | (1 << 3);
GPDRD = BIT(5) | BIT(4) | BIT(3);
// PLVDD_RST_EC
GPDRE = (1 << 6);
GPDRE = BIT(6);
// EC_PECI
GPDRF = (1 << 6);
GPDRF = BIT(6);
// H_PROCHOT#_EC, LED_NUM#
GPDRG = (1 << 6) | (1 << 0);
GPDRG = BIT(6) | BIT(0);
// AIRPLAN_LED#
GPDRH = 0x80; // (1 << 7)
GPDRH = BIT(7);
GPDRI = 0x00;
// LED_SCROLL#, LED_CAP#
GPDRJ = (1 << 3) | (1 << 2);
GPDRJ = BIT(3) | BIT(2);
// Set GPIO control
// EC_PWM_LEDKB_P

2
src/board/system76/bonw14/gpio.c
View File

@ -43,7 +43,7 @@ void gpio_init() {
// Enable LPC reset on GPD2
GCR = 0x04;
// Enable SMBus channel 4
GCR15 = (1 << 4);
GCR15 = BIT(4);
// Set GPF2 and GPF3 to 3.3V
GCR20 = 0;

17
src/board/system76/common/acpi.c
View File

@ -7,6 +7,7 @@
#include <board/kbled.h>
#include <board/lid.h>
#include <board/peci.h>
#include <common/macro.h>
#include <common/debug.h>
#include <ec/pwm.h>
@ -86,10 +87,10 @@ uint8_t acpi_read(uint8_t addr) {
case 0x03:
if (gpio_get(&LID_SW_N)) {
// Lid is open
data |= 1 << 0;
data |= BIT(0);
}
if (lid_wake) {
data |= 1 << 2;
data |= BIT(2);
}
break;
@ -99,11 +100,11 @@ uint8_t acpi_read(uint8_t addr) {
case 0x10:
if (!gpio_get(&ACIN_N)) {
// AC adapter connected
data |= 1 << 0;
data |= BIT(0);
}
if (battery_status & BATTERY_INITIALIZED) {
// BAT0 connected
data |= 1 << 2;
data |= BIT(2);
}
break;
@ -117,7 +118,7 @@ uint8_t acpi_read(uint8_t addr) {
// And battery is not fully charged
if (battery_current != 0) {
// Battery is charging
data |= 1 << 1;
data |= BIT(1);
}
}
break;
@ -152,7 +153,7 @@ uint8_t acpi_read(uint8_t addr) {
// Airplane mode LED
case 0xD9:
if (!gpio_get(&LED_AIRPLANE_N)) {
data |= (1 << 6);
data |= BIT(6);
}
break;
#endif // HAVE_LED_AIRPLANE_N
@ -178,7 +179,7 @@ void acpi_write(uint8_t addr, uint8_t data) {
switch (addr) {
// Lid state and other flags
case 0x03:
lid_wake = (bool)(data & (1 << 2));
lid_wake = (bool)(data & BIT(2));
break;
case 0x68:
@ -196,7 +197,7 @@ void acpi_write(uint8_t addr, uint8_t data) {
#if HAVE_LED_AIRPLANE_N
// Airplane mode LED
case 0xD9:
gpio_set(&LED_AIRPLANE_N, !(bool)(data & (1 << 6)));
gpio_set(&LED_AIRPLANE_N, !(bool)(data & BIT(6)));
break;
#endif

5
src/board/system76/common/charger/bq24780s.c
View File

@ -5,17 +5,18 @@
#include <board/battery.h>
#include <board/smbus.h>
#include <common/macro.h>
#include <common/debug.h>
// ChargeOption0 flags
// Low Power Mode Enable
#define SBC_EN_LWPWR ((uint16_t)(1 << 15))
#define SBC_EN_LWPWR ((uint16_t)(BIT(15)))
// Watchdog Timer Adjust
#define SBC_WDTMR_ADJ_175S ((uint16_t)(0b11 << 13))
// Switching Frequency
#define SBC_PWM_FREQ_800KHZ ((uint16_t)(0b01 << 8))
// IDCHG Amplifier Gain
#define SBC_IDCHC_GAIN ((uint16_t)(1 << 3))
#define SBC_IDCHC_GAIN ((uint16_t)(BIT(3)))
// XXX: Assumption: ac_last is initialized high.
static bool charger_enabled = false;

7
src/board/system76/common/ecpm.c
View File

@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-3.0-only
#include <board/ecpm.h>
#include <common/macro.h>
void ecpm_init(void) {
// Clock gate EGPC, CIR, and SWUC
CGCTRL2 |= (1 << 6) | (1 << 5) | (1 << 4);
CGCTRL2 |= BIT(6) | BIT(5) | BIT(4);
// Clock gate UART, SSPI, and DBGR
CGCTRL3 |= (1 << 2) | (1 << 1) | (1 << 0);
CGCTRL3 |= BIT(2) | BIT(1) | BIT(0);
// Clock gate CEC
CGCTRL4 |= (1 << 0);
CGCTRL4 |= BIT(0);
}

4
src/board/system76/common/include/board/battery.h
View File

@ -3,6 +3,8 @@
#ifndef _BOARD_BATTERY_H
#define _BOARD_BATTERY_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -14,7 +16,7 @@
#define CHARGER_ADDRESS 0x09
#endif
#define BATTERY_INITIALIZED (1U << 7)
#define BATTERY_INITIALIZED BIT(7)
extern uint16_t battery_temp;
extern uint16_t battery_voltage;

21
src/board/system76/common/kbscan.c
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@ -11,6 +11,7 @@
#include <board/lid.h>
#include <board/pmc.h>
#include <board/power.h>
#include <common/macro.h>
#include <common/debug.h>
// Default to not n-key rollover
@ -67,7 +68,7 @@ static uint8_t kbscan_get_row(int i) {
// Set current line as output
if (i < 8) {
KSOLGOEN = 1 << i;
KSOLGOEN = BIT(i);
KSOHGOEN = 0;
#if KM_OUT >= 17
GPCRC3 = GPIO_IN;
@ -77,7 +78,7 @@ static uint8_t kbscan_get_row(int i) {
#endif
} else if (i < 16) {
KSOLGOEN = 0;
KSOHGOEN = 1 << (i - 8);
KSOHGOEN = BIT((i - 8));
#if KM_OUT >= 17
GPCRC3 = GPIO_IN;
#endif
@ -104,10 +105,10 @@ static uint8_t kbscan_get_row(int i) {
#endif
}
#if KM_OUT >= 17
GPDRC &= ~(1 << 3);
GPDRC &= ~BIT(3);
#endif
#if KM_OUT >= 18
GPDRC &= ~(1 << 5);
GPDRC &= ~BIT(5);
#endif
// TODO: figure out optimal delay
@ -134,8 +135,8 @@ static uint8_t kbscan_get_real_keys(int row, uint8_t rowdata) {
for (uint8_t col = 0; col < KM_IN; col++) {
// This tests the default keymap intentionally, to avoid blanks in the
// dynamic keymap
if (KEYMAP[0][row][col] && (rowdata & (1 << col))) {
realdata |= 1 << col;
if (KEYMAP[0][row][col] && (rowdata & BIT(col))) {
realdata |= BIT(col);
}
}
@ -332,8 +333,8 @@ void kbscan_event(void) {
// A key was pressed or released
int j;
for (j = 0; j < KM_IN; j++) {
bool new_b = new & (1 << j);
bool last_b = last & (1 << j);
bool new_b = new & BIT(j);
bool last_b = last & BIT(j);
if (new_b != last_b) {
bool reset = false;
@ -385,9 +386,9 @@ void kbscan_event(void) {
// Reset bit to last state
if (reset) {
if (last_b) {
new |= (1 << j);
new |= BIT(j);
} else {
new &= ~(1 << j);
new &= ~BIT(j);
}
}
}

11
src/board/system76/common/parallel.c
View File

@ -3,6 +3,7 @@
#include <arch/delay.h>
#include <arch/time.h>
#include <board/parallel.h>
#include <common/macro.h>
#include <ec/kbscan.h>
#include <stdbool.h>
@ -18,12 +19,12 @@
* nWAIT = KSOH[1]
*/
#define CTL_WRITE (1 << 0)
#define CTL_DATA (1 << 1)
#define CTL_RESET (1 << 2)
#define CTL_ADDR (1 << 3)
#define CTL_WRITE BIT(0)
#define CTL_DATA BIT(1)
#define CTL_RESET BIT(2)
#define CTL_ADDR BIT(3)
#define STS_WAIT (1 << 1)
#define STS_WAIT BIT(1)
// Maximum peripheral response time in ms
#define PARALLEL_TIMEOUT 10

10
src/board/system76/common/peci.c
View File

@ -59,7 +59,7 @@ static struct Fan __code FAN = {
void peci_init(void) {
// Allow PECI pin to be used
GCR2 |= (1 << 4);
GCR2 |= BIT(4);
// Set frequency to 1MHz
HOCTL2R = 0x01;
@ -76,7 +76,7 @@ int peci_wr_pkg_config(uint8_t index, uint16_t param, uint32_t data) {
HOSTAR = HOSTAR;
// Enable PECI, clearing data fifo's, enable AW_FCS
HOCTLR = (1 << 5) | (1 << 3) | (1 << 1);
HOCTLR = BIT(5) | BIT(3) | BIT(1);
// Set address to default
HOTRADDR = 0x30;
// Set write length
@ -106,7 +106,7 @@ int peci_wr_pkg_config(uint8_t index, uint16_t param, uint32_t data) {
while (HOSTAR & 1) {}
int status = (int)HOSTAR;
if (status & (1 << 1)) {
if (status & BIT(1)) {
int cc = (int)HORDDR;
if (cc & 0x80) {
return -cc;
@ -137,7 +137,7 @@ uint8_t peci_get_fan_duty(void) {
HOSTAR = HOSTAR;
// Enable PECI, clearing data fifo's
HOCTLR = (1 << 5) | (1 << 3);
HOCTLR = BIT(5) | BIT(3);
// Set address to default
HOTRADDR = 0x30;
// Set write length
@ -152,7 +152,7 @@ uint8_t peci_get_fan_duty(void) {
// Wait for completion
while (HOSTAR & 1) {}
if (HOSTAR & (1 << 1)) {
if (HOSTAR & BIT(1)) {
// Use result if finished successfully
uint8_t low = HORDDR;
uint8_t high = HORDDR;

9
src/board/system76/common/pmc.c
View File

@ -4,6 +4,7 @@
#include <board/acpi.h>
#include <board/gpio.h>
#include <board/pmc.h>
#include <common/macro.h>
#include <common/debug.h>
#include <ec/espi.h>
@ -54,7 +55,7 @@ static void pmc_sci_interrupt(void) {
bool pmc_sci(struct Pmc * pmc, uint8_t sci) {
// Set SCI pending bit
pmc_set_status(pmc, pmc_status(pmc) | (1 << 5));
pmc_set_status(pmc, pmc_status(pmc) | BIT(5));
// Send SCI
pmc_sci_interrupt();
@ -107,7 +108,7 @@ static void pmc_on_input_command(struct Pmc * pmc, uint8_t data) {
case 0x82:
TRACE(" burst enable\n");
// Set burst bit
pmc_set_status(pmc, pmc_status(pmc) | (1 << 4));
pmc_set_status(pmc, pmc_status(pmc) | BIT(4));
// Send acknowledgement byte
state = PMC_STATE_WRITE;
state_data = 0x90;
@ -115,14 +116,14 @@ static void pmc_on_input_command(struct Pmc * pmc, uint8_t data) {
case 0x83:
TRACE(" burst disable\n");
// Clear burst bit
pmc_set_status(pmc, pmc_status(pmc) & ~(1 << 4));
pmc_set_status(pmc, pmc_status(pmc) & ~BIT(4));
// Send SCI for IBF=0
pmc_sci_interrupt();
break;
case 0x84:
TRACE(" SCI queue\n");
// Clear SCI pending bit
pmc_set_status(pmc, pmc_status(pmc) & ~(1 << 5));
pmc_set_status(pmc, pmc_status(pmc) & ~BIT(5));
// Send SCI queue
state = PMC_STATE_WRITE;
state_data = pmc_sci_queue;

5
src/board/system76/common/pnp.c
View File

@ -2,6 +2,7 @@
#include <stdint.h>
#include <common/macro.h>
#include <common/debug.h>
#include <ec/espi.h>
@ -10,12 +11,12 @@ volatile uint8_t __xdata __at(0x1201) IHD;
volatile uint8_t __xdata __at(0x1204) IBMAE;
volatile uint8_t __xdata __at(0x1205) IBCTL;
void e2ci_write(uint8_t port, uint8_t data) {
while (IBCTL & ((1 << 2) | (1 << 1))) {}
while (IBCTL & (BIT(2) | BIT(1))) {}
IHIOA = port;
IHD = data;
IBMAE = 1;
IBCTL = 1;
while (IBCTL & (1 << 2)) {}
while (IBCTL & BIT(2)) {}
IBMAE = 0;
IBCTL = 0;
}

3
src/board/system76/common/pwm.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-3.0-only
#include <board/pwm.h>
#include <common/macro.h>
void pwm_init(void) {
// Set T0CHSEL to TACH0A and T1CHSEL to TACH1A
@ -26,5 +27,5 @@ void pwm_init(void) {
DCR2 = 0;
// Enable PWM
ZTIER = (1 << 1);
ZTIER = BIT(1);
}

6
src/board/system76/common/smfi.c
View File

@ -96,10 +96,10 @@ void smfi_init(void) {
HRAMW1AAS = 0x34;
// Enable H2RAM window 0 and 1 using LPC I/O
HRAMWC |= (1 << 4) | (1 << 1) | (1 << 0);
HRAMWC |= BIT(4) | BIT(1) | BIT(0);
// Enable backup ROM access
FLHCTRL3 |= (1 << 3);
FLHCTRL3 |= BIT(3);
}
static enum Result cmd_print(void) {
@ -298,7 +298,7 @@ static enum Result cmd_spi(void) {
static enum Result cmd_reset(void) {
// Attempt to trigger watchdog reset
ETWCFG |= (1 << 5);
ETWCFG |= BIT(5);
EWDKEYR = 0;
// Failed if it got this far

8
src/board/system76/darp5/gpio.c
View File

@ -48,15 +48,15 @@ void gpio_init() {
// Set GPIO data
GPDRA = 0;
// NC
GPDRB = (1 << 0);
GPDRB = BIT(0);
GPDRC = 0;
// PWR_BTN#, SCI#, SMI#
GPDRD = (1 << 5) | (1 << 4) | (1 << 3);
GPDRD = BIT(5) | BIT(4) | BIT(3);
GPDRE = 0;
// USB_PWR_EN#, H_PECI
GPDRF = 0xC0; // (1 << 7) | (1 << 6)
GPDRF = BIT(7) | BIT(6);
// AIRPLAN_LED#
GPDRG = (1 << 6);
GPDRG = BIT(6);
GPDRH = 0;
GPDRI = 0;
GPDRJ = 0;

8
src/board/system76/galp3-c/gpio.c
View File

@ -48,15 +48,15 @@ void gpio_init() {
// Set GPIO data
GPDRA = 0;
// NC
GPDRB = (1 << 0);
GPDRB = BIT(0);
GPDRC = 0;
// PWR_BTN#, SCI#, SMI#
GPDRD = (1 << 5) | (1 << 4) | (1 << 3);
GPDRD = BIT(5) | BIT(4) | BIT(3);
GPDRE = 0;
// USB_PWR_EN#, H_PECI
GPDRF = 0xC0; // (1 << 7) | (1 << 6)
GPDRF = BIT(7) | BIT(6);
// AIRPLAN_LED#
GPDRG = (1 << 6);
GPDRG = BIT(6);
GPDRH = 0;
GPDRI = 0;
GPDRJ = 0;

2
src/board/system76/gaze15/gpio.c
View File

@ -40,7 +40,7 @@ void gpio_init() {
// Enable LPC reset on GPD2
GCR = 0x04;
// Enable SMBus channel 4
GCR15 = (1 << 4);
GCR15 = BIT(4);
// Set GPF2 and GPF3 to 3.3V
GCR20 = 0;

10
src/board/system76/lemp9/gpio.c
View File

@ -43,17 +43,17 @@ void gpio_init() {
// Enable LPC reset on GPD2
GCR = 0x04;
// Enable SMBus channel 4
GCR15 = (1 << 4);
GCR15 = BIT(4);
// Set GPF2 and GPF3 to 3.3V
GCR20 = 0;
// Set GPIO data
GPDRA = 0;
GPDRB = (1 << 4) | (1 << 3);
GPDRB = BIT(4) | BIT(3);
GPDRC = 0;
GPDRD = (1 << 5) | (1 << 4) | (1 << 3);
GPDRE = (1 << 3);
GPDRF = (1 << 6);
GPDRD = BIT(5) | BIT(4) | BIT(3);
GPDRE = BIT(3);
GPDRF = BIT(6);
GPDRG = 0;
GPDRH = 0;
GPDRI = 0;

10
src/board/system76/oryp5/gpio.c
View File

@ -45,16 +45,16 @@ void gpio_init(void) {
GPDRB = 0x00;
GPDRC = 0x00;
// PWR_BTN#, SCI#, SMI#
GPDRD = (1U << 5) | (1U << 4) | (1U << 3);
GPDRD = BIT(5) | BIT(4) | BIT(3);
// AMP_EN
GPDRE = (1U << 1);
GPDRE = BIT(1);
// USB_PWR_EN#, H_PECI
GPDRF = (1U << 7) | (1U << 6);
GPDRF = BIT(7) | BIT(6);
// AIRPLAN_LED#
GPDRG = (1U << 6);
GPDRG = BIT(6);
GPDRH = 0x00;
// EC_AMP_EN
GPDRI = (1U << 5);
GPDRI = BIT(5);
GPDRJ = 0x00;
// EC_SSD_LED#

2
src/board/system76/oryp6/gpio.c
View File

@ -41,7 +41,7 @@ void gpio_init() {
// Enable LPC reset on GPD2
GCR = 0x04;
// Enable SMBus channel 4
GCR15 = (1 << 4);
GCR15 = BIT(4);
// Set GPF2 and GPF3 to 3.3V
GCR20 = 0;

10
src/common/include/common/command.h
View File

@ -3,6 +3,8 @@
#ifndef _COMMON_COMMAND_H
#define _COMMON_COMMAND_H
#include <common/macro.h>
enum Command {
// Indicates that EC is ready to accept commands
CMD_NONE = 0,
@ -55,13 +57,13 @@ enum Result {
enum CommandSpiFlag {
// Read from SPI chip if set, write otherwise
CMD_SPI_FLAG_READ = (1 << 0),
CMD_SPI_FLAG_READ = BIT(0),
// Disable SPI chip after executing command
CMD_SPI_FLAG_DISABLE = (1 << 1),
CMD_SPI_FLAG_DISABLE = BIT(1),
// Run firmware from scratch RAM if necessary
CMD_SPI_FLAG_SCRATCH = (1 << 2),
CMD_SPI_FLAG_SCRATCH = BIT(2),
// Write to backup ROM instead
CMD_SPI_FLAG_BACKUP = (1 << 3),
CMD_SPI_FLAG_BACKUP = BIT(3),
};
#define CMD_LED_INDEX_ALL 0xFF

16
src/ec/it5570e/i2c.c
View File

@ -43,7 +43,7 @@ struct I2C __code I2C_4 = {
void i2c_reset(struct I2C * i2c, bool kill) {
if (*(i2c->hosta) & HOSTA_BUSY) {
// Set kill bit
if (kill) *(i2c->hoctl) |= (1 << 1);
if (kill) *(i2c->hoctl) |= BIT(1);
// Wait for host to finish
while (*(i2c->hosta) & HOSTA_BUSY) {}
}
@ -63,7 +63,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) __reentrant {
// If we are switching to read mode
if (read) {
// Enable direction switch
*(i2c->hoctl2) |= (1 << 3) | (1 << 2);
*(i2c->hoctl2) |= BIT(3) | BIT(2);
} else {
// Unsupported!
i2c_reset(i2c, true);
@ -74,7 +74,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) __reentrant {
i2c_reset(i2c, true);
// Enable host controller with i2c compatibility
*(i2c->hoctl2) = (1 << 1) | 1;
*(i2c->hoctl2) = BIT(1) | BIT(0);
// Set address
*(i2c->trasla) = (addr << 1) | read;
@ -85,7 +85,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) __reentrant {
void i2c_stop(struct I2C * i2c) {
// Disable i2c compatibility
*(i2c->hoctl2) &= ~(1 << 1);
*(i2c->hoctl2) &= ~BIT(1);
// Clear status
*(i2c->hosta) = *(i2c->hosta);
@ -99,7 +99,7 @@ static int i2c_transaction(struct I2C * i2c, uint8_t * data, int length, bool re
// If last byte
if ((i + 1) == length) {
// Set last byte bit
*(i2c->hoctl) |= (1 << 5);
*(i2c->hoctl) |= BIT(5);
}
} else {
// Write byte
@ -112,13 +112,13 @@ static int i2c_transaction(struct I2C * i2c, uint8_t * data, int length, bool re
*(i2c->hosta) = *(i2c->hosta);
} else {
// Start new transaction
*(i2c->hoctl) = (1 << 6) | (0b111 << 2);
*(i2c->hoctl) = BIT(6) | (0b111 << 2);
}
// If we are waiting on direction switch
if (*(i2c->hoctl2) & (1 << 2)) {
if (*(i2c->hoctl2) & BIT(2)) {
// Complete direction switch
*(i2c->hoctl2) &= ~(1 << 2);
*(i2c->hoctl2) &= ~BIT(2);
}
// Wait for byte done, timeout, or error

4
src/ec/it5570e/include/ec/gpio.h
View File

@ -3,6 +3,8 @@
#ifndef _EC_GPIO_H
#define _EC_GPIO_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -17,7 +19,7 @@ struct Gpio {
.data = &GPDR ## BLOCK, \
.mirror = &GPDMR ## BLOCK, \
.control = &GPCR ## BLOCK ## NUMBER, \
.value = (1 << NUMBER), \
.value = BIT(NUMBER), \
}
bool gpio_get(struct Gpio * gpio);

8
src/ec/it5570e/include/ec/kbc.h
View File

@ -3,6 +3,8 @@
#ifndef _EC_KBC_H
#define _EC_KBC_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -25,9 +27,9 @@ struct Kbc {
extern struct Kbc __code KBC;
#define KBC_STS_OBF (1 << 0)
#define KBC_STS_IBF (1 << 1)
#define KBC_STS_CMD (1 << 3)
#define KBC_STS_OBF BIT(0)
#define KBC_STS_IBF BIT(1)
#define KBC_STS_CMD BIT(3)
uint8_t kbc_status(struct Kbc * kbc);
uint8_t kbc_read(struct Kbc * kbc);

8
src/ec/it5570e/include/ec/pmc.h
View File

@ -3,6 +3,8 @@
#ifndef _EC_PMC_H
#define _EC_PMC_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -23,9 +25,9 @@ extern struct Pmc __code PMC_3;
extern struct Pmc __code PMC_4;
extern struct Pmc __code PMC_5;
#define PMC_STS_OBF (1 << 0)
#define PMC_STS_IBF (1 << 1)
#define PMC_STS_CMD (1 << 3)
#define PMC_STS_OBF BIT(0)
#define PMC_STS_IBF BIT(1)
#define PMC_STS_CMD BIT(3)
uint8_t pmc_status(struct Pmc * pmc);
void pmc_set_status(struct Pmc * pmc, uint8_t status);

18
src/ec/it5570e/include/ec/smbus.h
View File

@ -3,16 +3,18 @@
#ifndef _EC_SMBUS_H
#define _EC_SMBUS_H
#include <common/macro.h>
#include <stdint.h>
#define HOSTA_BYTE_DONE (1 << 7)
#define HOSTA_TIMEOUT (1 << 6)
#define HOSTA_NACK (1 << 5)
#define HOSTA_FAIL (1 << 4)
#define HOSTA_BUS_ERR (1 << 3)
#define HOSTA_DEV_ERR (1 << 2)
#define HOSTA_FINISH (1 << 1)
#define HOSTA_BUSY (1 << 0)
#define HOSTA_BYTE_DONE BIT(7)
#define HOSTA_TIMEOUT BIT(6)
#define HOSTA_NACK BIT(5)
#define HOSTA_FAIL BIT(4)
#define HOSTA_BUS_ERR BIT(3)
#define HOSTA_DEV_ERR BIT(2)
#define HOSTA_FINISH BIT(1)
#define HOSTA_BUSY BIT(0)
#define HOSTA_ERR (HOSTA_TIMEOUT | HOSTA_NACK | HOSTA_FAIL | HOSTA_BUS_ERR | HOSTA_DEV_ERR)
// Host status for channel A

9
src/ec/it5570e/ps2.c
View File

@ -2,6 +2,7 @@
#include <stdbool.h>
#include <common/macro.h>
#include <ec/ps2.h>
#define PS2(NUM) { \
@ -13,11 +14,11 @@
#define PS2_TIMEOUT 10000
#define PSSTS_TIMEOUT_ERR (1 << 6)
#define PSSTS_FRAME_ERR (1 << 5)
#define PSSTS_PARITY_ERR (1 << 4)
#define PSSTS_TIMEOUT_ERR BIT(6)
#define PSSTS_FRAME_ERR BIT(5)
#define PSSTS_PARITY_ERR BIT(4)
#define PSSTS_ALL_ERR (PSSTS_TIMEOUT_ERR | PSSTS_FRAME_ERR | PSSTS_PARITY_ERR)
#define PSSTS_DONE (1 << 3)
#define PSSTS_DONE BIT(3)
struct Ps2 __code PS2_1 = PS2(1);
struct Ps2 __code PS2_2 = PS2(2);

16
src/ec/it8587e/i2c.c
View File

@ -35,7 +35,7 @@ struct I2C __code I2C_1 = {
void i2c_reset(struct I2C * i2c, bool kill) {
if (*(i2c->hosta) & HOSTA_BUSY) {
// Set kill bit
if (kill) *(i2c->hoctl) |= (1 << 1);
if (kill) *(i2c->hoctl) |= BIT(1);
// Wait for host to finish
while (*(i2c->hosta) & HOSTA_BUSY) {}
}
@ -55,7 +55,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) __reentrant {
// If we are switching to read mode
if (read) {
// Enable direction switch
*(i2c->hoctl2) |= (1 << 3) | (1 << 2);
*(i2c->hoctl2) |= BIT(3) | BIT(2);
} else {
// Unsupported!
i2c_reset(i2c, true);
@ -66,7 +66,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) __reentrant {
i2c_reset(i2c, true);
// Enable host controller with i2c compatibility
*(i2c->hoctl2) = (1 << 1) | 1;
*(i2c->hoctl2) = BIT(1) | BIT(0);
// Set address
*(i2c->trasla) = (addr << 1) | read;
@ -77,7 +77,7 @@ int i2c_start(struct I2C * i2c, uint8_t addr, bool read) __reentrant {
void i2c_stop(struct I2C * i2c) {
// Disable i2c compatibility
*(i2c->hoctl2) &= ~(1 << 1);
*(i2c->hoctl2) &= ~BIT(1);
// Clear status
*(i2c->hosta) = *(i2c->hosta);
@ -91,7 +91,7 @@ static int i2c_transaction(struct I2C * i2c, uint8_t * data, int length, bool re
// If last byte
if ((i + 1) == length) {
// Set last byte bit
*(i2c->hoctl) |= (1 << 5);
*(i2c->hoctl) |= BIT(5);
}
} else {
// Write byte
@ -104,13 +104,13 @@ static int i2c_transaction(struct I2C * i2c, uint8_t * data, int length, bool re
*(i2c->hosta) = *(i2c->hosta);
} else {
// Start new transaction
*(i2c->hoctl) = (1 << 6) | (0b111 << 2);
*(i2c->hoctl) = BIT(6) | (0b111 << 2);
}
// If we are waiting on direction switch
if (*(i2c->hoctl2) & (1 << 2)) {
if (*(i2c->hoctl2) & BIT(2)) {
// Complete direction switch
*(i2c->hoctl2) &= ~(1 << 2);
*(i2c->hoctl2) &= ~BIT(2);
}
// Wait for byte done, timeout, or error

4
src/ec/it8587e/include/ec/gpio.h
View File

@ -3,6 +3,8 @@
#ifndef _EC_GPIO_H
#define _EC_GPIO_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -17,7 +19,7 @@ struct Gpio {
.data = &GPDR ## BLOCK, \
.mirror = &GPDMR ## BLOCK, \
.control = &GPCR ## BLOCK ## NUMBER, \
.value = (1 << NUMBER), \
.value = BIT(NUMBER), \
}
bool gpio_get(struct Gpio * gpio);

8
src/ec/it8587e/include/ec/kbc.h
View File

@ -3,6 +3,8 @@
#ifndef _EC_KBC_H
#define _EC_KBC_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -25,9 +27,9 @@ struct Kbc {
extern struct Kbc __code KBC;
#define KBC_STS_OBF (1 << 0)
#define KBC_STS_IBF (1 << 1)
#define KBC_STS_CMD (1 << 3)
#define KBC_STS_OBF BIT(0)
#define KBC_STS_IBF BIT(1)
#define KBC_STS_CMD BIT(3)
uint8_t kbc_status(struct Kbc * kbc);
uint8_t kbc_read(struct Kbc * kbc);

8
src/ec/it8587e/include/ec/pmc.h
View File

@ -3,6 +3,8 @@
#ifndef _EC_PMC_H
#define _EC_PMC_H
#include <common/macro.h>
#include <stdbool.h>
#include <stdint.h>
@ -23,9 +25,9 @@ extern struct Pmc __code PMC_3;
extern struct Pmc __code PMC_4;
extern struct Pmc __code PMC_5;
#define PMC_STS_OBF (1 << 0)
#define PMC_STS_IBF (1 << 1)
#define PMC_STS_CMD (1 << 3)
#define PMC_STS_OBF BIT(0)
#define PMC_STS_IBF BIT(1)
#define PMC_STS_CMD BIT(3)
uint8_t pmc_status(struct Pmc * pmc);
void pmc_set_status(struct Pmc * pmc, uint8_t status);

18
src/ec/it8587e/include/ec/smbus.h
View File

@ -3,16 +3,18 @@
#ifndef _EC_SMBUS_H
#define _EC_SMBUS_H
#include <common/macro.h>
#include <stdint.h>
#define HOSTA_BYTE_DONE (1 << 7)
#define HOSTA_TIMEOUT (1 << 6)
#define HOSTA_NACK (1 << 5)
#define HOSTA_FAIL (1 << 4)
#define HOSTA_BUS_ERR (1 << 3)
#define HOSTA_DEV_ERR (1 << 2)
#define HOSTA_FINISH (1 << 1)
#define HOSTA_BUSY (1 << 0)
#define HOSTA_BYTE_DONE BIT(7)
#define HOSTA_TIMEOUT BIT(6)
#define HOSTA_NACK BIT(5)
#define HOSTA_FAIL BIT(4)
#define HOSTA_BUS_ERR BIT(3)
#define HOSTA_DEV_ERR BIT(2)
#define HOSTA_FINISH BIT(1)
#define HOSTA_BUSY BIT(0)
#define HOSTA_ERR (HOSTA_TIMEOUT | HOSTA_NACK | HOSTA_FAIL | HOSTA_BUS_ERR | HOSTA_DEV_ERR)
// Host status for channel A

9
src/ec/it8587e/ps2.c
View File

@ -2,6 +2,7 @@
#include <stdbool.h>
#include <common/macro.h>
#include <ec/ps2.h>
#define PS2(NUM) { \
@ -13,11 +14,11 @@
#define PS2_TIMEOUT 10000
#define PSSTS_TIMEOUT_ERR (1 << 6)
#define PSSTS_FRAME_ERR (1 << 5)
#define PSSTS_PARITY_ERR (1 << 4)
#define PSSTS_TIMEOUT_ERR BIT(6)
#define PSSTS_FRAME_ERR BIT(5)
#define PSSTS_PARITY_ERR BIT(4)
#define PSSTS_ALL_ERR (PSSTS_TIMEOUT_ERR | PSSTS_FRAME_ERR | PSSTS_PARITY_ERR)
#define PSSTS_DONE (1 << 3)
#define PSSTS_DONE BIT(3)
struct Ps2 __code PS2_1 = PS2(1);
struct Ps2 __code PS2_2 = PS2(2);