Reduce variable usage to fit within paged data
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ae4379199c
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@ -12,9 +12,6 @@
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int16_t peci_offset = 0;
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int16_t peci_offset = 0;
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int16_t peci_temp = 0;
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int16_t peci_temp = 0;
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uint8_t peci_duty = 0;
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uint8_t peci_duty = 0;
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uint8_t peci_tcontrol = 0;
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uint8_t peci_tjmax = T_JUNCTION;
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static bool peci_config_loaded = false;
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#define PECI_TEMP(X) (((int16_t)(X)) << 6)
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#define PECI_TEMP(X) (((int16_t)(X)) << 6)
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#define PWM_DUTY(X) ((uint8_t)(((((uint16_t)(X)) * 255) + 99) / 100))
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#define PWM_DUTY(X) ((uint8_t)(((((uint16_t)(X)) * 255) + 99) / 100))
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@ -78,55 +75,6 @@ void peci_init(void) {
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PADCTLR = 0x02;
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PADCTLR = 0x02;
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}
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}
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// Read tjmax using index 16 of RdPkgConfig
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static void peci_config(void) {
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// Wait for completion
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while (HOSTAR & 1) {}
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// Clear status
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HOSTAR = HOSTAR;
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// Enable PECI, clearing data fifo's
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HOCTLR = (1 << 5) | (1 << 3);
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// Set address to default
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HOTRADDR = 0x30;
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// Set write length
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HOWRLR = 5;
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// Set read length
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HORDLR = 5;
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// Set command
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HOCMDR = 0xA1;
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// Set Host ID ?
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HOWRDR = 0x00;
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// Set index
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HOWRDR = 16;
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// Set parameter
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HOWRDR = 0;
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HOWRDR = 0;
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// Start transaction
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HOCTLR |= 1;
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// Wait for completion
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while (HOSTAR & 1) {}
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if (HOSTAR & (1 << 1)) {
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// Use result if finished successfully
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//TODO: check completion code
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uint8_t data = HOWRDR;
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// Throw away reserved byte
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data = HOWRDR;
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// Tead tcontrol for now
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peci_tcontrol = HOWRDR;
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// Read tjmax
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peci_tjmax = HOWRDR;
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// Throw away reserved byte
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data = HOWRDR;
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peci_config_loaded = true;
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}
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}
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// PECI information can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/core-i7-lga-2011-guide.pdf
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// PECI information can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/core-i7-lga-2011-guide.pdf
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void peci_event(void) {
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void peci_event(void) {
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// Wait for completion
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// Wait for completion
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@ -156,12 +104,6 @@ void peci_event(void) {
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uint8_t high = HORDDR;
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uint8_t high = HORDDR;
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peci_offset = ((int16_t)high << 8) | (int16_t)low;
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peci_offset = ((int16_t)high << 8) | (int16_t)low;
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// TODO: Update max value if possible
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// if (!peci_config_loaded) {
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// peci_config();
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// }
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// TODO: tjmax
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peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset;
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peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset;
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peci_duty = fan_duty(peci_temp);
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peci_duty = fan_duty(peci_temp);
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} else {
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} else {
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@ -35,7 +35,7 @@ bool pmc_sci(struct Pmc * pmc, uint8_t sci) {
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void pmc_event(struct Pmc * pmc) {
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void pmc_event(struct Pmc * pmc) {
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static enum PmcState state = PMC_STATE_DEFAULT;
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static enum PmcState state = PMC_STATE_DEFAULT;
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static uint8_t state_data[2] = {0, 0};
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static uint8_t state_data = 0;
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uint16_t burst_timeout;
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uint16_t burst_timeout;
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for (burst_timeout = 1; burst_timeout > 0; burst_timeout--) {
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for (burst_timeout = 1; burst_timeout > 0; burst_timeout--) {
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@ -94,16 +94,16 @@ void pmc_event(struct Pmc * pmc) {
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switch (state) {
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switch (state) {
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case PMC_STATE_ACPI_READ:
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case PMC_STATE_ACPI_READ:
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state = PMC_STATE_DEFAULT;
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state = PMC_STATE_DEFAULT;
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uint8_t value = acpi_read(data);
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state_data = acpi_read(data);
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pmc_write(pmc, value, PMC_TIMEOUT);
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pmc_write(pmc, state_data, PMC_TIMEOUT);
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break;
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break;
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case PMC_STATE_ACPI_WRITE:
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case PMC_STATE_ACPI_WRITE:
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state = PMC_STATE_ACPI_WRITE_ADDR;
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state = PMC_STATE_ACPI_WRITE_ADDR;
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state_data[0] = data;
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state_data = data;
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break;
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break;
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case PMC_STATE_ACPI_WRITE_ADDR:
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case PMC_STATE_ACPI_WRITE_ADDR:
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state = PMC_STATE_DEFAULT;
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state = PMC_STATE_DEFAULT;
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acpi_write(state_data[0], data);
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acpi_write(state_data, data);
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break;
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break;
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default:
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default:
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state = PMC_STATE_DEFAULT;
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state = PMC_STATE_DEFAULT;
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