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8051: Allow up to 64KB firmware images.

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The ITE EC hardware always has the first 32KB of ram mapped, while
a second 32KB of ram is banked immediately after. By default, the
banked physical address immediately follows the fixed area in flash.
This commit is contained in:
Evan Lojewski 2020-05-18 19:01:41 -06:00 committed by Jeremy Soller
parent 99ef48f9c4
commit ba5f1ab55c
3 changed files with 8 additions and 2 deletions
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4
src/arch/8051/arch.mk
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@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-3.0-only # SPDX-License-Identifier: GPL-3.0-only
CC=sdcc -mmcs51 --model-large --xram-size $(SRAM_SIZE) --Werror CC=sdcc -mmcs51 --model-large --code-size $(CODE_SIZE) --xram-size $(SRAM_SIZE) --Werror
OBJ=$(patsubst src/%.c,$(BUILD)/%.rel,$(SRC)) OBJ=$(patsubst src/%.c,$(BUILD)/%.rel,$(SRC))
# Run EC rom in simulator # Run EC rom in simulator
@ -14,7 +14,7 @@ sim: $(BUILD)/ec.rom
# Convert from Intel Hex file to binary file # Convert from Intel Hex file to binary file
$(BUILD)/ec.rom: $(BUILD)/ec.ihx $(BUILD)/ec.rom: $(BUILD)/ec.ihx
@mkdir -p $(@D) @mkdir -p $(@D)
makebin -p < $< > $@ makebin -s $(CODE_SIZE) -p < $< > $@
# Link object files into Intel Hex file # Link object files into Intel Hex file
$(BUILD)/ec.ihx: $(OBJ) $(BUILD)/ec.ihx: $(OBJ)

3
src/ec/it5570e/ec.mk
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@ -2,6 +2,9 @@
ARCH=8051 ARCH=8051
# 64 KB is the max without banking
CODE_SIZE=65536
# SRAM is 6144 bytes, only 4096 bytes are mapped at address 0. Region at # SRAM is 6144 bytes, only 4096 bytes are mapped at address 0. Region at
# 0x0E00-0x1000 is used for AP communication. So this is brought down to 2048, # 0x0E00-0x1000 is used for AP communication. So this is brought down to 2048,
# which matches it8587e limits # which matches it8587e limits

3
src/ec/it8587e/ec.mk
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@ -2,5 +2,8 @@
ARCH=8051 ARCH=8051
# 64 KB is the max without banking
CODE_SIZE=65536
# SRAM is 4096 bytes, but SRAM at address 2048 is used for scratch ROM # SRAM is 4096 bytes, but SRAM at address 2048 is used for scratch ROM
SRAM_SIZE=2048 SRAM_SIZE=2048