sravan/system76-embedded-controller
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix calculation of S3 power state, remove S4 power state

Browse Source
This commit is contained in:
Jeremy Soller 2020-03-17 12:49:11 -06:00
parent 7fbad82088
commit d96147688d
No known key found for this signature in database
GPG Key ID: E988B49EE78A7FB1
6 changed files with 18 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/board/system76/darp5/include/board/power.h
View File

@ -5,8 +5,6 @@ enum PowerState {
POWER_STATE_DEFAULT,
POWER_STATE_DS5,
POWER_STATE_S5,
POWER_STATE_DS4,
POWER_STATE_S4,
POWER_STATE_DS3,
POWER_STATE_S3,
POWER_STATE_S0,

23
src/board/system76/darp5/power.c
View File

@ -56,19 +56,14 @@ enum PowerState power_state = POWER_STATE_DEFAULT;
enum PowerState calculate_power_state(void) {
//TODO: Deep Sx states using SLP_SUS#
if (gpio_get(&BUF_PLT_RST_N)) {
// CPU powered
if (gpio_get(&SUSB_N_PCH)) {
// S3, S4, and S5 planes powered
return POWER_STATE_S0;
}
if (gpio_get(&SUSB_N_PCH)) {
// S3 plane powered
return POWER_STATE_S3;
}
if (gpio_get(&SUSC_N_PCH)) {
// S4 plane powered
return POWER_STATE_S4;
// S4 and S5 planes powered
return POWER_STATE_S3;
}
if (gpio_get(&EC_RSMRST_N)) {
@ -103,12 +98,6 @@ void update_power_state(void) {
case POWER_STATE_S5:
DEBUG("POWER_STATE_S5\n");
break;
case POWER_STATE_DS4:
DEBUG("POWER_STATE_DS4\n");
break;
case POWER_STATE_S4:
DEBUG("POWER_STATE_S4\n");
break;
case POWER_STATE_DS3:
DEBUG("POWER_STATE_DS3\n");
break;
@ -165,9 +154,9 @@ void power_on_s5(void) {
// TODO - signal timing graph
// See Figure 12-24 in Whiskey Lake Platform Design Guide
// TODO - rail timing graph
// TODO: Must have SL_SUS# set high by PCH
// Enable VCCPRIM_* planes - must be enabled prior to USB power in order to
// avoid leakage
gpio_set(&VA_EC_EN, true);

2
src/board/system76/galp3-c/include/board/power.h
View File

@ -5,8 +5,6 @@ enum PowerState {
POWER_STATE_DEFAULT,
POWER_STATE_DS5,
POWER_STATE_S5,
POWER_STATE_DS4,
POWER_STATE_S4,
POWER_STATE_DS3,
POWER_STATE_S3,
POWER_STATE_S0,

23
src/board/system76/galp3-c/power.c
View File

@ -55,19 +55,14 @@ enum PowerState power_state = POWER_STATE_DEFAULT;
enum PowerState calculate_power_state(void) {
//TODO: Deep Sx states using SLP_SUS#
if (gpio_get(&BUF_PLT_RST_N)) {
// CPU powered
if (gpio_get(&SUSB_N_PCH)) {
// S3, S4, and S5 planes powered
return POWER_STATE_S0;
}
if (gpio_get(&SUSB_N_PCH)) {
// S3 plane powered
return POWER_STATE_S3;
}
if (gpio_get(&SUSC_N_PCH)) {
// S4 plane powered
return POWER_STATE_S4;
// S4 and S5 planes powered
return POWER_STATE_S3;
}
if (gpio_get(&EC_RSMRST_N)) {
@ -102,12 +97,6 @@ void update_power_state(void) {
case POWER_STATE_S5:
DEBUG("POWER_STATE_S5\n");
break;
case POWER_STATE_DS4:
DEBUG("POWER_STATE_DS4\n");
break;
case POWER_STATE_S4:
DEBUG("POWER_STATE_S4\n");
break;
case POWER_STATE_DS3:
DEBUG("POWER_STATE_DS3\n");
break;
@ -164,9 +153,9 @@ void power_on_s5(void) {
// TODO - signal timing graph
// See Figure 12-24 in Whiskey Lake Platform Design Guide
// TODO - rail timing graph
// TODO: Must have SL_SUS# set high by PCH
// Enable VCCPRIM_* planes - must be enabled prior to USB power in order to
// avoid leakage
gpio_set(&VA_EC_EN, true);

2
src/board/system76/lemp9/include/board/power.h
View File

@ -5,8 +5,6 @@ enum PowerState {
POWER_STATE_DEFAULT,
POWER_STATE_DS5,
POWER_STATE_S5,
POWER_STATE_DS4,
POWER_STATE_S4,
POWER_STATE_DS3,
POWER_STATE_S3,
POWER_STATE_S0,

23
src/board/system76/lemp9/power.c
View File

@ -55,19 +55,14 @@ enum PowerState power_state = POWER_STATE_DEFAULT;
enum PowerState calculate_power_state(void) {
//TODO: Deep Sx states using SLP_SUS#
if (gpio_get(&BUF_PLT_RST_N)) {
// CPU powered
if (gpio_get(&SUSB_N_PCH)) {
// S3, S4, and S5 planes powered
return POWER_STATE_S0;
}
if (gpio_get(&SUSB_N_PCH)) {
// S3 plane powered
return POWER_STATE_S3;
}
if (gpio_get(&SUSC_N_PCH)) {
// S4 plane powered
return POWER_STATE_S4;
// S4 and S5 planes powered
return POWER_STATE_S3;
}
if (gpio_get(&EC_RSMRST_N)) {
@ -102,12 +97,6 @@ void update_power_state(void) {
case POWER_STATE_S5:
DEBUG("POWER_STATE_S5\n");
break;
case POWER_STATE_DS4:
DEBUG("POWER_STATE_DS4\n");
break;
case POWER_STATE_S4:
DEBUG("POWER_STATE_S4\n");
break;
case POWER_STATE_DS3:
DEBUG("POWER_STATE_DS3\n");
break;
@ -164,9 +153,9 @@ void power_on_s5(void) {
// TODO - signal timing graph
// See Figure 12-24 in Whiskey Lake Platform Design Guide
// TODO - rail timing graph
// TODO: Must have SL_SUS# set high by PCH
// Enable VCCPRIM_* planes - must be enabled prior to USB power in order to
// avoid leakage
gpio_set(&VA_EC_EN, true);