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docs: Add note about IME state on TGL-U

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Explain why we ship galp5/lemp10 with the IME enabled.
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Tim Crawford
2021-02-26 10:02:04 -07:00
committed by Jeremy Soller
parent 541f4f3f13
commit c59c6e7fa4
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docs/intel-me.md
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@@ -11,6 +11,16 @@ does not support the ME version used on many of our systems. Instead, we [send
a HECI command][heci_disable] to tell the Intel ME to disable runtime
components during early boot.
## Tiger Lake-U
Models using TGL-U processors currently leave the IME enabled. TGL-U removes
support for S3 and requires S0ix. This requires all CPU, PCH, and PCIe devices
to have ACPI defined low power states. With S0ix, the CPU has numerous states
for low power, with the lowest being C10. In order to reach this C10 state, the
IME must report that it is in a low power state. Disabling the ME with the HAP
bit keeps the CPU in the C8 state. This nearly triples the power usage in S0ix
suspend, from around 1 watt to around 3 watts.
[wiki]: https://en.wikipedia.org/wiki/Intel_Management_Engine
[me\_cleaner]: https://github.com/corna/me_cleaner
[heci_disable]: https://github.com/system76/coreboot/blob/011439cb9196d6a71d394ead8c98dfd8ead325d4/src/soc/intel/cannonlake/me.c#L186