Add darp7, galp5, and lemp10
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Jeremy Soller
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Jeremy Soller
Jeremy Soller
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356
models/lemp10/FSP/Include/GpioConfig.h
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356
models/lemp10/FSP/Include/GpioConfig.h
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/** @file
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Header file for GpioConfig structure used by GPIO library.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2017 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _GPIO_CONFIG_H_
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#define _GPIO_CONFIG_H_
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#pragma pack(push, 1)
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///
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/// For any GpioPad usage in code use GPIO_PAD type
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///
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typedef UINT32 GPIO_PAD;
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///
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/// For any GpioGroup usage in code use GPIO_GROUP type
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///
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typedef UINT32 GPIO_GROUP;
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/**
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GPIO configuration structure used for pin programming.
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Structure contains fields that can be used to configure pad.
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**/
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typedef struct {
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/**
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Pad Mode
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Pad can be set as GPIO or one of its native functions.
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When in native mode setting Direction (except Inversion), OutputState,
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InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
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Refer to definition of GPIO_PAD_MODE.
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Refer to EDS for each native mode according to the pad.
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**/
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UINT32 PadMode : 5;
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/**
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Host Software Pad Ownership
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Set pad to ACPI mode or GPIO Driver Mode.
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Refer to definition of GPIO_HOSTSW_OWN.
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**/
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UINT32 HostSoftPadOwn : 2;
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/**
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GPIO Direction
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Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
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Refer to definition of GPIO_DIRECTION for supported settings.
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**/
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UINT32 Direction : 6;
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/**
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Output State
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Set Pad output value.
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Refer to definition of GPIO_OUTPUT_STATE for supported settings.
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This setting takes place when output is enabled.
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**/
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UINT32 OutputState : 2;
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/**
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GPIO Interrupt Configuration
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Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
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This setting is applicable only if GPIO is in GpioMode with input enabled.
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Refer to definition of GPIO_INT_CONFIG for supported settings.
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**/
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UINT32 InterruptConfig : 9;
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/**
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GPIO Power Configuration.
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This setting controls Pad Reset Configuration.
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Refer to definition of GPIO_RESET_CONFIG for supported settings.
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**/
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UINT32 PowerConfig : 8;
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/**
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GPIO Electrical Configuration
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This setting controls pads termination and voltage tolerance.
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Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
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**/
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UINT32 ElectricalConfig : 9;
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/**
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GPIO Lock Configuration
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This setting controls pads lock.
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Refer to definition of GPIO_LOCK_CONFIG for supported settings.
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**/
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UINT32 LockConfig : 4;
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/**
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Additional GPIO configuration
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Refer to definition of GPIO_OTHER_CONFIG for supported settings.
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**/
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UINT32 OtherSettings : 2;
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UINT32 RsvdBits : 17; ///< Reserved bits for future extension
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} GPIO_CONFIG;
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typedef enum {
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GpioHardwareDefault = 0x0 ///< Leave setting unmodified
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} GPIO_HARDWARE_DEFAULT;
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/**
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GPIO Pad Mode
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Refer to GPIO documentation on native functions available for certain pad.
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If GPIO is set to one of NativeX modes then following settings are not applicable
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and can be skipped:
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- Interrupt related settings
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- Host Software Ownership
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- Output/Input enabling/disabling
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- Output lock
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**/
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typedef enum {
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GpioPadModeGpio = 0x1,
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GpioPadModeNative1 = 0x3,
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GpioPadModeNative2 = 0x5,
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GpioPadModeNative3 = 0x7,
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GpioPadModeNative4 = 0x9
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} GPIO_PAD_MODE;
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/**
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Host Software Pad Ownership modes
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This setting affects GPIO interrupt status registers. Depending on chosen ownership
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some GPIO Interrupt status register get updated and other masked.
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Please refer to EDS for HOSTSW_OWN register description.
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**/
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typedef enum {
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GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
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/**
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Set HOST ownership to ACPI.
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Use this setting if pad is not going to be used by GPIO OS driver.
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If GPIO is configured to generate SCI/SMI/NMI then this setting must be
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used for interrupts to work
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**/
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GpioHostOwnAcpi = 0x1,
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/**
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Set HOST ownership to GPIO Driver mode.
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Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
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GPIO OS Driver will be able to control the pad if appropriate entry in
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ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
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**/
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GpioHostOwnGpio = 0x3
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} GPIO_HOSTSW_OWN;
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///
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/// GPIO Direction
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///
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typedef enum {
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GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
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GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
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GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
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GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
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GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
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GpioDirOut = 0x5, ///< Set pad for output only
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GpioDirNone = 0x7 ///< Disable both output and input
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} GPIO_DIRECTION;
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/**
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GPIO Output State
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This field is relevant only if output is enabled
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**/
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typedef enum {
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GpioOutDefault = 0x0, ///< Leave output value unmodified
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GpioOutLow = 0x1, ///< Set output to low
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GpioOutHigh = 0x3 ///< Set output to high
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} GPIO_OUTPUT_STATE;
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/**
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GPIO interrupt configuration
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This setting is applicable only if pad is in GPIO mode and has input enabled.
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GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
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and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
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EDS for details on this settings.
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Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
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to describe an interrupt e.g. GpioIntApic | GpioIntLevel
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If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
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If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
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Not all GPIO are capable of generating an SMI or NMI interrupt.
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When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
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interrupt cannot be shared and its IRQn number is not configurable.
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Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
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If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
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exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
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This type of GPIO Driver interrupt doesn't have any additional routing setting
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required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
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**/
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typedef enum {
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GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
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GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
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GpioIntNmi = 0x3, ///< Enable NMI interrupt only
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GpioIntSmi = 0x5, ///< Enable SMI interrupt only
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GpioIntSci = 0x9, ///< Enable SCI interrupt only
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GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
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GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
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GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
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GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
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GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
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} GPIO_INT_CONFIG;
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#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
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#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
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/**
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GPIO Power Configuration
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GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
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be used to reset certain GPIO settings.
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Refer to EDS for settings that are controllable by PadRstCfg.
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**/
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typedef enum {
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GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
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///
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/// Deprecated settings. Maintained only for compatibility.
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///
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GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
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GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
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GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
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GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
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///
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/// New GPIO reset configuration options
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///
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/**
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Resume Reset (RSMRST)
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GPP: PadRstCfg = 00b = "Powergood"
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GPD: PadRstCfg = 11b = "Resume Reset"
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Pad setting will reset on:
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- DeepSx transition
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- G3
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Pad settings will not reset on:
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- S3/S4/S5 transition
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- Warm/Cold/Global reset
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**/
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GpioResumeReset = 0x01,
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/**
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Host Deep Reset
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PadRstCfg = 01b = "Deep GPIO Reset"
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Pad settings will reset on:
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- Warm/Cold/Global reset
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- DeepSx transition
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- G3
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Pad settings will not reset on:
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- S3/S4/S5 transition
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**/
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GpioHostDeepReset = 0x03,
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/**
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Platform Reset (PLTRST)
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PadRstCfg = 10b = "GPIO Reset"
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Pad settings will reset on:
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- S3/S4/S5 transition
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- Warm/Cold/Global reset
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- DeepSx transition
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- G3
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**/
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GpioPlatformReset = 0x05,
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/**
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Deep Sleep Well Reset (DSW_PWROK)
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GPP: not applicable
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GPD: PadRstCfg = 00b = "Powergood"
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Pad settings will reset on:
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- G3
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Pad settings will not reset on:
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- S3/S4/S5 transition
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- Warm/Cold/Global reset
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- DeepSx transition
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**/
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GpioDswReset = 0x07
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} GPIO_RESET_CONFIG;
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/**
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GPIO Electrical Configuration
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Set GPIO termination and Pad Tolerance (applicable only for some pads)
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Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
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**/
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typedef enum {
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GpioTermDefault = 0x0, ///< Leave termination setting unmodified
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GpioTermNone = 0x1, ///< none
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GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
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GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
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GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
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GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
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GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
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GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
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GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
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/**
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Native function controls pads termination
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This setting is applicable only to some native modes.
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Please check EDS to determine which native functionality
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can control pads termination
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**/
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GpioTermNative = 0x1F,
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GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
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GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
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} GPIO_ELECTRICAL_CONFIG;
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#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
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#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
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/**
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GPIO LockConfiguration
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Set GPIO configuration lock and output state lock.
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GpioLockPadConfig and GpioLockOutputState can be OR'ed.
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Lock settings reset is in Powergood domain. Care must be taken when using this setting
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as fields it locks may be reset by a different signal and can be controllable
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by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
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functions which allow to unlock a GPIO pad.
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**/
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typedef enum {
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GpioLockDefault = 0x0, ///< Leave lock setting unmodified
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GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
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GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
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} GPIO_LOCK_CONFIG;
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#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
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#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
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/**
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Other GPIO Configuration
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GPIO_OTHER_CONFIG is used for less often settings and for future extensions
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Supported settings:
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- RX raw override to '1' - allows to override input value to '1'
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This setting is applicable only if in input mode (both in GPIO and native usage).
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The override takes place at the internal pad state directly from buffer and before the RXINV.
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**/
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typedef enum {
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GpioRxRaw1Default = 0x0, ///< Use default input override value
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GpioRxRaw1Dis = 0x1, ///< Don't override input
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GpioRxRaw1En = 0x3 ///< Override input to '1'
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} GPIO_OTHER_CONFIG;
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#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
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#pragma pack(pop)
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#endif //_GPIO_CONFIG_H_
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