coreboot: Fix USB2 on USB-C for gaze18, serw13

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Update ec
2023-03-22 08:41:26 -06:00 · 2023-03-21 20:35:28 -06:00 · 2023-03-21 20:07:27 -06:00 · 2023-03-21 19:56:40 -06:00 · 2023-03-21 19:52:26 -06:00 · 2023-03-21 13:41:25 -06:00
171 changed files with 319528 additions and 76 deletions
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,6 +4,11 @@ Changes are identified by the date of the released firmware including them. If
 you are running System76 Open Firmware, opening the boot menu will show this
 date followed by an underscore and a short git revision.

+## unreleased
+
+- Enabled support for Secure Boot
+- Enabled minimal UI for enforcing Secure Boot and resetting keys
+
 ## 2022-11-21

 - lemp11: Added workaround to force S0ix entry on suspend
--- a/apps/firmware-setup
+++ b/apps/firmware-setup
--- a/apps/firmware-update
+++ b/apps/firmware-update
--- a/2
+++ b/2
--- a/docs/adding-a-new-board.md
+++ b/docs/adding-a-new-board.md
@@ -71,8 +71,6 @@ Other things that should be dumped before porting/flashing are:

 To port coreboot to a new board, see the coreboot documentation.

- [TAS5825M] smart amp
-
 Once coreboot is ported, add its configuration.

 ```
@@ -84,6 +82,19 @@ cp coreboot/.config models/<model>/coreboot.config
 `generate.sh` does not create `devicetree.cb`. Some values for this file can be
 produced using the `devicetree.py` script.

+### Smart amp
+
+Boards may have a smart amp, which must be configured for speaker output to
+work.
+
+The initialization data for Realtek smart amps can be dumped from the module
+that does the codec init in proprietary firmware. The correct module can be
+found using UEFITool by searching for the vendor/device ID of the codec, such
+as "10ec1220" for the ALC1220. This is the start of the `cim_verb_data` array
+in coreboot.
+
+For info on the TI TAS5825M smart amp, see the [smart-amp] repo.
+
 ## Configuring Intel CSME

 The CSME image may need to be regenerated. Common changes that may be required
@@ -106,4 +117,4 @@ READMEs.
 [external-programmer]: ./flashing.md#external-programmer
 [intel-microcode]: https://github.com/system76/intel-microcode
 [mega2560]: https://github.com/system76/ec/blob/master/doc/mega2560.md
-[TAS5825M]: https://github.com/system76/smart-amp
+[smart-amp]: https://github.com/system76/smart-amp
--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/libs/intel-spi
+++ b/libs/intel-spi
--- a/models/README.md
+++ b/models/README.md
@@ -4,7 +4,9 @@

 - [addw1](./addw1) - System76 Adder Workstation (addw1)
 - [addw2](./addw2) - System76 Adder WS (addw2)
+- [addw3](./addw3) - System76 Adder WS (addw3)
 - [bonw14](./bonw14) - System76 Bonobo WS (bonw14)
+- [bonw15](./bonw15) - System76 Bonobo WS (bonw15)
 - [darp5](./darp5) - System76 Darter Pro (darp5)
 - [darp6](./darp6) - System76 Darter Pro (darp6)
 - [darp7](./darp7) - System76 Darter Pro (darp7)
@@ -24,13 +26,16 @@
 - [gaze16-3060-b](./gaze16-3060-b) - System76 Gazelle (gaze16)
 - [gaze17-3050](./gaze17-3050) - System76 Gazelle (gaze17)
 - [gaze17-3060-b](./gaze17-3060-b) - System76 Gazelle (gaze17-3060-b)
+- [gaze18](./gaze18) - System76 Gazelle (gaze18)
 - [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
 - [lemp11](./lemp11) - System76 Lemur Pro (lemp11)
 - [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
 - [oryp10](./oryp10) - System76 Oryx Pro (oryp10)
+- [oryp11](./oryp11) - System76 Oryx Pro (oryp11)
 - [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
 - [oryp6](./oryp6) - System76 Oryx Pro (oryp6)
 - [oryp7](./oryp7) - System76 Oryx Pro (oryp7)
 - [oryp8](./oryp8) - System76 Oryx Pro (oryp8)
 - [oryp9](./oryp9) - System76 Oryx Pro (oryp9)
 - [qemu](./qemu) - QEMU (Virtualization)
+- [serw13](./serw13) - System76 Serval WS (serw13)
--- a/models/addw1/edk2.config
+++ b/models/addw1/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/addw2/edk2.config
+++ b/models/addw2/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/addw3/AlderLakeFspBinPkg/AlderLakeFspBinPkg.dec
+++ b/models/addw3/AlderLakeFspBinPkg/AlderLakeFspBinPkg.dec
@@ -0,0 +1,43 @@
+## @file
+#  Component description file for AlderLake Fsp Bin package.
+#
+# @copyright
+#  INTEL CONFIDENTIAL
+#  Copyright 2016 - 2019 Intel Corporation.
+#
+#  The source code contained or described herein and all documents related to the
+#  source code ("Material") are owned by Intel Corporation or its suppliers or
+#  licensors. Title to the Material remains with Intel Corporation or its suppliers
+#  and licensors. The Material may contain trade secrets and proprietary and
+#  confidential information of Intel Corporation and its suppliers and licensors,
+#  and is protected by worldwide copyright and trade secret laws and treaty
+#  provisions. No part of the Material may be used, copied, reproduced, modified,
+#  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+#  without Intel's prior express written permission.
+#
+#  No license under any patent, copyright, trade secret or other intellectual
+#  property right is granted to or conferred upon you by disclosure or delivery
+#  of the Materials, either expressly, by implication, inducement, estoppel or
+#  otherwise. Any license under such intellectual property rights must be
+#  express and approved by Intel in writing.
+#
+#  Unless otherwise agreed by Intel in writing, you may not remove or alter
+#  this notice or any other notice embedded in Materials by Intel or
+#  Intel's suppliers or licensors in any way.
+#
+#  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+#  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+#  the terms of your license agreement with Intel or your vendor. This file may
+#  be modified by the user, subject to additional terms of the license agreement.
+#
+# @par Specification
+##
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = AlderLakeFspBinPkg
+  PACKAGE_GUID                   = 5A536013-A46E-44AD-8B30-738235F77B06
+  PACKAGE_VERSION                = 1.02
+
+[Includes]
+  Include
--- a/models/addw3/AlderLakeFspBinPkg/Fsp.bsf
+++ b/models/addw3/AlderLakeFspBinPkg/Fsp.bsf
--- a/models/addw3/AlderLakeFspBinPkg/Fsp.fd
+++ b/models/addw3/AlderLakeFspBinPkg/Fsp.fd
--- a/models/addw3/AlderLakeFspBinPkg/FspPkgPcdShare.dsc
+++ b/models/addw3/AlderLakeFspBinPkg/FspPkgPcdShare.dsc
@@ -0,0 +1,114 @@
+## @file
+#  Platform description for DynamicEx PCDs, defined in FSP Package
+#  and shared with Board Package.
+#
+# @copyright
+#  INTEL CONFIDENTIAL
+#  Copyright 2018 - 2021 Intel Corporation.
+#
+#  The source code contained or described herein and all documents related to the
+#  source code ("Material") are owned by Intel Corporation or its suppliers or
+#  licensors. Title to the Material remains with Intel Corporation or its suppliers
+#  and licensors. The Material may contain trade secrets and proprietary and
+#  confidential information of Intel Corporation and its suppliers and licensors,
+#  and is protected by worldwide copyright and trade secret laws and treaty
+#  provisions. No part of the Material may be used, copied, reproduced, modified,
+#  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+#  without Intel's prior express written permission.
+#
+#  No license under any patent, copyright, trade secret or other intellectual
+#  property right is granted to or conferred upon you by disclosure or delivery
+#  of the Materials, either expressly, by implication, inducement, estoppel or
+#  otherwise. Any license under such intellectual property rights must be
+#  express and approved by Intel in writing.
+#
+#  Unless otherwise agreed by Intel in writing, you may not remove or alter
+#  this notice or any other notice embedded in Materials by Intel or
+#  Intel's suppliers or licensors in any way.
+#
+#  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+#  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+#  the terms of your license agreement with Intel or your vendor. This file may
+#  be modified by the user, subject to additional terms of the license agreement.
+#
+# @par Specification
+##
+
+[PcdsDynamicExDefault]
+
+  ## Specifies max supported number of Logical Processors.
+  # @Prompt Configure max supported number of Logical Processorss
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
+
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xC0000000
+  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+
+  ## Specifies the base address of the first microcode Patch in the microcode Region.
+  # @Prompt Microcode Region base address.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0
+
+  ## Specifies the size of the microcode Region.
+  # @Prompt Microcode Region size.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0
+
+  ## Specifies the AP wait loop state during POST phase.
+  #  The value is defined as below.
+  #  1: Place AP in the Hlt-Loop state.
+  #  2: Place AP in the Mwait-Loop state.
+  #  3: Place AP in the Run-Loop state.
+  # @Prompt The AP wait loop state.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+
+  ## Specifies the AP target C-state for Mwait during POST phase.
+  #  The default value 0 means C1 state.
+  #  The value is defined as below.<BR><BR>
+  # @Prompt The specified AP target C-state for Mwait.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+
+  #
+  # Enable ACPI S3 support in FSP by default
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1
+
+  ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
+  # @Prompt The pointer to a CPU S3 data buffer.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00
+
+  ## As input, specifies user's desired settings for enabling/disabling processor features.
+  ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
+  # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+
+  ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
+  #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
+  # @Prompt The memory size used for processor trace if processor trace is enabled.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0
+
+  ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
+  #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
+  # @Prompt The processor trace output scheme used when processor trace is enabled.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0
+
+  ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
+  # @Prompt Processor feature capabilities.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+
+  # Set SEV-ES defaults
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
+  gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0
+
+  ## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library
+  #  instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
+  #  only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
+  #  default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
+  # @Prompt S3 Boot Script Table Private Data pointer.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
+
+  ## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library
+  #  instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
+  #  only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
+  #  default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
+  # @Prompt S3 Boot Script Table Private Smm Data pointer.
+  # @ValidList  0x80000001 | 0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0
--- a/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfo.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfo.h
@@ -0,0 +1,54 @@
+/** @file
+  Intel Firmware Version Info (FVI) related definitions.
+
+  @todo update document/spec reference
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+  System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
+  http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf
+
+**/
+
+#ifndef __FIRMWARE_VERSION_INFO_H__
+#define __FIRMWARE_VERSION_INFO_H__
+
+#include <IndustryStandard/SmBios.h>
+
+#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME    "Firmware Version Info"
+
+#pragma pack(1)
+
+///
+/// Firmware Version Structure
+///
+typedef struct {
+  UINT8                       MajorVersion;
+  UINT8                       MinorVersion;
+  UINT8                       Revision;
+  UINT16                      BuildNumber;
+} INTEL_FIRMWARE_VERSION;
+
+///
+/// Firmware Version Info (FVI) Structure
+///
+typedef struct {
+  SMBIOS_TABLE_STRING         ComponentName;  ///< String Index of Component Name
+  SMBIOS_TABLE_STRING         VersionString;  ///< String Index of Version String
+  INTEL_FIRMWARE_VERSION      Version;        ///< Firmware version
+} INTEL_FIRMWARE_VERSION_INFO;
+
+///
+/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
+///
+typedef struct {
+  SMBIOS_STRUCTURE            Header;         ///< SMBIOS structure header
+  UINT8                       Count;          ///< Number of FVI entries in this structure
+  INTEL_FIRMWARE_VERSION_INFO Fvi[1];         ///< FVI structure(s)
+} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
+
+#pragma pack()
+
+#endif
--- a/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfoHob.h
@@ -0,0 +1,68 @@
+/** @file
+  Header file for Firmware Version Information
+
+ @copyright
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License which accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+  UINT8                          MajorVersion;
+  UINT8                          MinorVersion;
+  UINT8                          Revision;
+  UINT16                         BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
+  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
+  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+  UINT8                          Type;
+  UINT8                          Length;
+  UINT16                         Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
+  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
+  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspInfoHob.h
@@ -0,0 +1,56 @@
+/** @file
+  Header file for FSP Information HOB.
+
+@copyright
+  INTEL CONFIDENTIAL
+  Copyright 2017 - 2019 Intel Corporation.
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+
+  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+  the terms of your license agreement with Intel or your vendor. This file may
+  be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+
+#ifndef _FSP_INFO_HOB_H_
+#define _FSP_INFO_HOB_H_
+
+extern EFI_GUID gFspInfoGuid;
+
+#pragma pack (push, 1)
+
+typedef struct {
+UINT8              SiliconInitVersionMajor;
+UINT8              SiliconInitVersionMinor;
+UINT8              SiliconInitVersionRevision;
+UINT8              SiliconInitVersionBuild;
+UINT8              FspVersionRevision;
+UINT8              FspVersionBuild;
+UINT8              TimeStamp [12];
+UINT8              FspVersionMinor;
+} FSP_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _FSP_INFO_HOB_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE               0x545F4450554C4441        /* 'ADLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE               0x4D5F4450554C4441        /* 'ADLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F4450554C4441        /* 'ADLUPD_S' */
+
+#pragma pack()
+
+#endif
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspmUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspmUpd.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspsUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspsUpd.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/FsptUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FsptUpd.h
@@ -0,0 +1,357 @@
+/** @file
+
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+  UINT32                      MicrocodeRegionBase;
+
+/** Offset 0x0044
+**/
+  UINT32                      MicrocodeRegionSize;
+
+/** Offset 0x0048
+**/
+  UINT32                      CodeRegionBase;
+
+/** Offset 0x004C
+**/
+  UINT32                      CodeRegionSize;
+
+/** Offset 0x0050
+**/
+  UINT8                       Reserved[16];
+} FSPT_CORE_UPD;
+
+/** Fsp T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0060 - PcdSerialIoUartDebugEnable
+  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
+  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+  UINT8                       PcdSerialIoUartDebugEnable;
+
+/** Offset 0x0061 - PcdSerialIoUartNumber
+  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+  Core interface, it cannot be used for debug purpose.
+  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+  UINT8                       PcdSerialIoUartNumber;
+
+/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
+  Select SerialIo Uart Controller mode
+  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       PcdSerialIoUartMode;
+
+/** Offset 0x0063
+**/
+  UINT8                       Rsvd00;
+
+/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
+  Set default BaudRate Supported from 0 - default to 6000000
+**/
+  UINT32                      PcdSerialIoUartBaudRate;
+
+/** Offset 0x0068 - Pci Express Base Address
+  Base address to be programmed for Pci Express
+**/
+  UINT64                      PcdPciExpressBaseAddress;
+
+/** Offset 0x0070 - Pci Express Region Length
+  Region Length to be programmed for Pci Express
+**/
+  UINT32                      PcdPciExpressRegionLength;
+
+/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
+  Set default Parity.
+  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       PcdSerialIoUartParity;
+
+/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
+  Set default word length. 0: Default, 5,6,7,8
+**/
+  UINT8                       PcdSerialIoUartDataBits;
+
+/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
+  Set default stop bits.
+  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+  UINT8                       PcdSerialIoUartStopBits;
+
+/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
+  Enables UART hardware flow control, CTS and RTS lines.
+  0: Disable, 1:Enable
+**/
+  UINT8                       PcdSerialIoUartAutoFlow;
+
+/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
+  Select RX pin muxing for SerialIo UART used for debug
+**/
+  UINT32                      PcdSerialIoUartRxPinMux;
+
+/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
+  Select TX pin muxing for SerialIo UART used for debug
+**/
+  UINT32                      PcdSerialIoUartTxPinMux;
+
+/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
+  Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+  for possible values.
+**/
+  UINT32                      PcdSerialIoUartRtsPinMux;
+
+/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
+  Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+  for possible values.
+**/
+  UINT32                      PcdSerialIoUartCtsPinMux;
+
+/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
+  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
+  = SerialIoUartPci.
+**/
+  UINT32                      PcdSerialIoUartDebugMmioBase;
+
+/** Offset 0x008C - PcdLpcUartDebugEnable
+  Enable to initialize LPC Uart device in FSP.
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcdLpcUartDebugEnable;
+
+/** Offset 0x008D - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
+**/
+  UINT8                       PcdDebugInterfaceFlags;
+
+/** Offset 0x008E - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       PcdSerialDebugLevel;
+
+/** Offset 0x008F - ISA Serial Base selection
+  Select ISA Serial Base address. Default is 0x3F8.
+  0:0x3F8, 1:0x2F8
+**/
+  UINT8                       PcdIsaSerialUartBase;
+
+/** Offset 0x0090 - PcdSerialIo2ndUartEnable
+  Enable Additional SerialIo Uart device in FSP.
+  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+  UINT8                       PcdSerialIo2ndUartEnable;
+
+/** Offset 0x0091 - PcdSerialIo2ndUartNumber
+  Select SerialIo Uart Controller Number
+  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+  UINT8                       PcdSerialIo2ndUartNumber;
+
+/** Offset 0x0092 - PcdSerialIo2ndUartMode - FSPT
+  Select SerialIo Uart Controller mode
+  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       PcdSerialIo2ndUartMode;
+
+/** Offset 0x0093
+**/
+  UINT8                       Rsvd01;
+
+/** Offset 0x0094 - PcdSerialIo2ndUartBaudRate - FSPT
+  Set default BaudRate Supported from 0 - default to 6000000
+**/
+  UINT32                      PcdSerialIo2ndUartBaudRate;
+
+/** Offset 0x0098 - PcdSerialIo2ndUartParity - FSPT
+  Set default Parity.
+  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       PcdSerialIo2ndUartParity;
+
+/** Offset 0x0099 - PcdSerialIo2ndUartDataBits - FSPT
+  Set default word length. 0: Default, 5,6,7,8
+**/
+  UINT8                       PcdSerialIo2ndUartDataBits;
+
+/** Offset 0x009A - PcdSerialIo2ndUartStopBits - FSPT
+  Set default stop bits.
+  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+  UINT8                       PcdSerialIo2ndUartStopBits;
+
+/** Offset 0x009B - PcdSerialIo2ndUartAutoFlow - FSPT
+  Enables UART hardware flow control, CTS and RTS lines.
+  0: Disable, 1:Enable
+**/
+  UINT8                       PcdSerialIo2ndUartAutoFlow;
+
+/** Offset 0x009C - PcdSerialIo2ndUartRxPinMux - FSPT
+  Select RX pin muxing for SerialIo UART
+**/
+  UINT32                      PcdSerialIo2ndUartRxPinMux;
+
+/** Offset 0x00A0 - PcdSerialIo2ndUartTxPinMux - FSPT
+  Select TX pin muxing for SerialIo UART
+**/
+  UINT32                      PcdSerialIo2ndUartTxPinMux;
+
+/** Offset 0x00A4 - PcdSerialIo2ndUartRtsPinMux - FSPT
+  Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+  for possible values.
+**/
+  UINT32                      PcdSerialIo2ndUartRtsPinMux;
+
+/** Offset 0x00A8 - PcdSerialIo2ndUartCtsPinMux - FSPT
+  Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+  for possible values.
+**/
+  UINT32                      PcdSerialIo2ndUartCtsPinMux;
+
+/** Offset 0x00AC - PcdSerialIo2ndUartMmioBase - FSPT
+  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
+  = SerialIoUartPci.
+**/
+  UINT32                      PcdSerialIo2ndUartMmioBase;
+
+/** Offset 0x00B0
+**/
+  UINT32                      TopMemoryCacheSize;
+
+/** Offset 0x00B4 - FspDebugHandler
+  <b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
+**/
+  UINT32                      FspDebugHandler;
+
+/** Offset 0x00B8 - Serial Io SPI Chip Select Polarity
+  Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
+  1:SerialIoSpiCsActiveHigh
+**/
+  UINT8                       PcdSerialIoSpiCsPolarity[2];
+
+/** Offset 0x00BA - Serial Io SPI Chip Select Enable
+  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+  UINT8                       PcdSerialIoSpiCsEnable[2];
+
+/** Offset 0x00BC - Serial Io SPI Device Mode
+  When mode is set to Pci, controller is initalized in early stage. Available modes:
+  0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
+**/
+  UINT8                       PcdSerialIoSpiMode;
+
+/** Offset 0x00BD - Serial Io SPI Default Chip Select Output
+  Sets Default CS as Output. Available options: 0:CS0, 1:CS1
+**/
+  UINT8                       PcdSerialIoSpiDefaultCsOutput;
+
+/** Offset 0x00BE - Serial Io SPI Default Chip Select Mode HW/SW
+  Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
+**/
+  UINT8                       PcdSerialIoSpiCsMode;
+
+/** Offset 0x00BF - Serial Io SPI Default Chip Select State Low/High
+  Sets Default CS State Low or High. Available options: 0:Low, 1:High
+**/
+  UINT8                       PcdSerialIoSpiCsState;
+
+/** Offset 0x00C0 - Serial Io SPI Device Number
+  Select which Serial Io SPI controller is initalized in early stage.
+**/
+  UINT8                       PcdSerialIoSpiNumber;
+
+/** Offset 0x00C1
+**/
+  UINT8                       Rsvd02[3];
+
+/** Offset 0x00C4 - Serial Io SPI Device MMIO Base
+  Assigns MMIO for Serial Io SPI controller usage in early stage.
+**/
+  UINT32                      PcdSerialIoSpiMmioBase;
+
+/** Offset 0x00C8
+**/
+  UINT8                       ReservedFsptUpd1[16];
+} FSP_T_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPT_ARCH_UPD               FsptArchUpd;
+
+/** Offset 0x0040
+**/
+  FSPT_CORE_UPD               FsptCoreUpd;
+
+/** Offset 0x0060
+**/
+  FSP_T_CONFIG                FsptConfig;
+
+/** Offset 0x00D8
+**/
+  UINT8                       Rsvd03[6];
+
+/** Offset 0x00DE
+**/
+  UINT16                      UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
--- a/models/addw3/AlderLakeFspBinPkg/Include/GpioConfig.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/GpioConfig.h
@@ -0,0 +1,356 @@
+/** @file
+  Header file for GpioConfig structure used by GPIO library.
+
+ @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2014 - 2017 Intel Corporation.
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+
+  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+  the terms of your license agreement with Intel or your vendor. This file may
+  be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+  GPIO configuration structure used for pin programming.
+  Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+  /**
+  Pad Mode
+  Pad can be set as GPIO or one of its native functions.
+  When in native mode setting Direction (except Inversion), OutputState,
+  InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+  Refer to definition of GPIO_PAD_MODE.
+  Refer to EDS for each native mode according to the pad.
+  **/
+  UINT32 PadMode            : 5;
+  /**
+  Host Software Pad Ownership
+  Set pad to ACPI mode or GPIO Driver Mode.
+  Refer to definition of GPIO_HOSTSW_OWN.
+  **/
+  UINT32 HostSoftPadOwn     : 2;
+  /**
+  GPIO Direction
+  Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+  Refer to definition of GPIO_DIRECTION for supported settings.
+  **/
+  UINT32 Direction           : 6;
+  /**
+  Output State
+  Set Pad output value.
+  Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+  This setting takes place when output is enabled.
+  **/
+  UINT32 OutputState         : 2;
+  /**
+  GPIO Interrupt Configuration
+  Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+  This setting is applicable only if GPIO is in GpioMode with input enabled.
+  Refer to definition of GPIO_INT_CONFIG for supported settings.
+  **/
+  UINT32 InterruptConfig     : 9;
+  /**
+  GPIO Power Configuration.
+  This setting controls Pad Reset Configuration.
+  Refer to definition of GPIO_RESET_CONFIG for supported settings.
+  **/
+  UINT32 PowerConfig        : 8;
+  /**
+  GPIO Electrical Configuration
+  This setting controls pads termination and voltage tolerance.
+  Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+  **/
+  UINT32 ElectricalConfig   : 9;
+  /**
+  GPIO Lock Configuration
+  This setting controls pads lock.
+  Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+  **/
+  UINT32 LockConfig         : 4;
+  /**
+  Additional GPIO configuration
+  Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+  **/
+  UINT32 OtherSettings     :  2;
+  UINT32 RsvdBits          : 17;    ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+  GpioHardwareDefault        = 0x0    ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+  GPIO Pad Mode
+  Refer to GPIO documentation on native functions available for certain pad.
+  If GPIO is set to one of NativeX modes then following settings are not applicable
+  and can be skipped:
+  - Interrupt related settings
+  - Host Software Ownership
+  - Output/Input enabling/disabling
+  - Output lock
+**/
+typedef enum {
+  GpioPadModeGpio     = 0x1,
+  GpioPadModeNative1  = 0x3,
+  GpioPadModeNative2  = 0x5,
+  GpioPadModeNative3  = 0x7,
+  GpioPadModeNative4  = 0x9
+} GPIO_PAD_MODE;
+
+/**
+  Host Software Pad Ownership modes
+  This setting affects GPIO interrupt status registers. Depending on chosen ownership
+  some GPIO Interrupt status register get updated and other masked.
+  Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+  GpioHostOwnDefault = 0x0,   ///< Leave ownership value unmodified
+  /**
+  Set HOST ownership to ACPI.
+  Use this setting if pad is not going to be used by GPIO OS driver.
+  If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+  used for interrupts to work
+  **/
+  GpioHostOwnAcpi    = 0x1,
+  /**
+  Set HOST ownership to GPIO Driver mode.
+  Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+  GPIO OS Driver will be able to control the pad if appropriate entry in
+  ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+  **/
+  GpioHostOwnGpio    = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+  GpioDirDefault         = 0x0,                ///< Leave pad direction setting unmodified
+  GpioDirInOut           = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+  GpioDirInInvOut        = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+  GpioDirIn              = (0x3 | (0x1 << 3)), ///< Set pad for input only
+  GpioDirInInv           = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+  GpioDirOut             = 0x5,                ///< Set pad for output only
+  GpioDirNone            = 0x7                 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+  GPIO Output State
+  This field is relevant only if output is enabled
+**/
+typedef enum {
+  GpioOutDefault         = 0x0,  ///< Leave output value unmodified
+  GpioOutLow             = 0x1,  ///< Set output to low
+  GpioOutHigh            = 0x3   ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+  GPIO interrupt configuration
+  This setting is applicable only if pad is in GPIO mode and has input enabled.
+  GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+  and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+  EDS for details on this settings.
+  Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+  to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+  If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+  If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+  Not all GPIO are capable of generating an SMI or NMI interrupt.
+  When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+  interrupt cannot be shared and its IRQn number is not configurable.
+  Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+  If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+  exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+  This type of GPIO Driver interrupt doesn't have any additional routing setting
+  required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+  GpioIntDefault           = 0x0,  ///< Leave value of interrupt routing unmodified
+  GpioIntDis               = 0x1,  ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+  GpioIntNmi               = 0x3,  ///< Enable NMI interrupt only
+  GpioIntSmi               = 0x5,  ///< Enable SMI interrupt only
+  GpioIntSci               = 0x9,  ///< Enable SCI interrupt only
+  GpioIntApic              = 0x11, ///< Enable IOxAPIC interrupt only
+  GpioIntLevel       = (0x1 << 5), ///< Set interrupt as level triggered
+  GpioIntEdge        = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+  GpioIntLvlEdgDis   = (0x5 << 5), ///< Disable interrupt trigger
+  GpioIntBothEdge    = (0x7 << 5)  ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK  0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK    0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+  GPIO Power Configuration
+  GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+  be used to reset certain GPIO settings.
+  Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+
+
+  GpioResetDefault   = 0x00,        ///< Leave value of pad reset unmodified
+  ///
+  /// Deprecated settings. Maintained only for compatibility.
+  ///
+  GpioResetPwrGood   = 0x09,        ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
+  GpioResetDeep      = 0x0B,        ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
+  GpioResetNormal    = 0x0D,        ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
+  GpioResetResume    = 0x0F,        ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
+
+  ///
+  /// New GPIO reset configuration options
+  ///
+  /**
+  Resume Reset (RSMRST)
+    GPP: PadRstCfg = 00b = "Powergood"
+    GPD: PadRstCfg = 11b = "Resume Reset"
+  Pad setting will reset on:
+  - DeepSx transition
+  - G3
+  Pad settings will not reset on:
+  - S3/S4/S5 transition
+  - Warm/Cold/Global reset
+  **/
+  GpioResumeReset      = 0x01,
+  /**
+  Host Deep Reset
+    PadRstCfg = 01b = "Deep GPIO Reset"
+  Pad settings will reset on:
+  - Warm/Cold/Global reset
+  - DeepSx transition
+  - G3
+  Pad settings will not reset on:
+  - S3/S4/S5 transition
+  **/
+  GpioHostDeepReset    = 0x03,
+  /**
+  Platform Reset (PLTRST)
+    PadRstCfg = 10b = "GPIO Reset"
+  Pad settings will reset on:
+  - S3/S4/S5 transition
+  - Warm/Cold/Global reset
+  - DeepSx transition
+  - G3
+  **/
+  GpioPlatformReset    = 0x05,
+  /**
+  Deep Sleep Well Reset (DSW_PWROK)
+    GPP: not applicable
+    GPD: PadRstCfg = 00b = "Powergood"
+  Pad settings will reset on:
+  - G3
+  Pad settings will not reset on:
+  - S3/S4/S5 transition
+  - Warm/Cold/Global reset
+  - DeepSx transition
+  **/
+  GpioDswReset         = 0x07
+} GPIO_RESET_CONFIG;
+
+/**
+  GPIO Electrical Configuration
+  Set GPIO termination and Pad Tolerance (applicable only for some pads)
+  Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
+**/
+typedef enum {
+  GpioTermDefault          = 0x0,  ///< Leave termination setting unmodified
+  GpioTermNone             = 0x1,  ///< none
+  GpioTermWpd5K            = 0x5,  ///< 5kOhm weak pull-down
+  GpioTermWpd20K           = 0x9,  ///< 20kOhm weak pull-down
+  GpioTermWpu1K            = 0x13, ///< 1kOhm weak pull-up
+  GpioTermWpu2K            = 0x17, ///< 2kOhm weak pull-up
+  GpioTermWpu5K            = 0x15, ///< 5kOhm weak pull-up
+  GpioTermWpu20K           = 0x19, ///< 20kOhm weak pull-up
+  GpioTermWpu1K2K          = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+  /**
+  Native function controls pads termination
+  This setting is applicable only to some native modes.
+  Please check EDS to determine which native functionality
+  can control pads termination
+  **/
+  GpioTermNative     = 0x1F,
+  GpioNoTolerance1v8 = (0x1 << 5),   ///< Disable 1.8V pad tolerance
+  GpioTolerance1v8   = (0x3 << 5)    ///< Enable 1.8V pad tolerance
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK    0x1F   ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK  0x60   ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
+
+/**
+  GPIO LockConfiguration
+  Set GPIO configuration lock and output state lock.
+  GpioLockPadConfig and GpioLockOutputState can be OR'ed.
+  Lock settings reset is in Powergood domain. Care must be taken when using this setting
+  as fields it locks may be reset by a different signal and can be controllable
+  by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+  functions which allow to unlock a GPIO pad.
+**/
+typedef enum {
+  GpioLockDefault          = 0x0,  ///< Leave lock setting unmodified
+  GpioPadConfigLock        = 0x3,  ///< Lock Pad Configuration
+  GpioOutputStateLock      = 0x5   ///< Lock GPIO pad output value
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK  0x3  ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK    0x5  ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+  Other GPIO Configuration
+  GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+  Supported settings:
+   - RX raw override to '1' - allows to override input value to '1'
+      This setting is applicable only if in input mode (both in GPIO and native usage).
+      The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+  GpioRxRaw1Default           = 0x0,  ///< Use default input override value
+  GpioRxRaw1Dis               = 0x1,  ///< Don't override input
+  GpioRxRaw1En                = 0x3   ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK  0x3  ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/GpioSampleDef.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/GpioSampleDef.h
@@ -0,0 +1,404 @@
+/** @file
+
+Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __GPIOCONFIG_H__
+#define __GPIOCONFIG_H__
+#include <FsptUpd.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+/*
+  SKL LP GPIO pins
+  Use below for functions from PCH GPIO Lib which
+  require GpioPad as argument. Encoding used here
+  has all information required by library functions
+*/
+#define GPIO_SKL_LP_GPP_A0      0x02000000
+#define GPIO_SKL_LP_GPP_A1      0x02000001
+#define GPIO_SKL_LP_GPP_A2      0x02000002
+#define GPIO_SKL_LP_GPP_A3      0x02000003
+#define GPIO_SKL_LP_GPP_A4      0x02000004
+#define GPIO_SKL_LP_GPP_A5      0x02000005
+#define GPIO_SKL_LP_GPP_A6      0x02000006
+#define GPIO_SKL_LP_GPP_A7      0x02000007
+#define GPIO_SKL_LP_GPP_A8      0x02000008
+#define GPIO_SKL_LP_GPP_A9      0x02000009
+#define GPIO_SKL_LP_GPP_A10     0x0200000A
+#define GPIO_SKL_LP_GPP_A11     0x0200000B
+#define GPIO_SKL_LP_GPP_A12     0x0200000C
+#define GPIO_SKL_LP_GPP_A13     0x0200000D
+#define GPIO_SKL_LP_GPP_A14     0x0200000E
+#define GPIO_SKL_LP_GPP_A15     0x0200000F
+#define GPIO_SKL_LP_GPP_A16     0x02000010
+#define GPIO_SKL_LP_GPP_A17     0x02000011
+#define GPIO_SKL_LP_GPP_A18     0x02000012
+#define GPIO_SKL_LP_GPP_A19     0x02000013
+#define GPIO_SKL_LP_GPP_A20     0x02000014
+#define GPIO_SKL_LP_GPP_A21     0x02000015
+#define GPIO_SKL_LP_GPP_A22     0x02000016
+#define GPIO_SKL_LP_GPP_A23     0x02000017
+#define GPIO_SKL_LP_GPP_B0      0x02010000
+#define GPIO_SKL_LP_GPP_B1      0x02010001
+#define GPIO_SKL_LP_GPP_B2      0x02010002
+#define GPIO_SKL_LP_GPP_B3      0x02010003
+#define GPIO_SKL_LP_GPP_B4      0x02010004
+#define GPIO_SKL_LP_GPP_B5      0x02010005
+#define GPIO_SKL_LP_GPP_B6      0x02010006
+#define GPIO_SKL_LP_GPP_B7      0x02010007
+#define GPIO_SKL_LP_GPP_B8      0x02010008
+#define GPIO_SKL_LP_GPP_B9      0x02010009
+#define GPIO_SKL_LP_GPP_B10     0x0201000A
+#define GPIO_SKL_LP_GPP_B11     0x0201000B
+#define GPIO_SKL_LP_GPP_B12     0x0201000C
+#define GPIO_SKL_LP_GPP_B13     0x0201000D
+#define GPIO_SKL_LP_GPP_B14     0x0201000E
+#define GPIO_SKL_LP_GPP_B15     0x0201000F
+#define GPIO_SKL_LP_GPP_B16     0x02010010
+#define GPIO_SKL_LP_GPP_B17     0x02010011
+#define GPIO_SKL_LP_GPP_B18     0x02010012
+#define GPIO_SKL_LP_GPP_B19     0x02010013
+#define GPIO_SKL_LP_GPP_B20     0x02010014
+#define GPIO_SKL_LP_GPP_B21     0x02010015
+#define GPIO_SKL_LP_GPP_B22     0x02010016
+#define GPIO_SKL_LP_GPP_B23     0x02010017
+#define GPIO_SKL_LP_GPP_C0      0x02020000
+#define GPIO_SKL_LP_GPP_C1      0x02020001
+#define GPIO_SKL_LP_GPP_C2      0x02020002
+#define GPIO_SKL_LP_GPP_C3      0x02020003
+#define GPIO_SKL_LP_GPP_C4      0x02020004
+#define GPIO_SKL_LP_GPP_C5      0x02020005
+#define GPIO_SKL_LP_GPP_C6      0x02020006
+#define GPIO_SKL_LP_GPP_C7      0x02020007
+#define GPIO_SKL_LP_GPP_C8      0x02020008
+#define GPIO_SKL_LP_GPP_C9      0x02020009
+#define GPIO_SKL_LP_GPP_C10     0x0202000A
+#define GPIO_SKL_LP_GPP_C11     0x0202000B
+#define GPIO_SKL_LP_GPP_C12     0x0202000C
+#define GPIO_SKL_LP_GPP_C13     0x0202000D
+#define GPIO_SKL_LP_GPP_C14     0x0202000E
+#define GPIO_SKL_LP_GPP_C15     0x0202000F
+#define GPIO_SKL_LP_GPP_C16     0x02020010
+#define GPIO_SKL_LP_GPP_C17     0x02020011
+#define GPIO_SKL_LP_GPP_C18     0x02020012
+#define GPIO_SKL_LP_GPP_C19     0x02020013
+#define GPIO_SKL_LP_GPP_C20     0x02020014
+#define GPIO_SKL_LP_GPP_C21     0x02020015
+#define GPIO_SKL_LP_GPP_C22     0x02020016
+#define GPIO_SKL_LP_GPP_C23     0x02020017
+#define GPIO_SKL_LP_GPP_D0      0x02030000
+#define GPIO_SKL_LP_GPP_D1      0x02030001
+#define GPIO_SKL_LP_GPP_D2      0x02030002
+#define GPIO_SKL_LP_GPP_D3      0x02030003
+#define GPIO_SKL_LP_GPP_D4      0x02030004
+#define GPIO_SKL_LP_GPP_D5      0x02030005
+#define GPIO_SKL_LP_GPP_D6      0x02030006
+#define GPIO_SKL_LP_GPP_D7      0x02030007
+#define GPIO_SKL_LP_GPP_D8      0x02030008
+#define GPIO_SKL_LP_GPP_D9      0x02030009
+#define GPIO_SKL_LP_GPP_D10     0x0203000A
+#define GPIO_SKL_LP_GPP_D11     0x0203000B
+#define GPIO_SKL_LP_GPP_D12     0x0203000C
+#define GPIO_SKL_LP_GPP_D13     0x0203000D
+#define GPIO_SKL_LP_GPP_D14     0x0203000E
+#define GPIO_SKL_LP_GPP_D15     0x0203000F
+#define GPIO_SKL_LP_GPP_D16     0x02030010
+#define GPIO_SKL_LP_GPP_D17     0x02030011
+#define GPIO_SKL_LP_GPP_D18     0x02030012
+#define GPIO_SKL_LP_GPP_D19     0x02030013
+#define GPIO_SKL_LP_GPP_D20     0x02030014
+#define GPIO_SKL_LP_GPP_D21     0x02030015
+#define GPIO_SKL_LP_GPP_D22     0x02030016
+#define GPIO_SKL_LP_GPP_D23     0x02030017
+#define GPIO_SKL_LP_GPP_E0      0x02040000
+#define GPIO_SKL_LP_GPP_E1      0x02040001
+#define GPIO_SKL_LP_GPP_E2      0x02040002
+#define GPIO_SKL_LP_GPP_E3      0x02040003
+#define GPIO_SKL_LP_GPP_E4      0x02040004
+#define GPIO_SKL_LP_GPP_E5      0x02040005
+#define GPIO_SKL_LP_GPP_E6      0x02040006
+#define GPIO_SKL_LP_GPP_E7      0x02040007
+#define GPIO_SKL_LP_GPP_E8      0x02040008
+#define GPIO_SKL_LP_GPP_E9      0x02040009
+#define GPIO_SKL_LP_GPP_E10     0x0204000A
+#define GPIO_SKL_LP_GPP_E11     0x0204000B
+#define GPIO_SKL_LP_GPP_E12     0x0204000C
+#define GPIO_SKL_LP_GPP_E13     0x0204000D
+#define GPIO_SKL_LP_GPP_E14     0x0204000E
+#define GPIO_SKL_LP_GPP_E15     0x0204000F
+#define GPIO_SKL_LP_GPP_E16     0x02040010
+#define GPIO_SKL_LP_GPP_E17     0x02040011
+#define GPIO_SKL_LP_GPP_E18     0x02040012
+#define GPIO_SKL_LP_GPP_E19     0x02040013
+#define GPIO_SKL_LP_GPP_E20     0x02040014
+#define GPIO_SKL_LP_GPP_E21     0x02040015
+#define GPIO_SKL_LP_GPP_E22     0x02040016
+#define GPIO_SKL_LP_GPP_E23     0x02040017
+#define GPIO_SKL_LP_GPP_F0      0x02050000
+#define GPIO_SKL_LP_GPP_F1      0x02050001
+#define GPIO_SKL_LP_GPP_F2      0x02050002
+#define GPIO_SKL_LP_GPP_F3      0x02050003
+#define GPIO_SKL_LP_GPP_F4      0x02050004
+#define GPIO_SKL_LP_GPP_F5      0x02050005
+#define GPIO_SKL_LP_GPP_F6      0x02050006
+#define GPIO_SKL_LP_GPP_F7      0x02050007
+#define GPIO_SKL_LP_GPP_F8      0x02050008
+#define GPIO_SKL_LP_GPP_F9      0x02050009
+#define GPIO_SKL_LP_GPP_F10     0x0205000A
+#define GPIO_SKL_LP_GPP_F11     0x0205000B
+#define GPIO_SKL_LP_GPP_F12     0x0205000C
+#define GPIO_SKL_LP_GPP_F13     0x0205000D
+#define GPIO_SKL_LP_GPP_F14     0x0205000E
+#define GPIO_SKL_LP_GPP_F15     0x0205000F
+#define GPIO_SKL_LP_GPP_F16     0x02050010
+#define GPIO_SKL_LP_GPP_F17     0x02050011
+#define GPIO_SKL_LP_GPP_F18     0x02050012
+#define GPIO_SKL_LP_GPP_F19     0x02050013
+#define GPIO_SKL_LP_GPP_F20     0x02050014
+#define GPIO_SKL_LP_GPP_F21     0x02050015
+#define GPIO_SKL_LP_GPP_F22     0x02050016
+#define GPIO_SKL_LP_GPP_F23     0x02050017
+#define GPIO_SKL_LP_GPP_G0      0x02060000
+#define GPIO_SKL_LP_GPP_G1      0x02060001
+#define GPIO_SKL_LP_GPP_G2      0x02060002
+#define GPIO_SKL_LP_GPP_G3      0x02060003
+#define GPIO_SKL_LP_GPP_G4      0x02060004
+#define GPIO_SKL_LP_GPP_G5      0x02060005
+#define GPIO_SKL_LP_GPP_G6      0x02060006
+#define GPIO_SKL_LP_GPP_G7      0x02060007
+#define GPIO_SKL_LP_GPD0        0x02070000
+#define GPIO_SKL_LP_GPD1        0x02070001
+#define GPIO_SKL_LP_GPD2        0x02070002
+#define GPIO_SKL_LP_GPD3        0x02070003
+#define GPIO_SKL_LP_GPD4        0x02070004
+#define GPIO_SKL_LP_GPD5        0x02070005
+#define GPIO_SKL_LP_GPD6        0x02070006
+#define GPIO_SKL_LP_GPD7        0x02070007
+#define GPIO_SKL_LP_GPD8        0x02070008
+#define GPIO_SKL_LP_GPD9        0x02070009
+#define GPIO_SKL_LP_GPD10       0x0207000A
+#define GPIO_SKL_LP_GPD11       0x0207000B
+
+#define END_OF_GPIO_TABLE   0xFFFFFFFF
+
+//
+//AlderLake S GPIO PCIe SLOT RTD3 and PEG reset pins.
+//
+#define GPIO_VER4_S_GPP_E2      0x080E0002
+#define GPIO_VER4_S_GPP_E3      0x080E0003
+#define GPIO_VER4_S_GPP_F11     0x0810000B
+#define GPIO_VER4_S_GPP_F12     0x0810000C
+#define GPIO_VER4_S_GPP_F13     0x0810000D
+
+//Sample GPIO Table
+
+//
+//AlderLake S Gpio table for assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase.
+//
+static GPIO_INIT_CONFIG mAdlSPcieRstPinGpioTable[] =
+{
+  { GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PEG_1 RTD3 Reset
+  { GPIO_VER4_S_GPP_E3,   {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PEG_2 RTD3 Reset Sinai DR0 (Rework)
+  { GPIO_VER4_S_GPP_F11,  {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PCIe SLOT_1 RTD3 Reset MIPI60 (Rework)
+  { GPIO_VER4_S_GPP_F12,  {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PCIe SLOT_2 RTD3 Reset MIPI60 (Rework)
+  { GPIO_VER4_S_GPP_F13,  {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PCIe SLOT_3 RTD3 Reset MIPI60 (Rework)
+  { 0x0 }  // terminator
+};
+
+static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
+{
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//H_RCIN_N
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//LPC_FRAME_ESPI_CS_N
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//INT_SERIRQ
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A7,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SLP_S0ix_R_N
+  {GPIO_SKL_LP_GPP_A8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_CLKRUN_N
+//skip for eSPI function    {GPIO_SKL_LP_GPP_A9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
+  {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//PCH_CLK_PCI_TPM
+  {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//EC_HID_INTR
+  {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+  {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SUS_PWR_ACK_R
+//skip for eSPI function    {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
+  {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SUSACK_R_N
+  {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_1P8_SEL
+  {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_PWR_EN_N
+  {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_0_SENSOR
+  {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_1_SENSOR
+  {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_2_SENSOR
+  {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GNSS_CHUB_IRQ
+  {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//FPS_SLP_N
+  {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//FPS_DRDY
+  {GPIO_SKL_LP_GPP_B0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID0
+  {GPIO_SKL_LP_GPP_B1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID1
+  {GPIO_SKL_LP_GPP_B2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GP_VRALERTB
+  {GPIO_SKL_LP_GPP_B3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,  GpioTermNone}},//TCH_PAD_INTR_R_N
+  {GPIO_SKL_LP_GPP_B4,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//BT_RF_KILL_N
+  {GPIO_SKL_LP_GPP_B5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_BT_UART_WAKE_N
+  // {GPIO_SKL_LP_GPP_B6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT1_N
+  // {GPIO_SKL_LP_GPP_B7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
+  // {GPIO_SKL_LP_GPP_B8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
+  // {GPIO_SKL_LP_GPP_B9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
+  // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WLAN_N
+  {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//MPHY_EXT_PWR_GATEB
+  {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SLP_S0_N
+  {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PLT_RST_N
+  {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_PWREN
+  {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_DFU
+  {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
+  {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset,  GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
+  {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
+  {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,   GpioTermNone}},//FPS_GSPI1_CS_R1_N
+  {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
+  {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
+  {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
+  {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
+  {GPIO_SKL_LP_GPP_C0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SMB_CLK
+  {GPIO_SKL_LP_GPP_C1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SMB_DATA
+  {GPIO_SKL_LP_GPP_C2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
+  {GPIO_SKL_LP_GPP_C3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_CLK
+  {GPIO_SKL_LP_GPP_C4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_DATA
+  {GPIO_SKL_LP_GPP_C5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
+  {GPIO_SKL_LP_GPP_C6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML1_CLK
+  {GPIO_SKL_LP_GPP_C7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SML1_DATA
+  {GPIO_SKL_LP_GPP_C8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RXD
+  {GPIO_SKL_LP_GPP_C9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_TXD
+  {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RTS_N
+  {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_CTS_N
+  {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
+  {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
+  {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
+  {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
+  {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SDA
+  {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SCL
+  {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SDA
+  {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SCL
+  {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RXD
+  {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_TXD
+  {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RTS_N
+  {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_CTS_N
+  {GPIO_SKL_LP_GPP_D0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CS_N
+  {GPIO_SKL_LP_GPP_D1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CLK
+  {GPIO_SKL_LP_GPP_D2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MISO
+  {GPIO_SKL_LP_GPP_D3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MOSI
+  {GPIO_SKL_LP_GPP_D4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CSI2_FLASH_STROBE
+  {GPIO_SKL_LP_GPP_D5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SDA
+  {GPIO_SKL_LP_GPP_D6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SCL
+  {GPIO_SKL_LP_GPP_D7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SDA
+  {GPIO_SKL_LP_GPP_D8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SCL
+  {GPIO_SKL_LP_GPP_D9,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//HOME_BTN
+  {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SCREEN_LOCK_PCH
+  {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_UP_PCH
+  {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_DOWN_PCH
+  {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
+  {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
+  {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RTS_N
+  {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
+  {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_1
+  {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_1
+  {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_0
+  {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_0
+  {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO2
+  {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO3
+  {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP_MCLK
+  {GPIO_SKL_LP_GPP_E0,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//SPI_TPM_HDR_IRQ_N
+  {GPIO_SKL_LP_GPP_E1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA_ODD_PRSNT_N
+  {GPIO_SKL_LP_GPP_E2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
+  {GPIO_SKL_LP_GPP_E3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioResumeReset,  GpioTermNone}},//EINK_SSR_DFU_N
+  {GPIO_SKL_LP_GPP_E4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_RESET
+  {GPIO_SKL_LP_GPP_E5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
+  {GPIO_SKL_LP_GPP_E6,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
+  {GPIO_SKL_LP_GPP_E8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SATA_LED_N
+  {GPIO_SKL_LP_GPP_E9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_0_WP1_OTG_N
+  {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_1_WP4_N
+  {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
+  {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_IRQ
+  {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_HPD_Q
+  {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_HPD_Q
+  {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset,  GpioTermNone}},//SMC_EXTSMI_R_N
+  {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//SMC_RUNTIME_SCI_R_N
+  {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EDP_HPD
+  {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_CTRL_CLK
+  {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI1_CTRL_DATA
+  {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_CTRL_CLK
+  {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI2_CTRL_DATA
+  {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_CODEC_IRQ
+  {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_RST_N
+  {GPIO_SKL_LP_GPP_F0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SCLK
+  {GPIO_SKL_LP_GPP_F1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SFRM
+  {GPIO_SKL_LP_GPP_F2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_TXD
+  {GPIO_SKL_LP_GPP_F3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_RXD
+  {GPIO_SKL_LP_GPP_F4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
+  {GPIO_SKL_LP_GPP_F5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
+  {GPIO_SKL_LP_GPP_F6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
+  {GPIO_SKL_LP_GPP_F7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
+  {GPIO_SKL_LP_GPP_F8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
+  {GPIO_SKL_LP_GPP_F9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
+  {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
+  {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
+  {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CMD
+  {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA0
+  {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA1
+  {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA2
+  {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA3
+  {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA4
+  {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA5
+  {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA6
+  {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA7
+  {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_RCLK
+  {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CLK
+  {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
+  {GPIO_SKL_LP_GPP_G0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CMD
+  {GPIO_SKL_LP_GPP_G1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA0
+  {GPIO_SKL_LP_GPP_G2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA1
+  {GPIO_SKL_LP_GPP_G3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA2
+  {GPIO_SKL_LP_GPP_G4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA3
+  {GPIO_SKL_LP_GPP_G5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CDB
+  {GPIO_SKL_LP_GPP_G6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CLK
+  {GPIO_SKL_LP_GPP_G7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_WP
+  {GPIO_SKL_LP_GPD0,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_BATLOW_R_N
+  {GPIO_SKL_LP_GPD1,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//AC_PRESENT_R
+  {GPIO_SKL_LP_GPD2,   {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset,  GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
+  {GPIO_SKL_LP_GPD3,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermWpu20K}},//PM_PWRBTN_R_N
+  {GPIO_SKL_LP_GPD4,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S3_R_N
+  {GPIO_SKL_LP_GPD5,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S4_R_N
+  {GPIO_SKL_LP_GPD6,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_M_R_N
+  {GPIO_SKL_LP_GPD7,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
+  {GPIO_SKL_LP_GPD8,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SUS_CLK
+  {GPIO_SKL_LP_GPD9,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PCH_SLP_WLAN_N
+  {GPIO_SKL_LP_GPD10,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S5_R_N
+  {GPIO_SKL_LP_GPD11,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_LANPHY_ENABLE
+  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
+};
+
+#endif   //_GPIO_CONFIG_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/HobUsageDataHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/HobUsageDataHob.h
@@ -0,0 +1,59 @@
+/** @file
+  Definitions for Hob Usage data HOB
+
+@copyright
+  INTEL CONFIDENTIAL
+  Copyright 2017 Intel Corporation.
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+
+  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+  the terms of your license agreement with Intel or your vendor. This file may
+  be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+
+#ifndef _HOB_USAGE_DATA_HOB_H_
+#define _HOB_USAGE_DATA_HOB_H_
+
+extern EFI_GUID gHobUsageDataGuid;
+
+#pragma pack (push, 1)
+
+/**
+  Hob Usage Data Hob
+
+  <b>Revision 1:</b>
+  - Initial version.
+**/
+typedef struct {
+  EFI_PHYSICAL_ADDRESS EfiMemoryTop;
+  EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
+  EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
+  EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
+  UINTN                FreeMemory;
+} HOB_USAGE_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _HOB_USAGE_DATA_HOB_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/MemInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/MemInfoHob.h
@@ -0,0 +1,337 @@
+/** @file
+  This file contains definitions required for creation of
+  Memory S3 Save data, Memory Info data and Memory Platform
+  data hobs.
+
+@copyright
+  INTEL CONFIDENTIAL
+  Copyright 1999 - 2021 Intel Corporation.
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+
+  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+  the terms of your license agreement with Intel or your vendor. This file may
+  be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE        2
+#define MAX_CH          4
+#define MAX_DIMM        2
+#define HOB_MAX_SAGV_POINTS 4
+
+///
+/// Host reset states from MRC.
+///
+#define  WARM_BOOT        2
+
+#define R_MC_CHNL_RANK_PRESENT  0x7C
+#define   B_RANK0_PRS           BIT0
+#define   B_RANK1_PRS           BIT1
+#define   B_RANK2_PRS           BIT4
+#define   B_RANK3_PRS           BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+  UINT16  HobType;
+  UINT16  HobLength;
+  UINT32  Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+  EFI_HOB_GENERIC_HEADER  Header;
+  EFI_GUID                Name;
+  ///
+  /// Guid specific data goes here
+  ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+  UINT8  Major;     ///< Major version number
+  UINT8  Minor;     ///< Minor version number
+  UINT8  Rev;       ///< Revision number
+  UINT8  Build;     ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT     0  // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED        1  // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT         2  // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED     0  // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED    1  // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT     2  // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3  // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__                 //The below values are originated from MrcCommonTypes.h
+  #ifndef INT32_MAX
+  #define INT32_MAX                       (0x7FFFFFFF)
+  #endif  //INT32_MAX
+typedef enum {
+  bmCold,                                 ///< Cold boot
+  bmWarm,                                 ///< Warm boot
+  bmS3,                                   ///< S3 resume
+  bmFast,                                 ///< Fast boot
+  MrcBootModeMax,                         ///< MRC_BOOT_MODE enumeration maximum value.
+  MrcBootModeDelim = INT32_MAX            ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif  //__MRC_BOOT_MODE__
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR5
+#define MRC_DDR_TYPE_DDR5     1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR5
+#define MRC_DDR_TYPE_LPDDR5   2
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4   3
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN  4
+#endif
+
+#define MAX_PROFILE_NUM     7 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
+
+#define MAX_TRACE_REGION             5
+#define MAX_TRACE_CACHE_TYPE         2
+
+//
+// DIMM timings
+//
+typedef struct {
+  UINT32 tCK;       ///< Memory cycle time, in femtoseconds.
+  UINT16 NMode;     ///< Number of tCK cycles for the channel DIMM's command rate mode.
+  UINT16 tCL;       ///< Number of tCK cycles for the channel DIMM's CAS latency.
+  UINT16 tCWL;      ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+  UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+  UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+  UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+  UINT16 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+  UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+  UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRFC4;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRPab;     ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+  UINT16 tRRD;      ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+  UINT16 tRRD_L;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+  UINT16 tRRD_S;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+  UINT16 tRTP;      ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+  UINT16 tWR;       ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+  UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+  UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+  UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+  UINT16 tCCD_L;  ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+typedef struct {
+  UINT16 tRDPRE;     ///< Read CAS to Precharge cmd delay
+} MRC_IP_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+  UINT8            Status;                  ///< See MrcDimmStatus for the definition of this field.
+  UINT8            DimmId;
+  UINT32           DimmCapacity;            ///< DIMM size in MBytes.
+  UINT16           MfgId;
+  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+  UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
+  UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+  UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+  UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+  UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz
+  UINT8            MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+  UINT8            Status;                  ///< Indicates whether this channel should be used.
+  UINT8            ChannelId;
+  UINT8            DimmCount;               ///< Number of valid DIMMs that exist in the channel.
+  MRC_CH_TIMING    Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+  DIMM_INFO        DimmInfo[MAX_DIMM];      ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+  UINT8            Status;                  ///< Indicates whether this controller should be used.
+  UINT16           DeviceId;                ///< The PCI device id of this memory controller.
+  UINT8            RevisionId;              ///< The PCI revision id of this memory controller.
+  UINT8            ChannelCount;            ///< Number of valid channels that exist on the controller.
+  CHANNEL_INFO     ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+  UINT64   BaseAddress;   ///< Trace Base Address
+  UINT64   TotalSize;     ///< Total Trace Region of Same Cache type
+  UINT8    CacheType;     ///< Trace Cache Type
+  UINT8    ErrorCode;     ///< Trace Region Allocation Fail Error code
+  UINT8    Rsvd[2];
+} PSMI_MEM_INFO;
+
+/// This data structure contains per-SaGv timing values that are considered output by the MRC.
+typedef struct {
+  UINT32        DataRate;    ///< The memory rate for the current SaGv Point in units of MT/s
+  MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
+  MRC_IP_TIMING IpTiming;    ///< Timings used for this entry's corresponding SaGv Point - IP specific
+} HOB_SAGV_TIMING_OUT;
+
+/// This data structure contains SAGV config values that are considered output by the MRC.
+typedef struct {
+  UINT32              NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
+  UINT32              SaGvPointMask;        ///< Bit mask where each bit indicates an enabled SAGV point.
+  HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
+} HOB_SAGV_INFO;
+
+typedef struct {
+  UINT8             Revision;
+  UINT16            DataWidth;              ///< Data width, in bits, of this memory device
+  /** As defined in SMBIOS 3.0 spec
+    Section 7.18.2 and Table 75
+  **/
+  UINT8             MemoryType;             ///< DDR type: DDR3, DDR4, or LPDDR3
+  UINT16            MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+  UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+  /** As defined in SMBIOS 3.0 spec
+    Section 7.17.3 and Table 72
+  **/
+  UINT8             ErrorCorrectionType;
+
+  SiMrcVersion      Version;
+  BOOLEAN           EccSupport;
+  UINT8             MemoryProfile;
+  UINT8             IsDMBRunning;                      ///< Deprecated.
+  UINT32            TotalPhysicalMemorySize;
+  UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+  ///
+  /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
+  /// Bit 0: XMP Profile 1 capability status
+  /// Bit 1: XMP Profile 2 capability status
+  /// Bit 2: XMP Profile 3 capability status
+  /// Bit 3: User Profile 4 capability status
+  /// Bit 4: User Profile 5 capability status
+  ///
+  UINT8             XmpProfileEnable;
+  UINT8             XmpConfigWarning;                  ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
+  UINT8             Ratio;                             ///< DDR Frequency Ratio, Max Value 255
+  UINT8             RefClk;
+  UINT32            VddVoltage[MAX_PROFILE_NUM];
+  UINT32            VddqVoltage[MAX_PROFILE_NUM];
+  UINT32            VppVoltage[MAX_PROFILE_NUM];
+  CONTROLLER_INFO   Controller[MAX_NODE];
+  UINT16            Ratio_UINT16;                      ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
+  UINT32            NumPopulatedChannels;              ///< Total number of memory channels populated
+  HOB_SAGV_INFO     SagvConfigInfo;                    ///< This data structure contains SAGV config values that are considered output by the MRC.
+  UINT16            TotalMemWidth;                     ///< Total Memory Width in bits from all populated channels
+  BOOLEAN           MemorySpeedReducedWrongDimmSlot;   ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
+  BOOLEAN           MemorySpeedReducedMixedConfig;     ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
+  BOOLEAN           DynamicMemoryBoostTrainingFailed;  ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
+} MEMORY_INFO_DATA_HOB;
+
+/**
+  Memory Platform Data Hob
+
+  <b>Revision 1:</b>
+  - Initial version.
+  <b>Revision 2:</b>
+  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+  UINT8             Revision;
+  UINT8             Reserved[3];
+  UINT32            BootMode;
+  UINT32            TsegSize;
+  UINT32            TsegBase;
+  UINT32            PrmrrSize;
+  UINT64            PrmrrBase;
+  UINT32            GttBase;
+  UINT32            MmioSize;
+  UINT32            PciEBaseAddress;
+  PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
+  PSMI_MEM_INFO     PsmiRegionInfo[MAX_TRACE_REGION];
+  BOOLEAN           MrcBasicMemoryTestPass;
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+  EFI_HOB_GUID_TYPE    EfiHobGuidType;
+  MEMORY_PLATFORM_DATA Data;
+  UINT8                *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/SmbiosCacheInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/SmbiosCacheInfoHob.h
@@ -0,0 +1,56 @@
+/** @file
+  Header file for SMBIOS Cache Info HOB
+
+ @copyright
+  INTEL CONFIDENTIAL
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License which accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  System Management BIOS (SMBIOS) Reference Specification v3.1.0
+  dated 2016-Nov-16 (DSP0134)
+  http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
+**/
+
+#ifndef _SMBIOS_CACHE_INFO_HOB_H_
+#define _SMBIOS_CACHE_INFO_HOB_H_
+
+#include <Uefi.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// SMBIOS Cache Info HOB Structure
+///
+typedef struct {
+  UINT16     ProcessorSocketNumber;
+  UINT16     NumberOfCacheLevels;         ///< Based on Number of Cache Types L1/L2/L3
+  UINT8      SocketDesignationStrIndex;   ///< String Index in the string Buffer. Example "L1-CACHE"
+  UINT16     CacheConfiguration;          ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
+  UINT16     MaxCacheSize;                ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  UINT16     InstalledSize;               ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  UINT16     SupportedSramType;           ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
+  UINT16     CurrentSramType;             ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
+  UINT8      CacheSpeed;                  ///< Cache Speed in nanoseconds. 0 if speed is unknown.
+  UINT8      ErrorCorrectionType;         ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
+  UINT8      SystemCacheType;             ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
+  UINT8      Associativity;               ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
+  //
+  // Add for smbios 3.1.0
+  //
+  UINT32     MaximumCacheSize2;           ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  UINT32     InstalledSize2;              ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  /**
+  String Buffer - each string terminated by NULL "0x00"
+  String buffer terminated by double NULL "0x0000"
+  **/
+} SMBIOS_CACHE_INFO;
+#pragma pack()
+
+#endif // _SMBIOS_CACHE_INFO_HOB_H_
--- a/models/addw3/AlderLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h
@@ -0,0 +1,67 @@
+/** @file
+  Header file for SMBIOS Processor Info HOB
+
+ @copyright
+  INTEL CONFIDENTIAL
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  System Management BIOS (SMBIOS) Reference Specification v3.1.0
+  dated 2016-Nov-16 (DSP0134)
+  http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
+**/
+
+#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
+#define _SMBIOS_PROCESSOR_INFO_HOB_H_
+
+#include <Uefi.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// SMBIOS Processor Info HOB Structure
+///
+typedef struct {
+  UINT16     TotalNumberOfSockets;
+  UINT16     CurrentSocketNumber;
+  UINT8      ProcessorType;                 ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
+  /** This info is used for both ProcessorFamily and ProcessorFamily2 fields
+      See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
+  **/
+  UINT16     ProcessorFamily;
+  UINT8      ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
+  UINT64     ProcessorId;                   ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
+  UINT8      ProcessorVersionStrIndex;      ///< Index of the String in the String Buffer
+  UINT8      Voltage;                       ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
+  UINT16     ExternalClockInMHz;            ///< External Clock Frequency. Set to 0 if unknown.
+  UINT16     MaxSpeedInMHz;                 ///< Snapshot of Max processor speed during boot
+  UINT16     CurrentSpeedInMHz;             ///< Snapshot of current processor speed during boot
+  UINT8      Status;                        ///< Format defined in the SMBIOS Spec v3.1 Table 21
+  UINT8      ProcessorUpgrade;              ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
+  /** This info is used for both CoreCount & CoreCount2 fields
+      See detailed description in SMBIOS Spec v3.1 Section 7.5.6
+  **/
+  UINT16     CoreCount;
+  /** This info is used for both CoreEnabled & CoreEnabled2 fields
+      See detailed description in SMBIOS Spec v3.1 Section 7.5.7
+  **/
+  UINT16     EnabledCoreCount;
+  /** This info is used for both ThreadCount & ThreadCount2 fields
+      See detailed description in SMBIOS Spec v3.1 Section 7.5.8
+  **/
+  UINT16     ThreadCount;
+  UINT16     ProcessorCharacteristics;      ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
+  /**
+  String Buffer - each string terminated by NULL "0x00"
+  String buffer terminated by double NULL "0x0000"
+  **/
+} SMBIOS_PROCESSOR_INFO;
+#pragma pack()
+
+#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
--- a/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c
+++ b/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c
@@ -0,0 +1,49 @@
+/** @file
+  Library instance to list all DynamicEx PCD FSP consumes.
+  No real functionality.
+
+@copyright
+  INTEL CONFIDENTIAL
+  Copyright 2019 Intel Corporation.
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+
+  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+  the terms of your license agreement with Intel or your vendor. This file may
+  be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+
+#include <Base.h>
+
+/**
+  Do nothing function.
+
+**/
+VOID
+FspPcdListLibNull (
+  VOID
+  )
+{
+  return;
+}
--- a/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf
+++ b/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf
@@ -0,0 +1,85 @@
+## @file
+# Library instance to list all DynamicEx PCD FSP consumes.
+#
+# @copyright
+#  INTEL CONFIDENTIAL
+#  Copyright 2019 - 2021 Intel Corporation.
+#
+#  The source code contained or described herein and all documents related to the
+#  source code ("Material") are owned by Intel Corporation or its suppliers or
+#  licensors. Title to the Material remains with Intel Corporation or its suppliers
+#  and licensors. The Material may contain trade secrets and proprietary and
+#  confidential information of Intel Corporation and its suppliers and licensors,
+#  and is protected by worldwide copyright and trade secret laws and treaty
+#  provisions. No part of the Material may be used, copied, reproduced, modified,
+#  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+#  without Intel's prior express written permission.
+#
+#  No license under any patent, copyright, trade secret or other intellectual
+#  property right is granted to or conferred upon you by disclosure or delivery
+#  of the Materials, either expressly, by implication, inducement, estoppel or
+#  otherwise. Any license under such intellectual property rights must be
+#  express and approved by Intel in writing.
+#
+#  Unless otherwise agreed by Intel in writing, you may not remove or alter
+#  this notice or any other notice embedded in Materials by Intel or
+#  Intel's suppliers or licensors in any way.
+#
+#  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+#  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+#  the terms of your license agreement with Intel or your vendor. This file may
+#  be modified by the user, subject to additional terms of the license agreement.
+#
+# @par Specification Reference:
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = FspPcdListLibNull
+  FILE_GUID                      = C5D4D79E-3D5C-4EB6-899E-6F1563CB0B32
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = NULL
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  ClientOneSiliconPkg/SiPkg.dec
+
+[Sources]
+  FspPcdListLibNull.c
+
+[Pcd]
+  #
+  # List all the DynamicEx PCDs that FSP will consume.
+  # FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are
+  # built into PCD database.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr     ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr  ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                            ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber             ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress                       ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength                        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress                 ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize              ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode                            ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate                        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled                           ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable                        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress                         ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting                       ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize                      ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme                 ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability                    ## CONSUMES
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.bin
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.bin
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.json
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.json
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.bin
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.bin
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.json
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.json
--- a/models/addw3/IntelGopDriver.efi
+++ b/models/addw3/IntelGopDriver.efi
--- a/models/addw3/IntelGopDriver.inf
+++ b/models/addw3/IntelGopDriver.inf
@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IntelGopDriver
+  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.X64]
+  PE32|IntelGopDriver.efi|*
--- a/models/addw3/README.md
+++ b/models/addw3/README.md
@@ -0,0 +1,12 @@
+# System76 Adder WS (addw3)
+
+## Contents
+
+- [EC](./ec.rom)
+  - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+  - Size: 4 KB
+  - HAP: false
+- [ME](./me.rom)
+  - Size: 3944 KB
+  - Version: 16.1.25.2091
--- a/models/addw3/README.md.in
+++ b/models/addw3/README.md.in
@@ -0,0 +1 @@
+# System76 Adder WS (addw3)
--- a/models/addw3/chip.txt
+++ b/models/addw3/chip.txt
@@ -0,0 +1 @@
+GD25Q256D
--- a/models/addw3/coreboot-collector.txt
+++ b/models/addw3/coreboot-collector.txt
@@ -0,0 +1,333 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
+PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
+PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
+PCI Device: 0000:00:1b.0: Class 0x00060400, Vendor 0x8086, Device 0x7A44, Revision 0x11
+PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3C, Revision 0x11
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
+PCI Device: 0000:00:1f.3: Class 0x00040100, Vendor 0x8086, Device 0x7A50, Revision 0x11
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
+PCI Device: 0000:00:1f.6: Class 0x00020000, Vendor 0x8086, Device 0x0DC8, Revision 0x11
+PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2820, Revision 0xA1
+PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BD, Revision 0xA1
+PCI Device: 0000:02:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:01.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:02.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:03.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:04:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x1134, Revision 0x00
+PCI Device: 0000:39:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x1135, Revision 0x00
+PCI Device: 0000:6c:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
+PCI Device: 10000:e0:1d.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 10000:e0:1d.4: Class 0x00060400, Vendor 0x8086, Device 0x7A34, Revision 0x11
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
+## GPIO ##
+600 Series PCH
+GPP_I0 (0x6E,0x00) 0x44000100 0x00000018 0x00000000 0x00000000
+GPP_I1 (0x6E,0x02) 0x44000500 0x00000019 0x00000000 0x00000000
+GPP_I2 (0x6E,0x04) 0x86800100 0x0000001a 0x00000000 0x00000000
+GPP_I3 (0x6E,0x06) 0x44000500 0x0000001b 0x00000000 0x00000000
+GPP_I4 (0x6E,0x08) 0x86800100 0x0000001c 0x00000000 0x00000000
+GPP_I5 (0x6E,0x0A) 0x84000201 0x0000001d 0x00000000 0x00000000
+GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
+GPP_I7 (0x6E,0x0E) 0x44000300 0x00000020 0x00000000 0x00000000
+GPP_I8 (0x6E,0x10) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_I9 (0x6E,0x12) 0x44000300 0x00000022 0x00000000 0x00000000
+GPP_I10 (0x6E,0x14) 0x44000300 0x00000023 0x00000000 0x00000000
+GPP_I11 (0x6E,0x16) 0x84000402 0x00000024 0x00000000 0x00000000
+GPP_I12 (0x6E,0x18) 0x84000402 0x00000025 0x00000000 0x00000000
+GPP_I13 (0x6E,0x1A) 0x84000402 0x00000026 0x00000000 0x00000000
+GPP_I14 (0x6E,0x1C) 0x84000402 0x00000027 0x00000000 0x00000000
+GPP_I15 (0x6E,0x1E) 0x44000300 0x00000028 0x00000000 0x00000000
+GPP_I16 (0x6E,0x20) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_I17 (0x6E,0x22) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_I18 (0x6E,0x24) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_I19 (0x6E,0x26) 0x44000300 0x0000002c 0x00000000 0x00000000
+GPP_I20 (0x6E,0x28) 0x44000300 0x0000002d 0x00000000 0x00000000
+GPP_I21 (0x6E,0x2A) 0x44000300 0x0000002e 0x00000000 0x00000000
+GPP_I22 (0x6E,0x2C) 0x44000200 0x00000030 0x00000000 0x00000000
+GPP_R0 (0x6E,0x32) 0x44000600 0x00000031 0x00000000 0x00000000
+GPP_R1 (0x6E,0x34) 0x44000600 0x00003c32 0x00000000 0x00000000
+GPP_R2 (0x6E,0x36) 0x44000600 0x00003c33 0x00000000 0x00000000
+GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
+GPP_R4 (0x6E,0x3A) 0x44000600 0x00000035 0x00000000 0x00000000
+GPP_R5 (0x6E,0x3C) 0x44000300 0x00000036 0x00000000 0x00000000
+GPP_R6 (0x6E,0x3E) 0x44000300 0x00000037 0x00000000 0x00000000
+GPP_R7 (0x6E,0x40) 0x44000300 0x00000038 0x00000000 0x00000000
+GPP_R8 (0x6E,0x42) 0x84000102 0x00000039 0x00000000 0x00000000
+GPP_R9 (0x6E,0x44) 0x44000502 0x0000003a 0x00000000 0x00000000
+GPP_R10 (0x6E,0x46) 0x44000300 0x0000003b 0x00000000 0x00000000
+GPP_R11 (0x6E,0x48) 0x44000300 0x0000003c 0x00000000 0x00000000
+GPP_R12 (0x6E,0x4A) 0x44000300 0x0000003d 0x00000000 0x00000000
+GPP_R13 (0x6E,0x4C) 0x44000300 0x0000003e 0x00000000 0x00000000
+GPP_R14 (0x6E,0x4E) 0x44000300 0x0000003f 0x00000000 0x00000000
+GPP_R15 (0x6E,0x50) 0x44000300 0x00000040 0x00000000 0x00000000
+GPP_R16 (0x6E,0x52) 0x44000201 0x00000041 0x00000000 0x00000000
+GPP_R17 (0x6E,0x54) 0x44000300 0x00000042 0x00000000 0x00000000
+GPP_R18 (0x6E,0x56) 0x44000300 0x00000043 0x00000000 0x00000000
+GPP_R19 (0x6E,0x58) 0x44000300 0x00000044 0x00000000 0x00000000
+GPP_R20 (0x6E,0x5A) 0x44000300 0x00000045 0x00000000 0x00000000
+GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
+GPP_J0 (0x6E,0x60) 0x44000502 0x00000047 0x00000000 0x00000000
+GPP_J1 (0x6E,0x62) 0x84000600 0x00000048 0x00000000 0x00000000
+GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
+GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
+GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
+GPP_J5 (0x6E,0x6A) 0x44000502 0x0000304c 0x00000000 0x00000000
+GPP_J6 (0x6E,0x6C) 0x44000502 0x0000004d 0x00000000 0x00000000
+GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
+GPP_J8 (0x6E,0x70) 0x44000300 0x00000050 0x00000000 0x00000000
+GPP_J9 (0x6E,0x72) 0x44000300 0x00000051 0x00000000 0x00000000
+GPP_J10 (0x6E,0x74) 0x44000700 0x00001052 0x00000000 0x00000000
+GPP_J11 (0x6E,0x76) 0x44000700 0x00001053 0x00000000 0x00000000
+GPP_B0 (0x6D,0x00) 0x40100102 0x00000050 0x00000000 0x00000000
+GPP_B1 (0x6D,0x02) 0x44000300 0x00000051 0x00000000 0x00000000
+GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
+GPP_B3 (0x6D,0x06) 0x44000201 0x00000053 0x00000000 0x00000000
+GPP_B4 (0x6D,0x08) 0x44000300 0x00000054 0x00000000 0x00000000
+GPP_B5 (0x6D,0x0A) 0x44000300 0x00000055 0x00000000 0x00000000
+GPP_B6 (0x6D,0x0C) 0x44000300 0x00000056 0x00000000 0x00000000
+GPP_B7 (0x6D,0x0E) 0x44000300 0x00000057 0x00000000 0x00000000
+GPP_B8 (0x6D,0x10) 0x44000300 0x00000058 0x00000000 0x00000000
+GPP_B9 (0x6D,0x12) 0x44000300 0x00000059 0x00000000 0x00000000
+GPP_B10 (0x6D,0x14) 0x44000300 0x0000005a 0x00000000 0x00000000
+GPP_B11 (0x6D,0x16) 0x44000300 0x0000005b 0x00000000 0x00000000
+GPP_B12 (0x6D,0x18) 0x44000600 0x0000005c 0x00000000 0x00000000
+GPP_B13 (0x6D,0x1A) 0x44000600 0x0000005d 0x00000000 0x00000000
+GPP_B14 (0x6D,0x1C) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_B15 (0x6D,0x1E) 0x44000102 0x0000005f 0x00000000 0x00000000
+GPP_B16 (0x6D,0x20) 0x44000300 0x00000060 0x00000000 0x00000000
+GPP_B17 (0x6D,0x22) 0x44000300 0x00000061 0x00000000 0x00000000
+GPP_B18 (0x6D,0x24) 0x04000602 0x00000062 0x00000000 0x00000000
+GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
+GPP_B20 (0x6D,0x28) 0x44000700 0x00001064 0x00000000 0x00000000
+GPP_B21 (0x6D,0x2A) 0x42880102 0x00000065 0x00000000 0x00000000
+GPP_B22 (0x6D,0x2C) 0x44000201 0x00000066 0x00000000 0x00000000
+GPP_B23 (0x6D,0x2E) 0x44000200 0x00000067 0x00000800 0x00000000
+GPP_G0 (0x6D,0x30) 0x44000100 0x00000068 0x00000000 0x00000000
+GPP_G1 (0x6D,0x32) 0x44000102 0x00000069 0x00000000 0x00000000
+GPP_G2 (0x6D,0x34) 0x44000700 0x0000106a 0x00000000 0x00000000
+GPP_G3 (0x6D,0x36) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_G4 (0x6D,0x38) 0x44000102 0x0000006c 0x00000000 0x00000000
+GPP_G5 (0x6D,0x3A) 0x44000600 0x0000006d 0x00000000 0x00000000
+GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
+GPP_G7 (0x6D,0x3E) 0x44000100 0x0000006f 0x00000000 0x00000000
+GPP_H0 (0x6D,0x40) 0x44000300 0x00000070 0x00000000 0x00000000
+GPP_H1 (0x6D,0x42) 0x44000102 0x00000071 0x00000000 0x00000000
+GPP_H2 (0x6D,0x44) 0x44000702 0x00000072 0x00000000 0x00000000
+GPP_H3 (0x6D,0x46) 0x44000300 0x00000073 0x00000000 0x00000000
+GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
+GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
+GPP_H6 (0x6D,0x4C) 0x44000702 0x00000076 0x00000000 0x00000000
+GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
+GPP_H8 (0x6D,0x50) 0x44000700 0x00000018 0x00000000 0x00000000
+GPP_H9 (0x6D,0x52) 0x44000700 0x00000019 0x00000000 0x00000000
+GPP_H10 (0x6D,0x54) 0x84000402 0x00000020 0x00000000 0x00000000
+GPP_H11 (0x6D,0x56) 0x84000402 0x00000021 0x00000000 0x00000000
+GPP_H12 (0x6D,0x58) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_H13 (0x6D,0x5A) 0x84000402 0x00000023 0x00000000 0x00000000
+GPP_H14 (0x6D,0x5C) 0x84000402 0x00000024 0x00000000 0x00000000
+GPP_H15 (0x6D,0x5E) 0x84000402 0x00000025 0x00000800 0x00000000
+GPP_H16 (0x6D,0x60) 0x84000402 0x00000026 0x00000000 0x00000000
+GPP_H17 (0x6D,0x62) 0x84000201 0x00000027 0x00000000 0x00000000
+GPP_H18 (0x6D,0x64) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_H19 (0x6D,0x66) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_H20 (0x6D,0x68) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_H21 (0x6D,0x6A) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_H23 (0x6D,0x6E) 0x44000300 0x0000002d 0x00000000 0x00000000
+GPD0 (0x6C,0x00) 0x04000502 0x00003060 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000502 0x00003c61 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x04000702 0x00000062 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000502 0x00003063 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000200 0x00000067 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000600 0x00000068 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000600 0x00000069 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x04000600 0x0000006b 0x00000000 0x00000000
+GPD12 (0x6C,0x18) 0x04000300 0x0000006c 0x00000000 0x00000000
+GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
+GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
+GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
+GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
+GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
+GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
+GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
+GPP_A7 (0x6B,0x20) 0x44000700 0x00003025 0x00000000 0x00000000
+GPP_A8 (0x6B,0x22) 0x44000700 0x00003026 0x00000000 0x00000000
+GPP_A9 (0x6B,0x24) 0x44000700 0x00003027 0x00000000 0x00000000
+GPP_A10 (0x6B,0x26) 0x44000702 0x00003028 0x00000000 0x00000000
+GPP_A11 (0x6B,0x28) 0x44000702 0x00003029 0x00000000 0x00000000
+GPP_A12 (0x6B,0x2A) 0x44000702 0x0000302a 0x00000000 0x00000000
+GPP_A13 (0x6B,0x2C) 0x44000702 0x0000302b 0x00000000 0x00000000
+GPP_A14 (0x6B,0x2E) 0x44000300 0x0000002c 0x00000000 0x00000000
+GPP_C0 (0x6B,0x32) 0x44000402 0x0000002d 0x00000000 0x00000000
+GPP_C1 (0x6B,0x34) 0x44000402 0x0000002e 0x00000000 0x00000000
+GPP_C2 (0x6B,0x36) 0x44000200 0x0000002f 0x00000800 0x00000000
+GPP_C3 (0x6B,0x38) 0x44000c02 0x00000030 0x00000000 0x00000000
+GPP_C4 (0x6B,0x3A) 0x44000c02 0x00000031 0x00000000 0x00000000
+GPP_C5 (0x6B,0x3C) 0x44000200 0x00000032 0x00000000 0x00000000
+GPP_C6 (0x6B,0x3E) 0x44000802 0x00000033 0x00000000 0x00000000
+GPP_C7 (0x6B,0x40) 0x44000802 0x00000034 0x00000000 0x00000000
+GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
+GPP_C9 (0x6B,0x44) 0x44000300 0x00000036 0x00000000 0x00000000
+GPP_C10 (0x6B,0x46) 0x44000201 0x00000037 0x00000000 0x00000000
+GPP_C11 (0x6B,0x48) 0x44000201 0x00000038 0x00000000 0x00000000
+GPP_C12 (0x6B,0x4A) 0x44000300 0x00000039 0x00000000 0x00000000
+GPP_C13 (0x6B,0x4C) 0x44000300 0x0000003a 0x00000000 0x00000000
+GPP_C14 (0x6B,0x4E) 0x44000300 0x0000003b 0x00000000 0x00000000
+GPP_C15 (0x6B,0x50) 0x44000300 0x0000003c 0x00000000 0x00000000
+GPP_C16 (0x6B,0x52) 0x44000402 0x0000003d 0x00000000 0x00000000
+GPP_C17 (0x6B,0x54) 0x44000402 0x0000003e 0x00000000 0x00000000
+GPP_C18 (0x6B,0x56) 0x44000402 0x0000003f 0x00000000 0x00000000
+GPP_C19 (0x6B,0x58) 0x44000402 0x00000040 0x00000000 0x00000000
+GPP_C20 (0x6B,0x5A) 0x44000300 0x00000041 0x00000000 0x00000000
+GPP_C21 (0x6B,0x5C) 0x44000300 0x00000042 0x00000000 0x00000000
+GPP_C22 (0x6B,0x5E) 0x44000300 0x00000043 0x00000000 0x00000000
+GPP_C23 (0x6B,0x60) 0x44000300 0x00000044 0x00000000 0x00000000
+GPP_S0 (0x6A,0x00) 0x44000300 0x01800030 0x00000000 0x00000000
+GPP_S1 (0x6A,0x02) 0x44000300 0x01800031 0x00000000 0x00000000
+GPP_S2 (0x6A,0x04) 0x44000300 0x01800032 0x00000000 0x00000000
+GPP_S3 (0x6A,0x06) 0x44000300 0x01800033 0x00000000 0x00000000
+GPP_S4 (0x6A,0x08) 0x44000300 0x01800034 0x00000000 0x00000000
+GPP_S5 (0x6A,0x0A) 0x44000300 0x01800035 0x00000000 0x00000000
+GPP_S6 (0x6A,0x0C) 0x44000a00 0x01800036 0x00000000 0x00000000
+GPP_S7 (0x6A,0x0E) 0x44000900 0x01800037 0x00000000 0x00000000
+GPP_E0 (0x6A,0x10) 0x44000300 0x00000038 0x00000000 0x00000000
+GPP_E1 (0x6A,0x12) 0x44000300 0x00000039 0x00000000 0x00000000
+GPP_E2 (0x6A,0x14) 0x44000300 0x0000003a 0x00000000 0x00000000
+GPP_E3 (0x6A,0x16) 0x42840103 0x0000003b 0x00000000 0x00000000
+GPP_E4 (0x6A,0x18) 0x44000300 0x0000003c 0x00000000 0x00000000
+GPP_E5 (0x6A,0x1A) 0x44000300 0x0000003d 0x00000000 0x00000000
+GPP_E6 (0x6A,0x1C) 0x44000300 0x0000003e 0x00000000 0x00000000
+GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
+GPP_E8 (0x6A,0x20) 0x44000600 0x00000040 0x00000000 0x00000000
+GPP_E9 (0x6A,0x22) 0x44000602 0x00000041 0x00000800 0x00000000
+GPP_E10 (0x6A,0x24) 0x44000602 0x00000042 0x00000800 0x00000000
+GPP_E11 (0x6A,0x26) 0x44000602 0x00000043 0x00000800 0x00000000
+GPP_E12 (0x6A,0x28) 0x44000602 0x00000044 0x00000000 0x00000000
+GPP_E13 (0x6A,0x2A) 0x44000300 0x00000045 0x00000000 0x00000000
+GPP_E14 (0x6A,0x2C) 0x44000300 0x00000046 0x00000000 0x00000000
+GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
+GPP_E16 (0x6A,0x30) 0x44000300 0x00000048 0x00000000 0x00000000
+GPP_E17 (0x6A,0x32) 0x44000102 0x00001049 0x00000000 0x00000000
+GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
+GPP_E19 (0x6A,0x36) 0x44000300 0x0000004b 0x00000000 0x00000000
+GPP_E20 (0x6A,0x38) 0x44000300 0x0000004c 0x00000000 0x00000000
+GPP_E21 (0x6A,0x3A) 0x44000300 0x0000004d 0x00000000 0x00000000
+GPP_K0 (0x6A,0x3E) 0x42800102 0x0000004e 0x00000000 0x00000000
+GPP_K1 (0x6A,0x40) 0x44000300 0x00000050 0x00000000 0x00000000
+GPP_K2 (0x6A,0x42) 0x44000300 0x00000051 0x00000000 0x00000000
+GPP_K3 (0x6A,0x44) 0x84000201 0x00000052 0x00000000 0x00000000
+GPP_K4 (0x6A,0x46) 0x04000200 0x00000053 0x00000000 0x00000000
+GPP_K5 (0x6A,0x48) 0x44000300 0x00000054 0x00000000 0x00000000
+GPP_K6 (0x6A,0x4A) 0x44000b02 0x00003055 0x00000000 0x00000000
+GPP_K7 (0x6A,0x4C) 0x44000b00 0x00001056 0x00000000 0x00000000
+GPP_K8 (0x6A,0x4E) 0x44000600 0x00000057 0x00000000 0x00000000
+GPP_K9 (0x6A,0x50) 0x44000600 0x00000058 0x00000000 0x00000000
+GPP_K10 (0x6A,0x52) 0x44000b02 0x00003059 0x00000000 0x00000000
+GPP_K11 (0x6A,0x54) 0x44000300 0x0000005a 0x00000000 0x00000000
+GPP_F0 (0x6A,0x5C) 0x44000a02 0x0000005b 0x00000000 0x00000000
+GPP_F1 (0x6A,0x5E) 0x44000300 0x0000005c 0x00000000 0x00000000
+GPP_F2 (0x6A,0x60) 0x84000201 0x0000005d 0x00000000 0x00000000
+GPP_F3 (0x6A,0x62) 0x84000201 0x0000005e 0x00000000 0x00000000
+GPP_F4 (0x6A,0x64) 0x84000201 0x00000060 0x00000000 0x00000000
+GPP_F5 (0x6A,0x66) 0x44000600 0x00000061 0x00000000 0x00000000
+GPP_F6 (0x6A,0x68) 0x44000300 0x00000062 0x00000000 0x00000000
+GPP_F7 (0x6A,0x6A) 0x84000102 0x00000063 0x00000000 0x00000000
+GPP_F8 (0x6A,0x6C) 0x44000100 0x00000064 0x00000000 0x00000000
+GPP_F9 (0x6A,0x6E) 0x44000201 0x00000065 0x00000000 0x00000000
+GPP_F10 (0x6A,0x70) 0x44000300 0x00000066 0x00000000 0x00000000
+GPP_F11 (0x6A,0x72) 0x44000300 0x00000067 0x00000000 0x00000000
+GPP_F12 (0x6A,0x74) 0x44000300 0x00000068 0x00000000 0x00000000
+GPP_F13 (0x6A,0x76) 0x44000300 0x00000069 0x00000000 0x00000000
+GPP_F14 (0x6A,0x78) 0x44000700 0x0000006a 0x00000000 0x00000000
+GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_F16 (0x6A,0x7C) 0x44000300 0x0000006c 0x00000000 0x00000000
+GPP_F17 (0x6A,0x7E) 0x44000102 0x0000006d 0x00000000 0x00000000
+GPP_F18 (0x6A,0x80) 0x84000200 0x0000006e 0x00000000 0x00000000
+GPP_F19 (0x6A,0x82) 0x44000600 0x0000006f 0x00000000 0x00000000
+GPP_F20 (0x6A,0x84) 0x44000600 0x00000070 0x00000000 0x00000000
+GPP_F21 (0x6A,0x86) 0x44000600 0x00000071 0x00000000 0x00000000
+GPP_F22 (0x6A,0x88) 0x44000300 0x00000072 0x00000000 0x00000000
+GPP_F23 (0x6A,0x8A) 0x44000300 0x00000073 0x00000000 0x00000000
+GPP_D0 (0x69,0x20) 0x44000300 0x00000026 0x00000000 0x00000000
+GPP_D1 (0x69,0x22) 0x44000300 0x00000027 0x00000000 0x00000000
+GPP_D2 (0x69,0x24) 0x44000300 0x00000028 0x00000000 0x00000000
+GPP_D3 (0x69,0x26) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_D4 (0x69,0x28) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_D5 (0x69,0x2A) 0x44000300 0x0000002b 0x00000000 0x00000000
+GPP_D6 (0x69,0x2C) 0x44000300 0x0000002c 0x00000000 0x00000000
+GPP_D7 (0x69,0x2E) 0x44000300 0x0000002d 0x00000000 0x00000000
+GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
+GPP_D9 (0x69,0x32) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D10 (0x69,0x34) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D13 (0x69,0x3A) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D14 (0x69,0x3C) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
+GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D22 (0x69,0x4C) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+  vendor_name: Realtek
+  chip_name: ALC256
+  vendor_id: 0x10ec0256
+  subsystem_id: 0x1558a671
+  revision_id: 0x100002
+  0x12: 0x90a60130
+  0x13: 0x40000000
+  0x14: 0x90170110
+  0x18: 0x411111f0
+  0x19: 0x411111f0
+  0x1a: 0x411111f0
+  0x1b: 0x02a11040
+  0x1d: 0x41700001
+  0x1e: 0x411111f0
+  0x21: 0x02211020
+hdaudioC0D2
+  vendor_name: Intel
+  chip_name: Raptorlake HDMI
+  vendor_id: 0x80862818
+  subsystem_id: 0x80860101
+  revision_id: 0x100000
+  0x04: 0x18560010
+  0x06: 0x18560010
+  0x08: 0x18560010
+  0x0a: 0x18560010
+  0x0b: 0x18560010
+  0x0c: 0x18560010
+  0x0d: 0x18560010
+  0x0e: 0x18560010
+  0x0f: 0x18560010
+hdaudioC1D0
+  vendor_name: Nvidia
+  chip_name: Generic HDMI
+  vendor_id: 0x10de00a6
+  subsystem_id: 0x10de0000
+  revision_id: 0x100100
+  0x04: 0x185600f0
+  0x05: 0x585600f0
+  0x06: 0x185600f0
+  0x07: 0x585600f0
--- a/models/addw3/coreboot.config
+++ b/models/addw3/coreboot.config
@@ -0,0 +1,28 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_ADDW3=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+CONFIG_HAVE_GBE_BIN=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_GBE_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/gbe.rom"
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
+CONFIG_POST_IO=n
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_V2=y
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
+
+# Custom FSP
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Fsp.fd"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Include"
+CONFIG_FSP_USE_REPO=n
--- a/models/addw3/ec.config
+++ b/models/addw3/ec.config
@@ -0,0 +1 @@
+BOARD=system76/addw3
--- a/models/addw3/ecspy.txt
+++ b/models/addw3/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 6
+A0: data 1 mirror 1 pot 0 control 00
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 0 mirror 1 pot 0 control 00
+A3: data 1 mirror 1 pot 0 control 80
+A4: data 0 mirror 0 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 0 mirror 1 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 80
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 1 mirror 1 pot 0 control 40
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 40
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 44
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 1 mirror 1 pot 0 control 44
+D4: data 1 mirror 1 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 1 mirror 1 pot 0 control 02
+D7: data 0 mirror 0 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 0 mirror 0 pot 0 control 84
+E3: data 1 mirror 1 pot 0 control 40
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 1 mirror 1 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 40
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 0 mirror 0 pot 0 control 00
+F7: data 0 mirror 0 pot 0 control 80
+G0: data 0 mirror 0 pot 0 control 80
+G1: data 1 mirror 1 pot 0 control 80
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 0 mirror 0 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 0 mirror 0 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 0 mirror 0 pot 0 control 40
+H4: data 1 mirror 1 pot 0 control 80
+H5: data 0 mirror 0 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 80
+H7: data 1 mirror 1 pot 0 control 80
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 00
+I3: data 0 mirror 0 pot 0 control 00
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 1 mirror 1 pot 0 control 80
+I6: data 1 mirror 1 pot 0 control 80
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 1 mirror 1 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 40
+J5: data 0 mirror 0 pot 0 control 40
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 1 mirror 1 pot 0 control 80
+M0: data 0 mirror 0 control 06
+M1: data 1 mirror 0 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 1 control 06
+M5: data 0 mirror 0 control 00
+M6: data 1 mirror 1 control 86
+M7: data 0 mirror 0 control 00
--- a/models/addw3/edk2.config
+++ b/models/addw3/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/addw3/fd.rom
+++ b/models/addw3/fd.rom
--- a/models/addw3/gbe.rom
+++ b/models/addw3/gbe.rom
--- a/models/addw3/gpio.h
+++ b/models/addw3/gpio.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A7, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A13, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A14, NONE),
+	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
+	PAD_NC(GPP_B1, NONE),
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 0, DEEP),
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000),
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+	PAD_NC(GPP_C9, NONE),
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	PAD_CFG_GPO(GPP_C11, 1, DEEP),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	_PAD_CFG_STRUCT(GPP_E3, 0x42840101, 0x0000),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	PAD_NC(GPP_E13, NONE),
+	PAD_NC(GPP_E14, NONE),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, DN_20K, DEEP),
+	PAD_CFG_GPO(GPP_E18, 1, DEEP),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+	PAD_NC(GPP_F1, NONE),
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F3, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F4, 1, PLTRST),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPI(GPP_F7, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, PLTRST),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+	PAD_CFG_NF(GPP_G2, DN_20K, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPI(GPP_H1, NONE, DEEP),
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	PAD_CFG_NF(GPP_H13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H14, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H18, 0, DEEP),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	PAD_CFG_GPO(GPP_H22, 0, DEEP),
+	PAD_NC(GPP_H23, NONE),
+	PAD_CFG_GPI(GPP_I0, NONE, DEEP),
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I2, 0x86800100, 0x0000),
+	PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I4, 0x86800100, 0x0000),
+	PAD_CFG_GPO(GPP_I5, 1, PLTRST),
+	PAD_CFG_GPO(GPP_I6, 0, DEEP),
+	PAD_NC(GPP_I7, NONE),
+	PAD_CFG_GPO(GPP_I8, 0, DEEP),
+	PAD_NC(GPP_I9, NONE),
+	PAD_NC(GPP_I10, NONE),
+	PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
+	PAD_NC(GPP_I15, NONE),
+	PAD_NC(GPP_I16, NONE),
+	PAD_NC(GPP_I17, NONE),
+	PAD_CFG_GPO(GPP_I18, 0, DEEP),
+	PAD_NC(GPP_I19, NONE),
+	PAD_NC(GPP_I20, NONE),
+	PAD_NC(GPP_I21, NONE),
+	PAD_CFG_GPO(GPP_I22, 0, DEEP),
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+	PAD_NC(GPP_J8, NONE),
+	PAD_NC(GPP_J9, NONE),
+	PAD_CFG_NF(GPP_J10, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000),
+	PAD_NC(GPP_K1, NONE),
+	PAD_NC(GPP_K2, NONE),
+	PAD_CFG_GPO(GPP_K3, 1, PLTRST),
+	PAD_CFG_GPO(GPP_K4, 0, PWROK),
+	PAD_NC(GPP_K5, NONE),
+	PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
+	PAD_NC(GPP_K11, NONE),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+	PAD_CFG_GPI(GPP_R8, NONE, PLTRST),
+	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
+	PAD_NC(GPP_R10, NONE),
+	PAD_NC(GPP_R11, NONE),
+	PAD_NC(GPP_R12, NONE),
+	PAD_NC(GPP_R13, NONE),
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
+	PAD_CFG_GPO(GPP_R16, 1, DEEP),
+	PAD_NC(GPP_R17, NONE),
+	PAD_NC(GPP_R18, NONE),
+	PAD_NC(GPP_R19, NONE),
+	PAD_NC(GPP_R20, NONE),
+	PAD_CFG_GPO(GPP_R21, 0, DEEP),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+};
+
+#endif
+
+#endif
--- a/models/addw3/hda_verb.c
+++ b/models/addw3/hda_verb.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x1558a671, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558a671),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+	/* Intel, RaptorlakeHDMI */
+	0x80862818, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+	/* Nvidia, GenericHDMI */
+	0x10de00a6, /* Vendor ID */
+	0x10de0000, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x10de0000),
+	AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x585600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/models/addw3/me.rom
+++ b/models/addw3/me.rom
--- a/models/addw3/vbt.rom
+++ b/models/addw3/vbt.rom
--- a/models/bonw14/edk2.config
+++ b/models/bonw14/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/bonw15/AlderLakeFspBinPkg
+++ b/models/bonw15/AlderLakeFspBinPkg
@@ -0,0 +1 @@
+../addw3/AlderLakeFspBinPkg
--- a/models/bonw15/IntelGopDriver.efi
+++ b/models/bonw15/IntelGopDriver.efi
--- a/models/bonw15/IntelGopDriver.inf
+++ b/models/bonw15/IntelGopDriver.inf
@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IntelGopDriver
+  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.X64]
+  PE32|IntelGopDriver.efi|*
--- a/models/bonw15/README.md
+++ b/models/bonw15/README.md
@@ -0,0 +1,12 @@
+# System76 Bonobo WS (bonw15)
+
+## Contents
+
+- [EC](./ec.rom)
+  - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+  - Size: 4 KB
+  - HAP: false
+- [ME](./me.rom)
+  - Size: 3944 KB
+  - Version: 16.1.25.2091
--- a/models/bonw15/README.md.in
+++ b/models/bonw15/README.md.in
@@ -0,0 +1 @@
+# System76 Bonobo WS (bonw15)
--- a/models/bonw15/chip.txt
+++ b/models/bonw15/chip.txt
@@ -0,0 +1 @@
+GD25Q256D
--- a/models/bonw15/coreboot-collector.txt
+++ b/models/bonw15/coreboot-collector.txt
@@ -0,0 +1,334 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
+PCI Device: 0000:00:01.1: Class 0x00060400, Vendor 0x8086, Device 0xA72D, Revision 0x01
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
+PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
+PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
+PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3E, Revision 0x11
+PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x7A30, Revision 0x11
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
+PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x7A50, Revision 0x11
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
+PCI Device: 0000:02:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x27E0, Revision 0xA1
+PCI Device: 0000:02:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BC, Revision 0xA1
+PCI Device: 0000:03:00.0: Class 0x00020000, Vendor 0x8086, Device 0x3101, Revision 0x03
+PCI Device: 0000:04:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:01.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:02.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:03.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:06:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x1137, Revision 0x00
+PCI Device: 0000:3a:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x1138, Revision 0x00
+PCI Device: 10000:e0:1b.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 10000:e0:1b.4: Class 0x00060400, Vendor 0x8086, Device 0x7A44, Revision 0x11
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
+## GPIO ##
+600 Series PCH
+GPP_I0 (0x6E,0x00) 0x44000200 0x00000018 0x00000000 0x00000000
+GPP_I1 (0x6E,0x02) 0x86880100 0x00000019 0x00000000 0x00000000
+GPP_I2 (0x6E,0x04) 0x86880100 0x0000001a 0x00000000 0x00000000
+GPP_I3 (0x6E,0x06) 0x86880100 0x0000001b 0x00000000 0x00000000
+GPP_I4 (0x6E,0x08) 0x86880100 0x0000001c 0x00000000 0x00000000
+GPP_I5 (0x6E,0x0A) 0x44000200 0x0000001d 0x00000000 0x00000000
+GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
+GPP_I7 (0x6E,0x0E) 0x44000200 0x00000020 0x00000000 0x00000000
+GPP_I8 (0x6E,0x10) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_I9 (0x6E,0x12) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_I10 (0x6E,0x14) 0x44000200 0x00000023 0x00000000 0x00000000
+GPP_I11 (0x6E,0x16) 0x44000300 0x00000024 0x00000000 0x00000000
+GPP_I12 (0x6E,0x18) 0x44000300 0x00000025 0x00000000 0x00000000
+GPP_I13 (0x6E,0x1A) 0x44000300 0x00000026 0x00000000 0x00000000
+GPP_I14 (0x6E,0x1C) 0x44000300 0x00000027 0x00000000 0x00000000
+GPP_I15 (0x6E,0x1E) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_I16 (0x6E,0x20) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_I17 (0x6E,0x22) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_I18 (0x6E,0x24) 0x44000102 0x0000002b 0x00000000 0x00000000
+GPP_I19 (0x6E,0x26) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_I20 (0x6E,0x28) 0x44000200 0x0000002d 0x00000000 0x00000000
+GPP_I21 (0x6E,0x2A) 0x44000200 0x0000002e 0x00000000 0x00000000
+GPP_I22 (0x6E,0x2C) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_R0 (0x6E,0x32) 0x44000500 0x00000031 0x00000000 0x00000000
+GPP_R1 (0x6E,0x34) 0x44000500 0x00003c32 0x00000000 0x00000000
+GPP_R2 (0x6E,0x36) 0x44000500 0x00003c33 0x00000000 0x00000000
+GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
+GPP_R4 (0x6E,0x3A) 0x44000500 0x00000035 0x00000000 0x00000000
+GPP_R5 (0x6E,0x3C) 0x44000200 0x00000036 0x00000000 0x00000000
+GPP_R6 (0x6E,0x3E) 0x44000200 0x00000037 0x00000000 0x00000000
+GPP_R7 (0x6E,0x40) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_R8 (0x6E,0x42) 0x44000102 0x00000039 0x00000000 0x00000000
+GPP_R9 (0x6E,0x44) 0x44000702 0x0000003a 0x00000000 0x00000000
+GPP_R10 (0x6E,0x46) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_R11 (0x6E,0x48) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_R12 (0x6E,0x4A) 0x44000200 0x0000003d 0x00000000 0x00000000
+GPP_R13 (0x6E,0x4C) 0x44000200 0x0000003e 0x00000000 0x00000000
+GPP_R14 (0x6E,0x4E) 0x44000200 0x0000003f 0x00000000 0x00000000
+GPP_R15 (0x6E,0x50) 0x44000200 0x00000040 0x00000000 0x00000000
+GPP_R16 (0x6E,0x52) 0x44000201 0x00000041 0x00000000 0x00000000
+GPP_R17 (0x6E,0x54) 0x44000200 0x00000042 0x00000000 0x00000000
+GPP_R18 (0x6E,0x56) 0x44000200 0x00000043 0x00000000 0x00000000
+GPP_R19 (0x6E,0x58) 0x44000200 0x00000044 0x00000000 0x00000000
+GPP_R20 (0x6E,0x5A) 0x44000200 0x00000045 0x00000000 0x00000000
+GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
+GPP_J0 (0x6E,0x60) 0x44000500 0x00000047 0x00000000 0x00000000
+GPP_J1 (0x6E,0x62) 0x44000700 0x00000048 0x00000000 0x00000000
+GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
+GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
+GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
+GPP_J5 (0x6E,0x6A) 0x44000500 0x0000304c 0x00000000 0x00000000
+GPP_J6 (0x6E,0x6C) 0x44000500 0x0000004d 0x00000000 0x00000000
+GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
+GPP_J8 (0x6E,0x70) 0x44000102 0x00000050 0x00000000 0x00000000
+GPP_J9 (0x6E,0x72) 0x44000200 0x00000051 0x00000000 0x00000000
+GPP_J10 (0x6E,0x74) 0x44000200 0x00000052 0x00000000 0x00000000
+GPP_J11 (0x6E,0x76) 0x44000200 0x00000053 0x00000000 0x00000000
+GPP_B0 (0x6D,0x00) 0x82900102 0x00000050 0x00000000 0x00000000
+GPP_B1 (0x6D,0x02) 0x44000200 0x00000051 0x00000000 0x00000000
+GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
+GPP_B3 (0x6D,0x06) 0x44000201 0x00000053 0x00000000 0x00000000
+GPP_B4 (0x6D,0x08) 0x44000200 0x00000054 0x00000000 0x00000000
+GPP_B5 (0x6D,0x0A) 0x44000200 0x00000055 0x00000000 0x00000000
+GPP_B6 (0x6D,0x0C) 0x44000200 0x00000056 0x00000000 0x00000000
+GPP_B7 (0x6D,0x0E) 0x44000200 0x00000057 0x00000000 0x00000000
+GPP_B8 (0x6D,0x10) 0x44000200 0x00000058 0x00000000 0x00000000
+GPP_B9 (0x6D,0x12) 0x44000200 0x00000059 0x00000000 0x00000000
+GPP_B10 (0x6D,0x14) 0x44000200 0x0000005a 0x00000000 0x00000000
+GPP_B11 (0x6D,0x16) 0x44000200 0x0000005b 0x00000000 0x00000000
+GPP_B12 (0x6D,0x18) 0x44000700 0x0000005c 0x00000000 0x00000000
+GPP_B13 (0x6D,0x1A) 0x44000700 0x0000005d 0x00000000 0x00000000
+GPP_B14 (0x6D,0x1C) 0x44000600 0x0000005e 0x00000000 0x00000000
+GPP_B15 (0x6D,0x1E) 0x44000200 0x0000005f 0x00000000 0x00000000
+GPP_B16 (0x6D,0x20) 0x44000200 0x00000060 0x00000000 0x00000000
+GPP_B17 (0x6D,0x22) 0x04000201 0x00000061 0x00000000 0x00000000
+GPP_B18 (0x6D,0x24) 0x04000702 0x00000062 0x00000000 0x00000000
+GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
+GPP_B20 (0x6D,0x28) 0x44000200 0x00000064 0x00000000 0x00000000
+GPP_B21 (0x6D,0x2A) 0x44000200 0x00000065 0x00000000 0x00000000
+GPP_B22 (0x6D,0x2C) 0x44000201 0x00000066 0x00000000 0x00000000
+GPP_B23 (0x6D,0x2E) 0x44000102 0x00000067 0x00000800 0x00000000
+GPP_G0 (0x6D,0x30) 0x04000200 0x00000068 0x00000000 0x00000000
+GPP_G1 (0x6D,0x32) 0x44000100 0x00000069 0x00000000 0x00000000
+GPP_G2 (0x6D,0x34) 0x44000100 0x0000106a 0x00000000 0x00000000
+GPP_G3 (0x6D,0x36) 0x44000102 0x0000006b 0x00000000 0x00000000
+GPP_G4 (0x6D,0x38) 0x44000100 0x0000006c 0x00000000 0x00000000
+GPP_G5 (0x6D,0x3A) 0x44000700 0x0000006d 0x00000000 0x00000000
+GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
+GPP_G7 (0x6D,0x3E) 0x42800102 0x0000006f 0x00000000 0x00000000
+GPP_H0 (0x6D,0x40) 0x44000102 0x00000070 0x00000000 0x00000000
+GPP_H1 (0x6D,0x42) 0x44000200 0x00000071 0x00000000 0x00000000
+GPP_H2 (0x6D,0x44) 0x44000100 0x00000072 0x00000000 0x00000000
+GPP_H3 (0x6D,0x46) 0x44000702 0x00000073 0x00000000 0x00000000
+GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
+GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
+GPP_H6 (0x6D,0x4C) 0x44000300 0x00000076 0x00000000 0x00000000
+GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
+GPP_H8 (0x6D,0x50) 0x44000700 0x00000018 0x00000000 0x00000000
+GPP_H9 (0x6D,0x52) 0x44000702 0x00000019 0x00000000 0x00000000
+GPP_H10 (0x6D,0x54) 0x44000502 0x00000020 0x00000000 0x00000000
+GPP_H11 (0x6D,0x56) 0x44000502 0x00000021 0x00000000 0x00000000
+GPP_H12 (0x6D,0x58) 0x44000102 0x00000022 0x00000000 0x00000000
+GPP_H13 (0x6D,0x5A) 0x44000502 0x00000023 0x00000000 0x00000000
+GPP_H14 (0x6D,0x5C) 0x44000500 0x00000024 0x00000000 0x00000000
+GPP_H15 (0x6D,0x5E) 0x44000102 0x00000025 0x00000800 0x00000000
+GPP_H16 (0x6D,0x60) 0x44000102 0x00000026 0x00000000 0x00000000
+GPP_H17 (0x6D,0x62) 0x44000201 0x00000027 0x00000000 0x00000000
+GPP_H18 (0x6D,0x64) 0x44000102 0x00000028 0x00000000 0x00000000
+GPP_H19 (0x6D,0x66) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_H20 (0x6D,0x68) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_H21 (0x6D,0x6A) 0x44000201 0x0000002b 0x00000000 0x00000000
+GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_H23 (0x6D,0x6E) 0x44000102 0x0000002d 0x00000000 0x00000000
+GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000702 0x00003c61 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x42880102 0x00000062 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000100 0x00000067 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000200 0x00000069 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x44000200 0x0000006b 0x00000000 0x00000000
+GPD12 (0x6C,0x18) 0x44000200 0x0000006c 0x00000000 0x00000000
+GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
+GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
+GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
+GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
+GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
+GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
+GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
+GPP_A7 (0x6B,0x20) 0x44000200 0x00000025 0x00000000 0x00000000
+GPP_A8 (0x6B,0x22) 0x44000200 0x00000026 0x00000000 0x00000000
+GPP_A9 (0x6B,0x24) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_A10 (0x6B,0x26) 0x44000500 0x00000028 0x00000000 0x00000000
+GPP_A11 (0x6B,0x28) 0x44000102 0x00003029 0x00000000 0x00000000
+GPP_A12 (0x6B,0x2A) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_A13 (0x6B,0x2C) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_A14 (0x6B,0x2E) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_C0 (0x6B,0x32) 0x44000502 0x0000002d 0x00000000 0x00000000
+GPP_C1 (0x6B,0x34) 0x44000502 0x0000002e 0x00000000 0x00000000
+GPP_C2 (0x6B,0x36) 0x84000102 0x0000002f 0x00000800 0x00000000
+GPP_C3 (0x6B,0x38) 0x44000200 0x00000030 0x00000000 0x00000000
+GPP_C4 (0x6B,0x3A) 0x44000200 0x00000031 0x00000000 0x00000000
+GPP_C5 (0x6B,0x3C) 0x44000502 0x00000032 0x00000000 0x00000000
+GPP_C6 (0x6B,0x3E) 0x44000200 0x00000033 0x00000000 0x00000000
+GPP_C7 (0x6B,0x40) 0x44000200 0x00000034 0x00000000 0x00000000
+GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
+GPP_C9 (0x6B,0x44) 0x44000200 0x00000036 0x00000000 0x00000000
+GPP_C10 (0x6B,0x46) 0x44000200 0x00000037 0x00000000 0x00000000
+GPP_C11 (0x6B,0x48) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_C12 (0x6B,0x4A) 0x44000200 0x00000039 0x00000000 0x00000000
+GPP_C13 (0x6B,0x4C) 0x44000200 0x0000003a 0x00000000 0x00000000
+GPP_C14 (0x6B,0x4E) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_C15 (0x6B,0x50) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_C16 (0x6B,0x52) 0x44000502 0x0000003d 0x00000000 0x00000000
+GPP_C17 (0x6B,0x54) 0x44000502 0x0000003e 0x00000000 0x00000000
+GPP_C18 (0x6B,0x56) 0x44000502 0x0000003f 0x00000000 0x00000000
+GPP_C19 (0x6B,0x58) 0x44000502 0x00000040 0x00000000 0x00000000
+GPP_C20 (0x6B,0x5A) 0x44000102 0x00000041 0x00000000 0x00000000
+GPP_C21 (0x6B,0x5C) 0x44000102 0x00000042 0x00000000 0x00000000
+GPP_C22 (0x6B,0x5E) 0x44000200 0x00000043 0x00000000 0x00000000
+GPP_C23 (0x6B,0x60) 0x44000200 0x00000044 0x00000000 0x00000000
+GPP_S0 (0x6A,0x00) 0x44000200 0x01800030 0x00000000 0x00000000
+GPP_S1 (0x6A,0x02) 0x44000200 0x01800031 0x00000000 0x00000000
+GPP_S2 (0x6A,0x04) 0x44000200 0x01800032 0x00000000 0x00000000
+GPP_S3 (0x6A,0x06) 0x44000200 0x01800033 0x00000000 0x00000000
+GPP_S4 (0x6A,0x08) 0x44000200 0x01800034 0x00000000 0x00000000
+GPP_S5 (0x6A,0x0A) 0x44000200 0x01800035 0x00000000 0x00000000
+GPP_S6 (0x6A,0x0C) 0x44000200 0x01800036 0x00000000 0x00000000
+GPP_S7 (0x6A,0x0E) 0x44000200 0x01800037 0x00000000 0x00000000
+GPP_E0 (0x6A,0x10) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_E1 (0x6A,0x12) 0x44000200 0x00000039 0x00000000 0x00000000
+GPP_E2 (0x6A,0x14) 0x44000200 0x0000003a 0x00000000 0x00000000
+GPP_E3 (0x6A,0x16) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_E4 (0x6A,0x18) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_E5 (0x6A,0x1A) 0x44000200 0x0000003d 0x00000000 0x00000000
+GPP_E6 (0x6A,0x1C) 0x44000200 0x0000003e 0x00000000 0x00000000
+GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
+GPP_E8 (0x6A,0x20) 0x44000500 0x00000040 0x00000000 0x00000000
+GPP_E9 (0x6A,0x22) 0x44000300 0x00000041 0x00000800 0x00000000
+GPP_E10 (0x6A,0x24) 0x44000300 0x00000042 0x00000800 0x00000000
+GPP_E11 (0x6A,0x26) 0x44000300 0x00000043 0x00000800 0x00000000
+GPP_E12 (0x6A,0x28) 0x44000300 0x00000044 0x00000000 0x00000000
+GPP_E13 (0x6A,0x2A) 0x44000200 0x00000045 0x00000000 0x00000000
+GPP_E14 (0x6A,0x2C) 0x44000200 0x00000046 0x00000000 0x00000000
+GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
+GPP_E16 (0x6A,0x30) 0x44000200 0x00000048 0x00000000 0x00000000
+GPP_E17 (0x6A,0x32) 0x44000200 0x00000049 0x00000000 0x00000000
+GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
+GPP_E19 (0x6A,0x36) 0x44000200 0x0000004b 0x00000000 0x00000000
+GPP_E20 (0x6A,0x38) 0x44000200 0x0000004c 0x00000000 0x00000000
+GPP_E21 (0x6A,0x3A) 0x44000200 0x0000004d 0x00000000 0x00000000
+GPP_K0 (0x6A,0x3E) 0x44000200 0x0000004e 0x00000000 0x00000000
+GPP_K1 (0x6A,0x40) 0x44000200 0x00000050 0x00000000 0x00000000
+GPP_K2 (0x6A,0x42) 0x44000200 0x00000051 0x00000000 0x00000000
+GPP_K3 (0x6A,0x44) 0x44000200 0x00000052 0x00000000 0x00000000
+GPP_K4 (0x6A,0x46) 0x44000200 0x00000053 0x00000000 0x00000000
+GPP_K5 (0x6A,0x48) 0x44000200 0x00000054 0x00000000 0x00000000
+GPP_K6 (0x6A,0x4A) 0x44000a02 0x00000055 0x00000000 0x00000000
+GPP_K7 (0x6A,0x4C) 0x44000a02 0x00000056 0x00000000 0x00000000
+GPP_K8 (0x6A,0x4E) 0x44000700 0x00000057 0x00000000 0x00000000
+GPP_K9 (0x6A,0x50) 0x44000700 0x00000058 0x00000000 0x00000000
+GPP_K10 (0x6A,0x52) 0x44000a02 0x00000059 0x00000000 0x00000000
+GPP_K11 (0x6A,0x54) 0x44000200 0x0000005a 0x00000000 0x00000000
+GPP_F0 (0x6A,0x5C) 0x44000200 0x0000005b 0x00000000 0x00000000
+GPP_F1 (0x6A,0x5E) 0x44000200 0x0000005c 0x00000000 0x00000000
+GPP_F2 (0x6A,0x60) 0x44000200 0x0000005d 0x00000000 0x00000000
+GPP_F3 (0x6A,0x62) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_F4 (0x6A,0x64) 0x44000200 0x00000060 0x00000000 0x00000000
+GPP_F5 (0x6A,0x66) 0x84000200 0x00000061 0x00000000 0x00000000
+GPP_F6 (0x6A,0x68) 0x44000200 0x00000062 0x00000000 0x00000000
+GPP_F7 (0x6A,0x6A) 0x44000200 0x00000063 0x00000000 0x00000000
+GPP_F8 (0x6A,0x6C) 0x44000100 0x00000064 0x00000000 0x00000000
+GPP_F9 (0x6A,0x6E) 0x42880102 0x00000065 0x00000000 0x00000000
+GPP_F10 (0x6A,0x70) 0x44000200 0x00000066 0x00000000 0x00000000
+GPP_F11 (0x6A,0x72) 0x44000200 0x00000067 0x00000000 0x00000000
+GPP_F12 (0x6A,0x74) 0x44000200 0x00000068 0x00000000 0x00000000
+GPP_F13 (0x6A,0x76) 0x44000200 0x00000069 0x00000000 0x00000000
+GPP_F14 (0x6A,0x78) 0x44000200 0x0000006a 0x00000000 0x00000000
+GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_F16 (0x6A,0x7C) 0x44000200 0x0000006c 0x00000000 0x00000000
+GPP_F17 (0x6A,0x7E) 0x44000200 0x0000006d 0x00000000 0x00000000
+GPP_F18 (0x6A,0x80) 0x44000200 0x0000006e 0x00000000 0x00000000
+GPP_F19 (0x6A,0x82) 0x44000700 0x0000006f 0x00000000 0x00000000
+GPP_F20 (0x6A,0x84) 0x44000700 0x00000070 0x00000000 0x00000000
+GPP_F21 (0x6A,0x86) 0x44000700 0x00000071 0x00000000 0x00000000
+GPP_F22 (0x6A,0x88) 0x44000201 0x00000072 0x00000000 0x00000000
+GPP_F23 (0x6A,0x8A) 0x44000200 0x00000073 0x00000000 0x00000000
+GPP_D0 (0x69,0x20) 0x44000200 0x00000026 0x00000000 0x00000000
+GPP_D1 (0x69,0x22) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_D2 (0x69,0x24) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_D3 (0x69,0x26) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_D4 (0x69,0x28) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_D5 (0x69,0x2A) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_D6 (0x69,0x2C) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_D7 (0x69,0x2E) 0x44000200 0x0000002d 0x00000000 0x00000000
+GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
+GPP_D9 (0x69,0x32) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D10 (0x69,0x34) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D13 (0x69,0x3A) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D14 (0x69,0x3C) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
+GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D22 (0x69,0x4C) 0x40000702 0x00000000 0x00000000 0x00000000
+GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+  vendor_name: Realtek
+  chip_name: ALC1220
+  vendor_id: 0x10ec1220
+  subsystem_id: 0x15583702
+  revision_id: 0x100101
+  0x12: 0x90a60130
+  0x14: 0x0421101f
+  0x15: 0x40000000
+  0x16: 0x411111f0
+  0x17: 0x411111f0
+  0x18: 0x04a11040
+  0x19: 0x411111f0
+  0x1a: 0x411111f0
+  0x1b: 0x90170110
+  0x1d: 0x40b7952d
+  0x1e: 0x04451150
+hdaudioC0D2
+  vendor_name: Intel
+  chip_name: Raptorlake HDMI
+  vendor_id: 0x80862818
+  subsystem_id: 0x80860101
+  revision_id: 0x100000
+  0x04: 0x18560010
+  0x06: 0x18560010
+  0x08: 0x18560010
+  0x0a: 0x18560010
+  0x0b: 0x18560010
+  0x0c: 0x18560010
+  0x0d: 0x18560010
+  0x0e: 0x18560010
+  0x0f: 0x18560010
+hdaudioC1D0
+  vendor_name: Nvidia
+  chip_name: Generic HDMI
+  vendor_id: 0x10de00a5
+  subsystem_id: 0x10de0000
+  revision_id: 0x100100
+  0x04: 0x585600f0
+  0x05: 0x185600f0
+  0x06: 0x185600f0
+  0x07: 0x185600f0
--- a/models/bonw15/coreboot.config
+++ b/models/bonw15/coreboot.config
@@ -0,0 +1,28 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_BONW15=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+CONFIG_HAVE_GBE_BIN=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_GBE_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/gbe.rom"
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
+CONFIG_POST_IO=n
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_V2=y
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
+
+# Custom FSP
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Fsp.fd"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Include"
+CONFIG_FSP_USE_REPO=n
--- a/models/bonw15/ec.config
+++ b/models/bonw15/ec.config
@@ -0,0 +1 @@
+BOARD=system76/bonw15
--- a/models/bonw15/ecspy.txt
+++ b/models/bonw15/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 6
+A0: data 1 mirror 1 pot 0 control 80
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 1 mirror 0 pot 0 control 00
+A3: data 0 mirror 0 pot 0 control 00
+A4: data 0 mirror 1 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 0 mirror 0 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 84
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 1 mirror 1 pot 0 control 40
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 40
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 40
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 0 mirror 0 pot 0 control 40
+D4: data 0 mirror 0 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 0 mirror 0 pot 0 control 02
+D7: data 1 mirror 1 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 1 mirror 1 pot 0 control 84
+E3: data 1 mirror 1 pot 0 control 40
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 0 mirror 0 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 40
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 1 mirror 1 pot 0 control 40
+F7: data 1 mirror 1 pot 0 control 80
+G0: data 1 mirror 1 pot 0 control 80
+G1: data 1 mirror 1 pot 0 control 40
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 0 mirror 0 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 0 mirror 0 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 1 mirror 1 pot 0 control 80
+H4: data 0 mirror 0 pot 0 control 80
+H5: data 0 mirror 0 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 40
+H7: data 1 mirror 1 pot 0 control 80
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 80
+I3: data 0 mirror 0 pot 0 control 00
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 1 mirror 1 pot 0 control 40
+I6: data 0 mirror 0 pot 0 control 00
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 1 mirror 1 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 40
+J5: data 1 mirror 1 pot 0 control 80
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 0 mirror 0 pot 0 control 84
+M0: data 0 mirror 0 control 06
+M1: data 0 mirror 0 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 1 control 06
+M5: data 0 mirror 0 control 00
+M6: data 0 mirror 0 control 86
+M7: data 0 mirror 0 control 00
--- a/models/bonw15/edk2.config
+++ b/models/bonw15/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/bonw15/fd.rom
+++ b/models/bonw15/fd.rom
--- a/models/bonw15/gpio.h
+++ b/models/bonw15/gpio.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD2, 0x42880100, 0x0000),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPI(GPD7, NONE, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD9, 0, PWROK),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD11, 0, DEEP),
+	PAD_CFG_GPO(GPD12, 0, DEEP),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+	PAD_CFG_GPO(GPP_A8, 0, DEEP),
+	PAD_CFG_GPO(GPP_A9, 0, DEEP),
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
+	PAD_CFG_GPO(GPP_A13, 0, DEEP),
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000),
+	PAD_CFG_GPO(GPP_B1, 0, DEEP),
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	PAD_CFG_GPO(GPP_B5, 0, DEEP),
+	PAD_CFG_GPO(GPP_B6, 0, DEEP),
+	PAD_CFG_GPO(GPP_B7, 0, DEEP),
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	PAD_CFG_GPO(GPP_B9, 0, DEEP),
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_CFG_GPO(GPP_B11, 0, DEEP),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 1, PWROK),
+	PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_CFG_GPO(GPP_B20, 0, DEEP),
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_C3, 0, DEEP),
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C6, 0, DEEP),
+	PAD_CFG_GPO(GPP_C7, 0, DEEP),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_C9, 0, DEEP),
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+	PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	PAD_CFG_GPO(GPP_C23, 0, DEEP),
+	PAD_CFG_GPO(GPP_D0, 0, DEEP),
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPO(GPP_D4, 0, DEEP),
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	PAD_CFG_GPO(GPP_D7, 0, DEEP),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	PAD_CFG_GPO(GPP_E1, 0, DEEP),
+	PAD_CFG_GPO(GPP_E2, 0, DEEP),
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	PAD_CFG_GPO(GPP_E5, 0, DEEP),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_GPO(GPP_E13, 0, DEEP),
+	PAD_CFG_GPO(GPP_E14, 0, DEEP),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	PAD_CFG_GPO(GPP_E17, 0, DEEP),
+	PAD_CFG_GPO(GPP_E18, 1, DEEP),
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	PAD_CFG_GPO(GPP_F0, 0, DEEP),
+	PAD_CFG_GPO(GPP_F1, 0, DEEP),
+	PAD_CFG_GPO(GPP_F2, 0, DEEP),
+	PAD_CFG_GPO(GPP_F3, 0, DEEP),
+	PAD_CFG_GPO(GPP_F4, 0, DEEP),
+	PAD_CFG_GPO(GPP_F5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F6, 0, DEEP),
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_F9, 0x42880100, 0x0000),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	PAD_CFG_GPO(GPP_F13, 0, DEEP),
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F22, 1, DEEP),
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),
+	PAD_CFG_GPO(GPP_G0, 0, PWROK),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_G7, 0x42800100, 0x0000),
+	PAD_CFG_GPI(GPP_H0, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPI(GPP_H2, NONE, DEEP),
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_NC(GPP_H6, NONE),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H17, 1, DEEP),
+	PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H19, 0, DEEP),
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	PAD_CFG_GPO(GPP_H21, 1, DEEP),
+	PAD_CFG_GPO(GPP_H22, 0, DEEP),
+	PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+	PAD_CFG_GPO(GPP_I0, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000),
+	PAD_CFG_GPO(GPP_I5, 0, DEEP),
+	PAD_CFG_GPO(GPP_I6, 0, DEEP),
+	PAD_CFG_GPO(GPP_I7, 0, DEEP),
+	PAD_CFG_GPO(GPP_I8, 0, DEEP),
+	PAD_CFG_GPO(GPP_I9, 0, DEEP),
+	PAD_CFG_GPO(GPP_I10, 0, DEEP),
+	PAD_NC(GPP_I11, NONE),
+	PAD_NC(GPP_I12, NONE),
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+	PAD_CFG_GPO(GPP_I15, 0, DEEP),
+	PAD_CFG_GPO(GPP_I16, 0, DEEP),
+	PAD_CFG_GPO(GPP_I17, 0, DEEP),
+	PAD_CFG_GPI(GPP_I18, NONE, DEEP),
+	PAD_CFG_GPO(GPP_I19, 0, DEEP),
+	PAD_CFG_GPO(GPP_I20, 0, DEEP),
+	PAD_CFG_GPO(GPP_I21, 0, DEEP),
+	PAD_CFG_GPI(GPP_I22, NONE, DEEP),
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_J8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_J9, 0, DEEP),
+	PAD_CFG_GPO(GPP_J10, 0, DEEP),
+	PAD_CFG_GPO(GPP_J11, 0, DEEP),
+	PAD_CFG_GPO(GPP_K0, 0, DEEP),
+	PAD_CFG_GPO(GPP_K1, 0, DEEP),
+	PAD_CFG_GPO(GPP_K2, 0, DEEP),
+	PAD_CFG_GPO(GPP_K3, 0, DEEP),
+	PAD_CFG_GPO(GPP_K4, 0, DEEP),
+	PAD_CFG_GPO(GPP_K5, 0, DEEP),
+	PAD_CFG_NF(GPP_K6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_K7, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
+	PAD_CFG_GPO(GPP_K11, 0, DEEP),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R5, 0, DEEP),
+	PAD_CFG_GPO(GPP_R6, 0, DEEP),
+	PAD_CFG_GPO(GPP_R7, 0, DEEP),
+	PAD_CFG_GPI(GPP_R8, NONE, DEEP),
+	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R10, 0, DEEP),
+	PAD_CFG_GPO(GPP_R11, 0, DEEP),
+	PAD_CFG_GPO(GPP_R12, 0, DEEP),
+	PAD_CFG_GPO(GPP_R13, 0, DEEP),
+	PAD_CFG_GPO(GPP_R14, 0, DEEP),
+	PAD_CFG_GPO(GPP_R15, 0, DEEP),
+	PAD_CFG_GPO(GPP_R16, 1, DEEP),
+	PAD_CFG_GPO(GPP_R17, 0, DEEP),
+	PAD_CFG_GPO(GPP_R18, 0, DEEP),
+	PAD_CFG_GPO(GPP_R19, 0, DEEP),
+	PAD_CFG_GPO(GPP_R20, 0, DEEP),
+	PAD_CFG_GPO(GPP_R21, 0, DEEP),
+	PAD_CFG_GPO(GPP_S0, 0, DEEP),
+	PAD_CFG_GPO(GPP_S1, 0, DEEP),
+	PAD_CFG_GPO(GPP_S2, 0, DEEP),
+	PAD_CFG_GPO(GPP_S3, 0, DEEP),
+	PAD_CFG_GPO(GPP_S4, 0, DEEP),
+	PAD_CFG_GPO(GPP_S5, 0, DEEP),
+	PAD_CFG_GPO(GPP_S6, 0, DEEP),
+	PAD_CFG_GPO(GPP_S7, 0, DEEP),
+};
+
+#endif
+
+#endif
--- a/models/bonw15/hda_verb.c
+++ b/models/bonw15/hda_verb.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15583702, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15583702),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+	/* Intel, RaptorlakeHDMI */
+	0x80862818, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+	/* Nvidia, GenericHDMI */
+	0x10de00a5, /* Vendor ID */
+	0x10de0000, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x10de0000),
+	AZALIA_PIN_CFG(0, 0x04, 0x585600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/models/bonw15/me.rom
+++ b/models/bonw15/me.rom
--- a/models/bonw15/vbt.rom
+++ b/models/bonw15/vbt.rom
--- a/models/darp5/edk2.config
+++ b/models/darp5/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp6/edk2.config
+++ b/models/darp6/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp7/edk2.config
+++ b/models/darp7/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp8/edk2.config
+++ b/models/darp8/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp2/edk2.config
+++ b/models/galp2/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp3-b/edk2.config
+++ b/models/galp3-b/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp3-c/edk2.config
+++ b/models/galp3-c/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp3/edk2.config
+++ b/models/galp3/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp4/edk2.config
+++ b/models/galp4/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp5/edk2.config
+++ b/models/galp5/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp6/edk2.config
+++ b/models/galp6/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze14_1650/edk2.config
+++ b/models/gaze14_1650/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze14_1660ti/edk2.config
+++ b/models/gaze14_1660ti/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze15/edk2.config
+++ b/models/gaze15/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze16-3050/edk2.config
+++ b/models/gaze16-3050/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze16-3060-b/edk2.config
+++ b/models/gaze16-3060-b/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze16-3060/edk2.config
+++ b/models/gaze16-3060/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze17-3050/edk2.config
+++ b/models/gaze17-3050/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze17-3060-b/edk2.config
+++ b/models/gaze17-3060-b/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/gaze18/AlderLakeFspBinPkg
+++ b/models/gaze18/AlderLakeFspBinPkg
@@ -0,0 +1 @@
+../oryp11/AlderLakeFspBinPkg
--- a/models/gaze18/IntelGopDriver.efi
+++ b/models/gaze18/IntelGopDriver.efi
--- a/models/gaze18/README.md
+++ b/models/gaze18/README.md
@@ -0,0 +1,12 @@
+# System76 Gazelle (gaze18)
+
+## Contents
+
+- [EC](./ec.rom)
+  - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+  - Size: 4 KB
+  - HAP: false
+- [ME](./me.rom)
+  - Size: 4824 KB
+  - Version: 16.1.25.2073
--- a/models/gaze18/README.md.in
+++ b/models/gaze18/README.md.in
@@ -0,0 +1 @@
+# System76 Gazelle (gaze18)
--- a/models/gaze18/chip.txt
+++ b/models/gaze18/chip.txt
@@ -0,0 +1 @@
+GD25Q256D
--- a/models/gaze18/coreboot-collector.txt
+++ b/models/gaze18/coreboot-collector.txt
@@ -0,0 +1,256 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA706, Revision 0x00
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x00
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA7A0, Revision 0x04
+PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x00
+PCI Device: 0000:00:06.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x00
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
+PCI Device: 0000:00:0d.0: Class 0x000C0330, Vendor 0x8086, Device 0xA71E, Revision 0x00
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x51ED, Revision 0x01
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x51EF, Revision 0x01
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x51F1, Revision 0x01
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x51E8, Revision 0x01
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x51E0, Revision 0x01
+PCI Device: 0000:00:17.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x51B0, Revision 0x01
+PCI Device: 0000:00:1d.2: Class 0x00060400, Vendor 0x8086, Device 0x51B2, Revision 0x01
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x519D, Revision 0x01
+PCI Device: 0000:00:1f.3: Class 0x00040380, Vendor 0x8086, Device 0x51CA, Revision 0x01
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x51A3, Revision 0x01
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x51A4, Revision 0x01
+PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x25A2, Revision 0xA1
+PCI Device: 0000:02:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
+PCI Device: 0000:03:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
+PCI Device: 10000:e0:06.0: Class 0x00060400, Vendor 0x8086, Device 0xA74D, Revision 0x00
+PCI Device: 10000:e0:17.0: Class 0x00010601, Vendor 0x8086, Device 0x51D3, Revision 0x01
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
+## GPIO ##
+600 Series PCH-LP
+GPP_B0 (0x6E,0x00) 0x44000700 0x0003c018 0x00000100 0x00000000
+GPP_B1 (0x6E,0x02) 0x44000700 0x0003c019 0x00000100 0x00000000
+GPP_B2 (0x6E,0x04) 0x44000200 0x0000001a 0x00000000 0x00000000
+GPP_B3 (0x6E,0x06) 0x44000102 0x0000001b 0x00000000 0x00000000
+GPP_B4 (0x6E,0x08) 0x44000100 0x0000001c 0x00000000 0x00000000
+GPP_B5 (0x6E,0x0A) 0x44000200 0x0000001d 0x00000000 0x00000000
+GPP_B6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
+GPP_B7 (0x6E,0x0E) 0x44000200 0x0000001f 0x00000000 0x00000000
+GPP_B8 (0x6E,0x10) 0x44000200 0x00000020 0x00000000 0x00000000
+GPP_B9 (0x6E,0x12) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_B10 (0x6E,0x14) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_B11 (0x6E,0x16) 0x44000300 0x00000023 0x00000000 0x00000000
+GPP_B12 (0x6E,0x18) 0x44000700 0x0003c024 0x00000000 0x00000000
+GPP_B13 (0x6E,0x1A) 0x44000700 0x0003c025 0x00000000 0x00000000
+GPP_B14 (0x6E,0x1C) 0x44001100 0x00000026 0x00000000 0x00000000
+GPP_B15 (0x6E,0x1E) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_B16 (0x6E,0x20) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_B17 (0x6E,0x22) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_B18 (0x6E,0x24) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_B19 (0x6E,0x26) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_B20 (0x6E,0x28) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_B21 (0x6E,0x2A) 0x44000200 0x0000002d 0x00000000 0x00000000
+GPP_B22 (0x6E,0x2C) 0x44000200 0x0000002e 0x00000000 0x00000000
+GPP_B23 (0x6E,0x2E) 0x44000200 0x0000002f 0x00000000 0x00000000
+GPP_T2 (0x6E,0x38) 0x44000200 0x00000032 0x00000000 0x00000000
+GPP_T3 (0x6E,0x3A) 0x44000200 0x00000033 0x00000000 0x00000000
+GPP_A0 (0x6E,0x54) 0x44000700 0x0003f040 0x00000100 0x00000000
+GPP_A1 (0x6E,0x56) 0x44000702 0x0003f041 0x00000100 0x00000000
+GPP_A2 (0x6E,0x58) 0x44000700 0x0003f042 0x00000100 0x00000000
+GPP_A3 (0x6E,0x5A) 0x44000700 0x0003f043 0x00000100 0x00000000
+GPP_A4 (0x6E,0x5C) 0x44000700 0x0003f044 0x00000100 0x00000000
+GPP_A5 (0x6E,0x5E) 0x44000702 0x00003045 0x00000100 0x00000000
+GPP_A6 (0x6E,0x60) 0x44000200 0x00000046 0x00000100 0x00000000
+GPP_A7 (0x6E,0x62) 0x44000200 0x00000047 0x00000000 0x00000000
+GPP_A8 (0x6E,0x64) 0x84000201 0x00000048 0x00000000 0x00000000
+GPP_A9 (0x6E,0x66) 0x44000700 0x0003d049 0x00000100 0x00000000
+GPP_A10 (0x6E,0x68) 0x44000700 0x0003c04a 0x00000100 0x00000000
+GPP_A11 (0x6E,0x6A) 0x44000200 0x0000004b 0x00000000 0x00000000
+GPP_A12 (0x6E,0x6C) 0x44000200 0x0000004c 0x00000000 0x00000000
+GPP_A13 (0x6E,0x6E) 0x84000201 0x0000004d 0x00000000 0x00000000
+GPP_A14 (0x6E,0x70) 0x44000200 0x0000004e 0x00000000 0x00000000
+GPP_A15 (0x6E,0x72) 0x44000900 0x0002404f 0x00000000 0x00000000
+GPP_A16 (0x6E,0x74) 0x44000702 0x00000050 0x00000000 0x00000000
+GPP_A17 (0x6E,0x76) 0x80100102 0x00000051 0x00000000 0x00000000
+GPP_A18 (0x6E,0x78) 0x44000500 0x00024052 0x00000000 0x00000000
+GPP_A19 (0x6E,0x7A) 0x44000100 0x00000053 0x00000000 0x00000000
+GPP_A20 (0x6E,0x7C) 0x44000200 0x00000054 0x00000000 0x00000000
+GPP_A21 (0x6E,0x7E) 0x44000200 0x00000055 0x00000000 0x00000000
+GPP_A22 (0x6E,0x80) 0x44000200 0x00000056 0x00000000 0x00000000
+GPP_A23 (0x6E,0x82) 0x44000200 0x00000057 0x00000100 0x00000000
+GPP_S0 (0x6D,0x00) 0x44000200 0x0180006c 0x00000000 0x00000000
+GPP_S1 (0x6D,0x02) 0x44000200 0x0180006d 0x00000000 0x00000000
+GPP_S2 (0x6D,0x04) 0x44000200 0x0180006e 0x00000000 0x00000000
+GPP_S3 (0x6D,0x06) 0x44000200 0x0180006f 0x00000000 0x00000000
+GPP_S4 (0x6D,0x08) 0x44000200 0x01800070 0x00000000 0x00000000
+GPP_S5 (0x6D,0x0A) 0x44000200 0x01800071 0x00000000 0x00000000
+GPP_S6 (0x6D,0x0C) 0x44000200 0x01800072 0x00000000 0x00000000
+GPP_S7 (0x6D,0x0E) 0x44000200 0x01800073 0x00000000 0x00000000
+GPP_H0 (0x6D,0x10) 0x44000200 0x00000074 0x00000000 0x00000000
+GPP_H1 (0x6D,0x12) 0x44000200 0x00000075 0x00000000 0x00000000
+GPP_H2 (0x6D,0x14) 0x44000200 0x00000076 0x00000000 0x00000000
+GPP_H3 (0x6D,0x16) 0x44000102 0x00000077 0x00000000 0x00000000
+GPP_H4 (0x6D,0x18) 0x44000502 0x00000018 0x00000000 0x00000000
+GPP_H5 (0x6D,0x1A) 0x44000502 0x00000019 0x00000000 0x00000000
+GPP_H6 (0x6D,0x1C) 0x44000102 0x0000001a 0x00000000 0x00000000
+GPP_H7 (0x6D,0x1E) 0x44000102 0x0000001b 0x00000000 0x00000000
+GPP_H8 (0x6D,0x20) 0x44000200 0x0000001c 0x00000100 0x00000000
+GPP_H9 (0x6D,0x22) 0x44000200 0x0000001d 0x00000100 0x00000000
+GPP_H10 (0x6D,0x24) 0x44000102 0x0000001e 0x00000000 0x00000000
+GPP_H11 (0x6D,0x26) 0x44000102 0x0000001f 0x00000000 0x00000000
+GPP_H12 (0x6D,0x28) 0x44000200 0x00000020 0x00000000 0x00000000
+GPP_H13 (0x6D,0x2A) 0x04001500 0x00000021 0x00000000 0x00000000
+GPP_H14 (0x6D,0x2C) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_H15 (0x6D,0x2E) 0x44000500 0x0003c023 0x00000000 0x00000000
+GPP_H16 (0x6D,0x30) 0x44000200 0x00000024 0x00000000 0x00000000
+GPP_H17 (0x6D,0x32) 0x44000502 0x0003c025 0x00000000 0x00000000
+GPP_H18 (0x6D,0x34) 0x44000700 0x0003c026 0x00000000 0x00000000
+GPP_H19 (0x6D,0x36) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_H20 (0x6D,0x38) 0x44000300 0x00000028 0x00000000 0x00000000
+GPP_H21 (0x6D,0x3A) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_H22 (0x6D,0x3C) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_H23 (0x6D,0x3E) 0x44000b02 0x0000002b 0x00000000 0x00000000
+GPP_D0 (0x6D,0x40) 0x44000201 0x0000002c 0x00000000 0x00000000
+GPP_D1 (0x6D,0x42) 0x44000102 0x0000002d 0x00000000 0x00000000
+GPP_D2 (0x6D,0x44) 0x44000300 0x0000002e 0x00000000 0x00000000
+GPP_D3 (0x6D,0x46) 0x44000200 0x0000002f 0x00000000 0x00000000
+GPP_D4 (0x6D,0x48) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_D5 (0x6D,0x4A) 0x44000700 0x00000031 0x00000000 0x00000000
+GPP_D6 (0x6D,0x4C) 0x44000702 0x00000032 0x00000000 0x00000000
+GPP_D7 (0x6D,0x4E) 0x44000702 0x00000033 0x00000000 0x00000000
+GPP_D8 (0x6D,0x50) 0x44000702 0x00000034 0x00000000 0x00000000
+GPP_D9 (0x6D,0x52) 0x44000200 0x00000035 0x00000100 0x00000000
+GPP_D10 (0x6D,0x54) 0x44000200 0x00000036 0x00000100 0x00000000
+GPP_D11 (0x6D,0x56) 0x44000b00 0x0001fc37 0x00000000 0x00000000
+GPP_D12 (0x6D,0x58) 0x44000b02 0x0001fc38 0x00000000 0x00000000
+GPP_D13 (0x6D,0x5A) 0x44000102 0x00000039 0x00000000 0x00000000
+GPP_D14 (0x6D,0x5C) 0x84000201 0x0000003a 0x00000000 0x00000000
+GPP_D15 (0x6D,0x5E) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_D16 (0x6D,0x60) 0x84000201 0x0000003c 0x00000000 0x00000000
+GPP_D17 (0x6D,0x62) 0x44000200 0x0000003d 0x00000000 0x00000000
+GPP_D18 (0x6D,0x64) 0x44000200 0x0000003e 0x00000000 0x00000000
+GPP_D19 (0x6D,0x66) 0x44000200 0x0000003f 0x00000100 0x00000000
+GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000702 0x00003c61 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x04000702 0x00003c62 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x44000200 0x00000067 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000200 0x00000069 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x04000600 0x0000006b 0x00000000 0x00000000
+GPP_C0 (0x6A,0x00) 0x44000502 0x0003c06e 0x00000000 0x00000000
+GPP_C1 (0x6A,0x02) 0x44000502 0x0003c06f 0x00000000 0x00000000
+GPP_C2 (0x6A,0x04) 0x84000201 0x00000070 0x00000800 0x00000000
+GPP_C3 (0x6A,0x06) 0x44000102 0x00000071 0x00000000 0x00000000
+GPP_C4 (0x6A,0x08) 0x44000102 0x00000072 0x00000000 0x00000000
+GPP_C5 (0x6A,0x0A) 0x44000200 0x00000073 0x00000000 0x00000000
+GPP_C6 (0x6A,0x0C) 0x44000300 0x00000074 0x00000000 0x00000000
+GPP_C7 (0x6A,0x0E) 0x44000300 0x00000075 0x00000000 0x00000000
+GPP_C8 (0x6A,0x10) 0x44000300 0x00000076 0x00000000 0x00000000
+GPP_C9 (0x6A,0x12) 0x44000300 0x00000077 0x00000000 0x00000000
+GPP_C10 (0x6A,0x14) 0x44000300 0x00000018 0x00000000 0x00000000
+GPP_C11 (0x6A,0x16) 0x44000300 0x00000019 0x00000000 0x00000000
+GPP_C12 (0x6A,0x18) 0x44000300 0x0000001a 0x00000000 0x00000000
+GPP_C13 (0x6A,0x1A) 0x44000300 0x0000001b 0x00000000 0x00000000
+GPP_C14 (0x6A,0x1C) 0x44000300 0x0000001c 0x00000000 0x00000000
+GPP_C15 (0x6A,0x1E) 0x44000300 0x0000001d 0x00000000 0x00000000
+GPP_C16 (0x6A,0x20) 0x44000300 0x0000001e 0x00000000 0x00000000
+GPP_C17 (0x6A,0x22) 0x44000300 0x0000001f 0x00000000 0x00000000
+GPP_C18 (0x6A,0x24) 0x44000300 0x00000020 0x00000000 0x00000000
+GPP_C19 (0x6A,0x26) 0x44000300 0x00000021 0x00000000 0x00000000
+GPP_C20 (0x6A,0x28) 0x44000300 0x00000022 0x00000000 0x00000000
+GPP_C21 (0x6A,0x2A) 0x44000300 0x00000023 0x00000000 0x00000000
+GPP_C22 (0x6A,0x2C) 0x44000300 0x00000024 0x00000000 0x00000000
+GPP_C23 (0x6A,0x2E) 0x44000300 0x00000025 0x00000000 0x00000000
+GPP_F0 (0x6A,0x30) 0x44000500 0x0003c056 0x00000100 0x00000000
+GPP_F1 (0x6A,0x32) 0x44000502 0x0003f057 0x00000100 0x00000000
+GPP_F2 (0x6A,0x34) 0x44000500 0x0003c058 0x00000100 0x00000000
+GPP_F3 (0x6A,0x36) 0x44000500 0x0003f059 0x00000100 0x00000000
+GPP_F4 (0x6A,0x38) 0x44000500 0x0003c05a 0x00000100 0x00000000
+GPP_F5 (0x6A,0x3A) 0x44000900 0x0003c05b 0x00000100 0x00000000
+GPP_F6 (0x6A,0x3C) 0x44000502 0x0000005c 0x00000100 0x00000000
+GPP_F7 (0x6A,0x3E) 0x44000201 0x0000005d 0x00000000 0x00000000
+GPP_F8 (0x6A,0x40) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_F9 (0x6A,0x42) 0x44000200 0x0000005f 0x00000100 0x00000000
+GPP_F10 (0x6A,0x44) 0x44000200 0x00000060 0x00000000 0x00000000
+GPP_F11 (0x6A,0x46) 0x44000300 0x00000061 0x00000000 0x00000000
+GPP_F12 (0x6A,0x48) 0x84000100 0x00000062 0x00000100 0x00000000
+GPP_F13 (0x6A,0x4A) 0x84000100 0x00000063 0x00000000 0x00000000
+GPP_F14 (0x6A,0x4C) 0x44000300 0x00000064 0x00000000 0x00000000
+GPP_F15 (0x6A,0x4E) 0x44000300 0x00000065 0x00000000 0x00000000
+GPP_F16 (0x6A,0x50) 0x44000200 0x00000066 0x00000000 0x00000000
+GPP_F17 (0x6A,0x52) 0x44000200 0x00000067 0x00000000 0x00000000
+GPP_F18 (0x6A,0x54) 0x44000200 0x00000068 0x00000000 0x00000000
+GPP_F19 (0x6A,0x56) 0x44000702 0x00000069 0x00000000 0x00000000
+GPP_F20 (0x6A,0x58) 0x84000201 0x0003c06a 0x00000000 0x00000000
+GPP_F21 (0x6A,0x5A) 0x44000200 0x0003c06b 0x00000000 0x00000000
+GPP_F22 (0x6A,0x5C) 0x44000500 0x0003c06c 0x00000000 0x00000000
+GPP_F23 (0x6A,0x5E) 0x44000500 0x0003c06d 0x00000000 0x00000000
+GPP_E0 (0x6A,0x6E) 0x44000102 0x00000026 0x00000000 0x00000000
+GPP_E1 (0x6A,0x70) 0x40100102 0x00003027 0x00000000 0x00000000
+GPP_E2 (0x6A,0x72) 0x44000100 0x00000028 0x00000000 0x00000000
+GPP_E3 (0x6A,0x74) 0x84000201 0x00000029 0x00000000 0x00000000
+GPP_E4 (0x6A,0x76) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_E5 (0x6A,0x78) 0x44000102 0x00000031 0x00000000 0x00000000
+GPP_E6 (0x6A,0x7A) 0x44000200 0x00000032 0x00000900 0x00000000
+GPP_E7 (0x6A,0x7C) 0x44000102 0x00000033 0x00000000 0x00000000
+GPP_E8 (0x6A,0x7E) 0x44000200 0x00000034 0x00000000 0x00000000
+GPP_E9 (0x6A,0x80) 0x44000502 0x00000035 0x00000800 0x00000000
+GPP_E10 (0x6A,0x82) 0x44000200 0x00000036 0x00000000 0x00000000
+GPP_E11 (0x6A,0x84) 0x44000100 0x00000037 0x00000000 0x00000000
+GPP_E12 (0x6A,0x86) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_E13 (0x6A,0x88) 0x44000200 0x00000039 0x00000000 0x00000000
+GPP_E14 (0x6A,0x8A) 0x44000700 0x0002403a 0x00000000 0x00000000
+GPP_E15 (0x6A,0x8C) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_E16 (0x6A,0x8E) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_E17 (0x6A,0x90) 0x44000100 0x0000003d 0x00000000 0x00000000
+GPP_E18 (0x6A,0x92) 0x44000200 0x0000003e 0x00000100 0x00000000
+GPP_E19 (0x6A,0x94) 0x44001600 0x00003c3f 0x00000100 0x00000000
+GPP_E20 (0x6A,0x96) 0x44000200 0x00000040 0x00000100 0x00000000
+GPP_E21 (0x6A,0x98) 0x44000200 0x00000041 0x00000100 0x00000000
+GPP_E22 (0x6A,0x9A) 0x44000600 0x0003c042 0x00000000 0x00000000
+GPP_E23 (0x6A,0x9C) 0x44000602 0x0003c043 0x00000000 0x00000000
+GPP_R0 (0x69,0x00) 0x44000500 0x0003c058 0x00000000 0x00000000
+GPP_R1 (0x69,0x02) 0x44000500 0x0003fc59 0x00000000 0x00000000
+GPP_R2 (0x69,0x04) 0x44000500 0x0003fc5a 0x00000000 0x00000000
+GPP_R3 (0x69,0x06) 0x44000500 0x0003fc5b 0x00000000 0x00000000
+GPP_R4 (0x69,0x08) 0x44000500 0x0003c05c 0x00000000 0x00000000
+GPP_R5 (0x69,0x0A) 0x44000200 0x0000005d 0x00000000 0x00000000
+GPP_R6 (0x69,0x0C) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_R7 (0x69,0x0E) 0x44000200 0x0000005f 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+  vendor_name: Realtek
+  chip_name: ALC256
+  vendor_id: 0x10ec0256
+  subsystem_id: 0x15585630
+  revision_id: 0x100002
+  0x12: 0x90a60130
+  0x13: 0x40000000
+  0x14: 0x90170110
+  0x18: 0x411111f0
+  0x19: 0x411111f0
+  0x1a: 0x411111f0
+  0x1b: 0x02a11040
+  0x1d: 0x41700001
+  0x1e: 0x411111f0
+  0x21: 0x02211020
+hdaudioC0D2
+  vendor_name: Intel
+  chip_name: Raptorlake-P HDMI
+  vendor_id: 0x8086281f
+  subsystem_id: 0x80860101
+  revision_id: 0x100000
+  0x04: 0x18560010
+  0x06: 0x18560010
+  0x08: 0x18560010
+  0x0a: 0x18560010
+  0x0b: 0x18560010
+  0x0c: 0x18560010
+  0x0d: 0x18560010
+  0x0e: 0x18560010
+  0x0f: 0x18560010
--- a/models/gaze18/coreboot.config
+++ b/models/gaze18/coreboot.config
@@ -0,0 +1,24 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_GAZE18=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_POST_IO=n
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_V2=y
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
+
+# Custom FSP
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Fsp.fd"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Include"
+CONFIG_FSP_USE_REPO=n
--- a/models/gaze18/ec.config
+++ b/models/gaze18/ec.config
@@ -0,0 +1 @@
+BOARD=system76/gaze18
--- a/models/gaze18/ecspy.txt
+++ b/models/gaze18/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 6
+A0: data 1 mirror 1 pot 0 control 00
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 1 mirror 0 pot 0 control 00
+A3: data 1 mirror 1 pot 0 control 44
+A4: data 0 mirror 0 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 1 mirror 1 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 84
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 0 mirror 0 pot 0 control 40
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 80
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 44
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 1 mirror 1 pot 0 control 40
+D4: data 1 mirror 1 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 0 mirror 0 pot 0 control 02
+D7: data 1 mirror 1 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 0 mirror 0 pot 0 control 84
+E3: data 1 mirror 1 pot 0 control 44
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 0 mirror 0 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 40
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 0 mirror 0 pot 0 control 00
+F7: data 0 mirror 0 pot 0 control 44
+G0: data 0 mirror 0 pot 0 control 80
+G1: data 1 mirror 1 pot 0 control 44
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 0 mirror 0 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 1 mirror 1 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 1 mirror 1 pot 0 control 84
+H4: data 1 mirror 1 pot 0 control 40
+H5: data 0 mirror 0 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 80
+H7: data 1 mirror 1 pot 0 control 44
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 00
+I3: data 0 mirror 0 pot 0 control 00
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 0 mirror 0 pot 0 control 00
+I6: data 0 mirror 0 pot 0 control 00
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 0 mirror 0 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 80
+J5: data 0 mirror 0 pot 0 control 40
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 1 mirror 1 pot 0 control 80
+M0: data 0 mirror 0 control 06
+M1: data 0 mirror 1 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 1 control 06
+M5: data 0 mirror 0 control 00
+M6: data 1 mirror 1 control 86
+M7: data 0 mirror 0 control 00
--- a/models/gaze18/edk2.config
+++ b/models/gaze18/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/gaze18/fd.rom
+++ b/models/gaze18/fd.rom
--- a/models/gaze18/gpio.h
+++ b/models/gaze18/gpio.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, DEEP),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD9, 0, PWROK),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A6, 0, DEEP),
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP),
+	PAD_CFG_GPO(GPP_A23, 0, DEEP),
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B2, 0, DEEP),
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B5, 0, DEEP),
+	PAD_CFG_GPO(GPP_B6, 0, DEEP),
+	PAD_CFG_GPO(GPP_B7, 0, DEEP),
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	PAD_CFG_GPO(GPP_B9, 0, DEEP),
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_CFG_GPO(GPP_B19, 0, DEEP),
+	PAD_CFG_GPO(GPP_B20, 0, DEEP),
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
+	PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_CFG_GPO(GPP_D0, 1, DEEP),
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+	PAD_NC(GPP_D2, NONE),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	PAD_CFG_GPO(GPP_D10, 0, DEEP),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E8, 0, DEEP),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E10, 0, DEEP),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E12, 0, DEEP),
+	PAD_CFG_GPO(GPP_E13, 0, DEEP),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E18, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F7, 1, DEEP),
+	PAD_CFG_GPO(GPP_F8, 0, DEEP),
+	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPO(GPP_H2, 0, DEEP),
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H7, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H8, 0, DEEP),
+	PAD_CFG_GPO(GPP_H9, 0, DEEP),
+	PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000),
+	PAD_CFG_GPO(GPP_H14, 0, DEEP),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H16, 0, DEEP),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H19, 0, DEEP),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R5, 0, DEEP),
+	PAD_CFG_GPO(GPP_R6, 0, DEEP),
+	PAD_CFG_GPO(GPP_R7, 0, DEEP),
+	PAD_CFG_GPO(GPP_S0, 0, DEEP),
+	PAD_CFG_GPO(GPP_S1, 0, DEEP),
+	PAD_CFG_GPO(GPP_S2, 0, DEEP),
+	PAD_CFG_GPO(GPP_S3, 0, DEEP),
+	PAD_CFG_GPO(GPP_S4, 0, DEEP),
+	PAD_CFG_GPO(GPP_S5, 0, DEEP),
+	PAD_CFG_GPO(GPP_S6, 0, DEEP),
+	PAD_CFG_GPO(GPP_S7, 0, DEEP),
+	PAD_CFG_GPO(GPP_T2, 0, DEEP),
+	PAD_CFG_GPO(GPP_T3, 0, DEEP),
+};
+
+#endif
+
+#endif
--- a/models/gaze18/hda_verb.c
+++ b/models/gaze18/hda_verb.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x15585630, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15585630),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+	/* Intel, Raptorlake-PHDMI */
+	0x8086281f, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/models/gaze18/me.rom
+++ b/models/gaze18/me.rom
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Tim Crawford	799ed79449	coreboot: Fix USB2 on USB-C for gaze18, serw13 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-22 08:41:26 -06:00
Jeremy Soller	218f91800a	Update ec	2023-03-21 20:35:28 -06:00
Jeremy Soller	c1d8c59151	Update EC	2023-03-21 20:07:27 -06:00
Jeremy Soller	40f54be14d	Update coreboot	2023-03-21 19:56:40 -06:00
Jeremy Soller	fd8b7072e8	Update EC	2023-03-21 19:52:26 -06:00
Jeremy Soller	1b5efa53ea	Update coreboot and ec	2023-03-21 13:41:25 -06:00
Jeremy Soller	14b9fc4c58	Update coreboot	2023-03-20 08:14:46 -06:00
Jeremy Soller	80844605e5	Update coreboot	2023-03-17 09:12:09 -06:00
Jeremy Soller	24cf0f0ae5	Update EC	2023-03-15 12:41:56 -06:00
Jeremy Soller	bd32163194	Update coreboot	2023-03-10 13:29:41 -07:00
Tim Crawford	445579e2e9	ec: Fix gaze18 keyboard backlight Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-09 12:58:28 -07:00
Tim Crawford	c78ef82126	edk2: Update Secure Boot keys and DBX Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-09 12:57:55 -07:00
Tim Crawford	b1a5cb3bed	gaze18: Add edk2.config Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-09 12:57:12 -07:00
Jeremy Soller	16ea64a1a7	bonw15: disable BootGuard and PTT	2023-03-08 11:04:42 -07:00
Jeremy Soller	8d43f0b4ba	Add config files for bonw15	2023-03-08 11:01:23 -07:00
Jeremy Soller	60f6621a96	Add extract for bonw15	2023-03-08 10:45:59 -07:00
Jeremy Soller	7919bcf824	Update firmware-update	2023-03-07 12:48:17 -07:00
Jeremy Soller	35c3869e3e	Update firmware-setup	2023-03-07 12:28:42 -07:00
Tim Crawford	b8c0ab0f30	edk2: Add minimal UI for Secure Boot Enable SecureBootConfigDxe with a stripped down UI. It allows users to enable or disable Secure Boot and reset the key data to the defaults. That's it. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-07 10:22:09 -07:00
Tim Crawford	ec114b2385	edk2: Enable Secure Boot support This enables support for Secure Boot. It is not recommended to enable Secure Boot. There is no firmware UI for managing the state or keys. The system will default to disabled in Setup Mode: $ mokutil --sb-state SecureBoot disabled Platform is in Setup Mode This is sufficient to install Windows 11. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-07 10:22:09 -07:00
Jeremy Soller	8ad772a884	Update coreboot and ec	2023-03-07 10:01:40 -07:00
Jeremy Soller	4328edbcf0	Update EC	2023-03-07 10:01:40 -07:00
Jeremy Soller	9b3b018688	Update firmware-update	2023-03-07 10:01:40 -07:00
Jeremy Soller	b1268ce48e	Update EC	2023-03-07 10:01:40 -07:00
Jeremy Soller	a6787eb4b6	Update coreboot	2023-03-07 10:01:40 -07:00
Jeremy Soller	e4bec20de5	Update coreboot	2023-03-07 10:01:40 -07:00
Jeremy Soller	a88b0b1613	Firmware security support	2023-03-07 10:01:40 -07:00
Jeremy Soller	26b46f19be	Update firmware-setup	2023-03-06 16:21:08 -07:00
Jeremy Soller	eff504109c	Update EDK2	2023-03-06 15:02:08 -07:00
Jeremy Soller	be21f603b9	Update EC	2023-03-06 14:58:09 -07:00
Jeremy Soller	4ce7fd1954	Update firmware-update	2023-03-06 14:58:03 -07:00
Tim Crawford	9efa3f36e3	Update coreboot and EC Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-06 12:02:11 -07:00
Jeremy Soller	d9f3a8ed93	Update coreboot	2023-03-03 10:44:07 -07:00
Jeremy Soller	751c914811	Update EC	2023-03-03 09:58:07 -07:00
Jeremy Soller	a3f105acf6	Update ec	2023-03-03 09:31:19 -07:00
Jeremy Soller	1c8ba80e97	Update coreboot	2023-03-03 09:17:20 -07:00
Jeremy Soller	e70043ca8a	Update coreboot	2023-03-01 09:51:42 -07:00
Jeremy Soller	d69bd4c25d	addw3: add GBE firmware and update coreboot	2023-02-28 14:57:13 -07:00
Jeremy Soller	de333a0b52	Update EC	2023-02-28 12:25:20 -07:00
Jeremy Soller	a185e1c167	Update coreboot	2023-02-28 12:22:09 -07:00
Jeremy Soller	d73f99cf06	Update coreboot	2023-02-27 14:25:54 -07:00
Jeremy Soller	a379a4e446	Update coreboot	2023-02-27 13:44:12 -07:00
Jeremy Soller	c9f99efea0	Update coreboot	2023-02-27 13:01:32 -07:00
Jeremy Soller	57f4e45477	Update coreboot	2023-02-27 12:30:22 -07:00
Jeremy Soller	df3633fc66	Update coreboot	2023-02-27 12:16:35 -07:00
Jeremy Soller	04e309fb5a	Update coreboot	2023-02-27 11:52:25 -07:00
Jeremy Soller	5f72a75115	Update coreboot	2023-02-27 08:47:30 -07:00
Jeremy Soller	d92498355d	Update coreboot	2023-02-25 20:36:48 -07:00
Jeremy Soller	52a416abe5	Update EC	2023-02-24 15:27:16 -07:00
Jeremy Soller	70938f6a4b	Update EC	2023-02-22 21:02:10 -07:00
Jeremy Soller	45391317e5	Update coreboot	2023-02-22 19:07:31 -07:00
Jeremy Soller	a9a38cc709	Update coreboot and ec	2023-02-22 15:49:57 -07:00
Jeremy Soller	b1308d43a4	Update ec	2023-02-22 14:37:03 -07:00
Jeremy Soller	da09a291d7	Update coreboot	2023-02-22 14:32:26 -07:00
Jeremy Soller	2d5d0fdf04	Update coreboot and ec	2023-02-22 14:28:55 -07:00
Jeremy Soller	d6d7131609	Update coreboot	2023-02-22 12:57:12 -07:00
Jeremy Soller	abd244ea96	Update coreboot and ec	2023-02-22 12:41:37 -07:00
Jeremy Soller	41728698ce	Update firmware-update	2023-02-22 11:46:41 -07:00
Jeremy Soller	2dda038952	Use RPL-H FSP for oryp11	2023-02-22 11:31:13 -07:00
Tim Crawford	40f9305ce2	serw13: Fix symlink to FSP Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-22 10:21:11 -07:00
Tim Crawford	3f99789509	gaze18: Symlink FSP, add chip.txt Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-22 10:18:11 -07:00
Tim Crawford	40843fbf53	gaze18: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-22 09:54:22 -07:00
Jeremy Soller	4937a74306	Update coreboot	2023-02-22 08:17:29 -07:00
Jeremy Soller	e00ff92929	Update coreboot and ec	2023-02-22 08:09:34 -07:00
Jeremy Soller	9d7ef8fb3a	Apply model renames to configs and readmes	2023-02-22 08:09:24 -07:00
Jeremy Soller	24ae446ef4	Rename gaze18-3050 to gaze18	2023-02-22 08:06:02 -07:00
Jeremy Soller	403c82cd8e	Rename gaze18-40x0 to addw3	2023-02-22 08:05:47 -07:00
Jeremy Soller	c30161a28a	Rename addp3 to oryp11	2023-02-22 08:05:25 -07:00
Jeremy Soller	94e6d375fa	Rename oryp11 to serw13	2023-02-22 08:05:15 -07:00
Jeremy Soller	5a89066f02	Update coreboot and EC	2023-02-21 20:09:01 -07:00
Jeremy Soller	02b6c688e0	Update coreboot	2023-02-21 15:43:52 -07:00
Jeremy Soller	76299a9043	Update ec	2023-02-21 14:55:28 -07:00
Jeremy Soller	f90becc96f	Disable bootguard and PTT on addp3	2023-02-21 14:03:54 -07:00
Jeremy Soller	b28a954926	Add FSP and configs for addp3	2023-02-21 14:03:39 -07:00
Tim Crawford	c09333e944	Revert "gaze18-3050: Update CSME" This reverts commit `062ff0364b`. The RPL-HX tools were used to regenerate the CSME, but the RPL-P tools need to be used. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-21 13:46:44 -07:00
Jeremy Soller	f8659ec3e5	Add addp3 extract	2023-02-21 13:32:49 -07:00
Tim Crawford	062ff0364b	gaze18-3050: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-21 11:53:17 -07:00
Tim Crawford	ab7600f44d	coreboot: Drop RUN_FSP_GOP selection Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-16 10:37:01 -07:00
Jeremy Soller	20e5a30b8d	Update ec	2023-02-15 19:05:04 -07:00
Jeremy Soller	3c481f5385	Update coreboot	2023-02-15 16:18:47 -07:00
Jeremy Soller	e2e62c413b	Update coreboot	2023-02-13 15:35:36 -07:00
Jeremy Soller	3ee1f1b614	Update coreboot	2023-02-10 12:56:42 -07:00
Jeremy Soller	748ba007e0	Update coreboot	2023-02-10 12:44:32 -07:00
Jeremy Soller	8c761d7aed	Update ec	2023-02-10 12:25:18 -07:00
Jeremy Soller	db73252a07	Update coreboot	2023-02-10 12:23:14 -07:00
Tim Crawford	afe6fc5f73	oryp11: Add ec.config, symlink and use FSP Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-10 11:53:20 -07:00
Jeremy Soller	ba551a077c	Update EC	2023-02-10 10:59:52 -07:00
Jeremy Soller	d2a6191ec0	Update coreboot	2023-02-10 10:47:22 -07:00
Jeremy Soller	9b5cdd2841	Update intel-spi	2023-02-10 10:27:54 -07:00
Jeremy Soller	8913ab4aa8	Update firmware-update	2023-02-10 10:18:49 -07:00
Jeremy Soller	3aebb0423e	Update firmware-update	2023-02-10 10:06:21 -07:00
Jeremy Soller	0977863fef	Update coreboot	2023-02-10 09:39:57 -07:00
Tim Crawford	8e90fec1ea	oryp11: Add config files - Specify chip.txt for external flashing - Copy IntelGopDriver.inf so GOP is used - Copy edk2.config to build with correct configs Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-09 09:22:58 -07:00
Tim Crawford	ef2ddd819a	docs: Add section for smart amp to porting notes Document how to find the Realtek smart amp init data from the proprietary firmware image. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-08 15:00:48 -07:00
Tim Crawford	836cbb0720	oryp11: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-08 13:07:19 -07:00
Tim Crawford	e74b939c4b	Add coreboot configs for oryp11, gaze18-3050 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-08 09:54:08 -07:00
Jeremy Soller	fc2979310b	Update coreboot	2023-02-08 08:28:11 -07:00
Jeremy Soller	02f8ee9934	Update coreboot	2023-02-08 08:15:28 -07:00
Jeremy Soller	6996a4cc89	Add FSP for gaze18-40x0	2023-02-07 15:58:22 -07:00
Jeremy Soller	69e429e2b4	Add chip.txt for gaze18	2023-02-07 15:37:47 -07:00
Jeremy Soller	7d984696d0	Disable bootguard for gaze18	2023-02-07 15:37:39 -07:00
Jeremy Soller	bbbafdea1f	Fix compilation of edk2	2023-02-07 14:34:11 -07:00
Jeremy Soller	00df2028b7	Update coreboot and add gaze18-40x0 configs	2023-02-07 14:33:57 -07:00
Tim Crawford	bd4b768ef2	models: Add oryp11 blobs Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-03 11:22:33 -07:00
Tim Crawford	d5001a6b6f	models: Add oryp11 extract Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-03 11:20:04 -07:00
Jeremy Soller	7775e64b6a	Add gaze18-40x0 extract	2023-02-02 09:29:13 -07:00
Jeremy Soller	5c5ab76c47	Update coreboot-collector	2023-02-02 09:27:59 -07:00
Jeremy Soller	78f21bab79	Update coreboot-collector	2023-02-02 08:49:34 -07:00
Tim Crawford	09c761ca68	models: Add gaze18-3050 dump Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-01 12:07:07 -07:00
Tim Crawford	56994a28fc	modeltool: Update edition, deps Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-01 12:06:10 -07:00