coreboot: Fix USB2 on USB-C for gaze18, serw13

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Update ec
2023-03-22 08:41:26 -06:00 · 2023-03-21 20:35:28 -06:00 · 2023-03-21 20:07:27 -06:00 · 2023-03-21 19:56:40 -06:00 · 2023-03-21 19:52:26 -06:00 · 2023-03-21 13:41:25 -06:00
277 changed files with 166217 additions and 603 deletions
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -10,6 +10,7 @@ assignees: []
 - BIOS version: <!-- `cat /sys/class/dmi/id/bios_version` (e.g.: 2021-09-30_14b8a6e)-->
 - EC version: <!-- This will match the BIOS version unless you flashed it separately. -->
 - OS: <!-- e.g.: Pop!_OS 21.10, Fedora 35, Windows 11 -->
+- Kernel: <!-- `uname -r` (e.g.: 6.0.6-76060006-generic) -->

 <!-- Briefly describe the problem. -->

--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,29 +4,92 @@ Changes are identified by the date of the released firmware including them. If
 you are running System76 Open Firmware, opening the boot menu will show this
 date followed by an underscore and a short git revision.

+## unreleased
+
+- Enabled support for Secure Boot
+- Enabled minimal UI for enforcing Secure Boot and resetting keys
+
+## 2022-11-21
+
+- lemp11: Added workaround to force S0ix entry on suspend
+- tgl-u: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives
+- adl-p: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives
+- adl-p: Fixed ACPI brightness controls on Windows 10 and Linux 6.1
+- adl-p: Disabled SATA DevSlp to fix S0ix entry
+- tgl-u: Disabled SATA DevSlp to fix S0ix entry
+- Updated Rust toolchain to nightly-2022-03-18
+- adl-p: Added workaround to force S0ix entry on suspend
+- adl-p: Fixed case where system gets stuck in S5 due to power loss
+- tgl-u: Fixed case where system gets stuck in S5 due to power loss
+- galp5: Fixed power off failing due to WLAN GPIO
+
+## 2022-10-14
+
+- Fixed smart charger values for all boards
+- Fixed keyboard backlight color with custom values
+- lemp11: Removed RTD3 config for card reader to fix suspend
+
+## 2022-09-26
+
+- oryp8: Fixed brightness controls on Windows
+- oryp10: Added initial release of open firmware with System76 EC
+
+## 2022-09-07
+
+- Updated CSME for TGL-H to 15.0.41.2158
+- Updated CSME for TGL-U to 15.0.41.2158
+- Changed build to use coreboot toolchain for edk2
+- Fixed signal used to detect S0ix
+- Fixed off-by-one for battery charging start/stop thresholds
+
+## 2022-08-03
+
+- Updated coreboot to upstream commit 37bf8c6dd590
+- Updated TGL-U microcode to revision 0xa4 from Intel's public repo
+- Updated TGL-H microcode to revision 0x3e from Intel's public repo
+- Updated ADL microcode to revision 0x41c from Intel's public repo
+- Updated ADL FSP to C.0.69.74 from Intel's public repo
+- Updated CSME for ADL-P to 16.0.15.1810v8 (16.0.15.1829)
+- Fixed uncommon I2C HID initialization failure on boot
+- Fixed smart charger values for all boards
+- galp6: Added initial release of open firmware with System76 EC
+
+## 2022-07-27
+
+- gaze17-3050: Added initial release of open firmware with System76 EC
+- gaze17-3060: Fixed suspend with WD drives
+
+## 2022-07-20
+
+- oryp9: Added initial release of open firmware with System76 EC
+
+## 2022-07-13
+
+- darp8: Fixed power off under load while on battery power
+
 ## 2022-07-05

- lemp11: Fix power off under load while on battery power
-
-## 2022-06-29
-
- lemp11: Release of open firmare with System76 EC
+- lemp11: Added initial release of open firmare with System76 EC

 ## 2022-06-23

- darp8: Release of open firmware with System76 EC
+- darp8: Added initial release of open firmware with System76 EC

 ## 2022-06-07

 - Fixed building for QEMU
 - Updated coreboot to upstream commit 670572ff6a
+- Fixed NVIDIA subsystem ID being lost on suspend
+- TGL: Fixed Device Manager warning about missing drivers for Tiger Lake IPC
+  Controller and System76 EC ACPI devices
 - Improved NVIDIA Optimus support
- gaze17-3060-b: Release of open firmware with System76 EC
+- tgl-u: Fixed suspend with certain drives
+- gaze17-3060-b: Added initial release of open firmware with System76 EC

 ## 2022-02-15

- Update ME for all supported systems
- Ensure that system powers off S5 plane if it fails to reach S0
+- Updated ME for all supported systems
+- Ensured that system powers off S5 plane if it fails to reach S0

 ## 2022-01-06

@@ -34,7 +97,7 @@ date followed by an underscore and a short git revision.
 - Enabled coreboot measured boot
 - Updated Rust toolchain to nightly-2021-06-15
 - Updated coreboot to 4.15
- Updated EDK2 to edk2-stabke202108
+- Updated EDK2 to edk2-stable202108
 - Updated TGL-U microcode blobs to revision 0x9a
 - Updated TGL-H microcode blobs to revision 0x3c
 - Updated all other boards to use microcode blobs from Intel's public repo
@@ -43,23 +106,23 @@ date followed by an underscore and a short git revision.

 ## 2021-09-30

- gaze16: Do not require unplugging the AC adapter after flashing
- gaze16: Fix using USB 2.0 devices in Type-C port
+- gaze16: Removed need to unplug the AC adapter after flashing
+- gaze16: Fixed using USB 2.0 devices in Type-C port

 ## 2021-09-23

- oryp8: Release of open firmware with System76 EC
- gaze16: Fix input current on 3050 variant
- gaze16: Fix power limit when booting on battery
- gaze16: Fix touchpad on newer Linux kernel and Windows
- Fix brightness controls on TGL platforms
- Fix PCIe subsystem IDs on TGL platforms
- Fix spurious clearing of boot options on Windows
- Provide battery cycle count
+- oryp8: Added initial release of open firmware with System76 EC
+- gaze16: Fixed input current on 3050 variant
+- gaze16: Fixed power limit when booting on battery
+- gaze16: Fixed touchpad on newer Linux kernel and Windows
+- Fixed brightness controls on TGL platforms
+- Fixed PCIe subsystem IDs on TGL platforms
+- Fixed spurious clearing of boot options on Windows
+- Added battery cycle count

 ## 2021-07-20

- gaze16: Release of open firmware with System76 EC
+- gaze16: Added initial release of open firmware with System76 EC
 - Improved thermals by syncing CPU and GPU fans
 - Enabled fan speed interpolation
 - Fixed ACPI timeout on S3 resume if a key is held
@@ -69,142 +132,148 @@ date followed by an underscore and a short git revision.

 ## 2021-04-07

- darp7, galp5, lemp10: Update microcode
+- tgl-u: Updated microcode

 ## 2021-04-02

- Fix fan max keeping fan on when in S0iX
- Report all keys as released when lid is closed
+- Fixed fan max keeping fan on when in S0iX
+- Changed keyboard behavior to report all keys as released when lid is closed

 ## 2021-03-19

- gaze15: Release of open firmware with System76 EC
- gaze15: Add ELAN touchpad settings
+- gaze15: Added initial release of open firmware with System76 EC
+- gaze15: Added ELAN touchpad settings

 ## 2021-03-16

- oryp6, oryp7: Fix buzzing at lowest fan speed
+- oryp6: Fixed buzzing at lowest fan speed
+- oryp7: Fixed buzzing at lowest fan speed

 ## 2021-03-11

- lemp9: Fix backlight ACPI issues and TPM interrupt
+- lemp9: Fixed backlight ACPI issues and TPM interrupt

 ## 2021-03-08

- oryp6, oryp7: Improved fan curve
+- oryp6: Improved fan curve
+- oryp7: Improved fan curve

 ## 2021-03-03

- oryp7: Release of open firmware with System76 EC
+- oryp7: Added initial release of open firmware with System76 EC

 ## 2021-02-15

- darp7, galp5: Raise HDMI data rate to support 4K@60Hz
+- darp7: Increased HDMI data rate to support 4K@60Hz
+- galp5: Increased HDMI data rate to support 4K@60Hz

 ## 2021-02-09

- galp5: Fix GPU driver crash in compute graphics mode
+- galp5: Fixed GPU driver crash in compute graphics mode

 ## 2021-02-05

- darp7: Fix keyboard scanning glitches
+- darp7: Fixed keyboard scanning glitches

 ## 2021-01-21

- darp7: Release of open firmware with System76 EC
+- darp7: Added initial release of open firmware with System76 EC

 ## 2021-01-19

- Update boot options on device hotplug
- Add fan toggle key (Fn+1)
- Clear NVRAM when CMOS battery is removed
- galp5, lemp10: Fix NVRAM compacting
+- Added behavior to update boot options on device hotplug
+- Added fan toggle key (Fn+1)
+- Added behavior to clear NVRAM when CMOS battery is removed
+- galp5: Fixed NVRAM compacting
+- lemp10: Fixed NVRAM compacting

 ## 2021-12-15

- galp5: Support variant with NVIDIA GPU
+- galp5: Added support for variant with NVIDIA GPU

 ## 2020-12-04

- galp5, lemp10: Release of open firmware with System76 EC
+- galp5: Added initial release of open firmware with System76 EC
+- lemp10: Added initial release of open firmware with System76 EC

 ## 2020-10-19

- Support customizing keyboard at runtime
- Add battery charging thresholds
- oryp6: Fix smart charger values
- Prevent wake when lid is closed
+- Added support for customizing keyboard at runtime
+- Added battery charging thresholds
+- oryp6: Fixed smart charger values
+- Prevented wake when lid is closed

 ## 2020-09-22

- darp6: Release of open firmware with System76 EC
- darp6: Fix allocation of memory type range registers
+- darp6: Added initial release of open firmware with System76 EC
+- darp6: Fixed allocation of memory type range registers

 ## 2020-09-17

- Enable Wake-on-Lan (on supported models)
- Add ACPI thermal interface
- Fix ESXi keyboard issue
+- Enabled Wake-on-Lan (on supported models)
+- Added ACPI thermal interface
+- Fixed ESXi keyboard issue

 ## 2020-09-03

- addw2: Release of open firmware with System76 EC
+- addw2: Added initial release of open firmware with System76 EC

 ## 2020-08-24

- bonw14: Release of open firmware with System76 EC
+- bonw14: Added initial release of open firmware with System76 EC

 ## 2020-08-13

- Add UEFI TPM2 support
+- Added UEFI TPM2 support

 ## 2020-08-06

- Enable ACPI backlight
- Add firmware configuration information
+- Enabled ACPI backlight
+- Added firmware configuration information

 ## 2020-07-06

- oryp6: Release of open firmware with System76 EC
+- oryp6: Added initial release of open firmware with System76 EC

 ## 2020-05-20

- Warn if no bootable media is found
+- Added warning if no bootable media is found

 ## 2020-05-15

- Enable i2c-hid touchpad interface
+- Enabled i2c-hid touchpad interface

 ## 2020-05-07

- Fix ghost key debouncing
+- Fixed ghost key debouncing

 ## 2020-05-04

- Improve ghost key handling and reduce key debounce
+- Improved ghost key handling and reduce key debounce

 ## 2020-04-23

- Fix duplicate release of key after release of function key
+- Fixed duplicate release of key after release of function key

 ## 2020-04-18

- lemp9: Update fan curve
+- lemp9: Updated fan curve

 ## 2020-04-09

- lemp9: Release of open firmware with System76 EC
+- lemp9: Added initial release of open firmware with System76 EC

 ## 2020-02-05

- Use descriptive device names
- Only show bootable devices
+- Changed boot manager to use descriptive device names
+- Changed boot manager to only show bootable devices

 ## 2020-01-13

- Fix NVIDIA eGPU issues
- Iimprove boot order editing
+- Fixed NVIDIA eGPU issues
+- Improved boot order editing

 ## 2019-10-31

- darp6, galp4: Release of open firmware with proprietary EC
+- darp6: Added intial release of open firmware with proprietary EC
+- galp4: Added intial release of open firmware with proprietary EC
--- a/2
+++ b/2
--- a/README.md
+++ b/README.md
@@ -12,17 +12,24 @@ manager:
 - bonw14
 - darp6
 - darp7
+- darp8
 - galp4
 - galp5
+- galp6
 - gaze15
 - gaze16-3050
 - gaze16-3060
 - gaze16-3060-b
+- gaze17-3050
+- gaze17-3060-b
 - lemp9
 - lemp10
+- lemp11
 - oryp6
 - oryp7
 - oryp8
+- oryp9
+- oryp10

 Other models may be in development or available without support, and can be
 seen in the `models/` directory.
--- a/apps/firmware-setup
+++ b/apps/firmware-setup
--- a/apps/firmware-update
+++ b/apps/firmware-update
--- a/2
+++ b/2
--- a/docs/adding-a-new-board.md
+++ b/docs/adding-a-new-board.md
@@ -61,12 +61,16 @@ If the microcode blobs from coreboot will not be used, then `microcode.rom`
 must be generated for the correct CPU set from the private [intel-microcode]
 repo.

+Other things that should be dumped before porting/flashing are:
+
+- The kernel log (`dmesg`)
+- DMI info (`dmidecode`)
+- ACPI tables (`acpidump -b`)
+
 ## Porting coreboot

 To port coreboot to a new board, see the coreboot documentation.

- [TAS5825M] smart amp
-
 Once coreboot is ported, add its configuration.

 ```
@@ -78,6 +82,19 @@ cp coreboot/.config models/<model>/coreboot.config
 `generate.sh` does not create `devicetree.cb`. Some values for this file can be
 produced using the `devicetree.py` script.

+### Smart amp
+
+Boards may have a smart amp, which must be configured for speaker output to
+work.
+
+The initialization data for Realtek smart amps can be dumped from the module
+that does the codec init in proprietary firmware. The correct module can be
+found using UEFITool by searching for the vendor/device ID of the codec, such
+as "10ec1220" for the ALC1220. This is the start of the `cim_verb_data` array
+in coreboot.
+
+For info on the TI TAS5825M smart amp, see the [smart-amp] repo.
+
 ## Configuring Intel CSME

 The CSME image may need to be regenerated. Common changes that may be required
@@ -100,4 +117,4 @@ READMEs.
 [external-programmer]: ./flashing.md#external-programmer
 [intel-microcode]: https://github.com/system76/intel-microcode
 [mega2560]: https://github.com/system76/ec/blob/master/doc/mega2560.md
-[TAS5825M]: https://github.com/system76/smart-amp
+[smart-amp]: https://github.com/system76/smart-amp
--- a/docs/flashing.md
+++ b/docs/flashing.md
@@ -31,8 +31,8 @@ Use one of these methods for first-time flashing or flashing a bricked system.
 ### Identifying the BIOS chip

 The packaging and protocol can be determined by `board_info.txt` in coreboot.
-Laptops use a SOIC-8 package for the SPI flash ROM. Pin 1 is marked by a small
-dot indent and a white paint mark. The silkscreen may also indicate pin 1.
+Pin 1 is marked by a small dot indent and a white paint mark. The silkscreen
+may also indicate pin 1.

 ### CH341A USB programmer - slower, but easier to set up

--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/libs/intel-spi
+++ b/libs/intel-spi
--- a/models/README.md
+++ b/models/README.md
@@ -4,7 +4,9 @@

 - [addw1](./addw1) - System76 Adder Workstation (addw1)
 - [addw2](./addw2) - System76 Adder WS (addw2)
+- [addw3](./addw3) - System76 Adder WS (addw3)
 - [bonw14](./bonw14) - System76 Bonobo WS (bonw14)
+- [bonw15](./bonw15) - System76 Bonobo WS (bonw15)
 - [darp5](./darp5) - System76 Darter Pro (darp5)
 - [darp6](./darp6) - System76 Darter Pro (darp6)
 - [darp7](./darp7) - System76 Darter Pro (darp7)
@@ -15,6 +17,7 @@
 - [galp3-c](./galp3-c) - System76 Galago Pro (galp3-c)
 - [galp4](./galp4) - System76 Galago Pro (galp4)
 - [galp5](./galp5) - System76 Galago Pro (galp5)
+- [galp6](./galp6) - System76 Galago Pro (galp6)
 - [gaze14_1650](./gaze14_1650) - System76 Gazelle (gaze14)
 - [gaze14_1660ti](./gaze14_1660ti) - System76 Gazelle (gaze14)
 - [gaze15](./gaze15) - System76 Gazelle (gaze15)
@@ -23,12 +26,16 @@
 - [gaze16-3060-b](./gaze16-3060-b) - System76 Gazelle (gaze16)
 - [gaze17-3050](./gaze17-3050) - System76 Gazelle (gaze17)
 - [gaze17-3060-b](./gaze17-3060-b) - System76 Gazelle (gaze17-3060-b)
+- [gaze18](./gaze18) - System76 Gazelle (gaze18)
 - [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
 - [lemp11](./lemp11) - System76 Lemur Pro (lemp11)
 - [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
+- [oryp10](./oryp10) - System76 Oryx Pro (oryp10)
+- [oryp11](./oryp11) - System76 Oryx Pro (oryp11)
 - [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
 - [oryp6](./oryp6) - System76 Oryx Pro (oryp6)
 - [oryp7](./oryp7) - System76 Oryx Pro (oryp7)
 - [oryp8](./oryp8) - System76 Oryx Pro (oryp8)
+- [oryp9](./oryp9) - System76 Oryx Pro (oryp9)
 - [qemu](./qemu) - QEMU (Virtualization)
- [thelio-b1](./thelio-b1) - System76 Thelio (thelio-b1)
+- [serw13](./serw13) - System76 Serval WS (serw13)
--- a/models/addw1/edk2.config
+++ b/models/addw1/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/addw2/edk2.config
+++ b/models/addw2/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/addw3/AlderLakeFspBinPkg/AlderLakeFspBinPkg.dec
+++ b/models/addw3/AlderLakeFspBinPkg/AlderLakeFspBinPkg.dec
--- a/models/addw3/AlderLakeFspBinPkg/Fsp.bsf
+++ b/models/addw3/AlderLakeFspBinPkg/Fsp.bsf
--- a/models/addw3/AlderLakeFspBinPkg/Fsp.fd
+++ b/models/addw3/AlderLakeFspBinPkg/Fsp.fd
--- a/models/addw3/AlderLakeFspBinPkg/FspPkgPcdShare.dsc
+++ b/models/addw3/AlderLakeFspBinPkg/FspPkgPcdShare.dsc
--- a/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfo.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfo.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfoHob.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspInfoHob.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspUpd.h
@@ -1,6 +1,6 @@
 /** @file

-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>

 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspmUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file

-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>

 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -310,7 +310,7 @@ typedef struct {

 /** Offset 0x0177
 **/
-  UINT8                       UnusedUpdSpace0;
+  UINT8                       Rsvd00;

 /** Offset 0x0178 - Tseg Size
  Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
@@ -407,11 +407,17 @@ typedef struct {
 **/
  UINT8                       PchHdaAudioLinkDmicClockSelect[2];

-/** Offset 0x019A - PchPreMemRsvd
+/** Offset 0x019A - Disable Tccold Handshake
+  Disable Tccold Handshake. <b>0: Do Nothing;</b> 1: Disable
+  $EN_DIS
+**/
+  UINT8                       DisableDynamicTccoldHandshake;
+
+/** Offset 0x019B - PchPreMemRsvd
  Reserved for PCH Pre-Mem Reserved
  $EN_DIS
 **/
-  UINT8                       PchPreMemRsvd[5];
+  UINT8                       PchPreMemRsvd[4];

 /** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table
  0=Disable/Clear, 1=Enable/Set
@@ -427,7 +433,7 @@ typedef struct {

 /** Offset 0x01A1
 **/
-  UINT8                       UnusedUpdSpace1[3];
+  UINT8                       Rsvd01[3];

 /** Offset 0x01A4 - Base addresses for VT-d function MMIO access
  Base addresses for VT-d MMIO access per VT-d engine
@@ -607,7 +613,7 @@ typedef struct {

 /** Offset 0x01E3
 **/
-  UINT8                       UnusedUpdSpace2;
+  UINT8                       Rsvd02;

 /** Offset 0x01E4 - Memory Voltage
  DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
@@ -636,7 +642,7 @@ typedef struct {

 /** Offset 0x01E9
 **/
-  UINT8                       UnusedUpdSpace3;
+  UINT8                       Rsvd03;

 /** Offset 0x01EA - tFAW
  Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected
@@ -658,7 +664,7 @@ typedef struct {

 /** Offset 0x01EF
 **/
-  UINT8                       UnusedUpdSpace4;
+  UINT8                       Rsvd04;

 /** Offset 0x01F0 - tREFI
  Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
@@ -811,9 +817,15 @@ typedef struct {
 **/
  UINT8                       PsmiRegionSize;

-/** Offset 0x0221
+/** Offset 0x0221 - Enable Program PSF0 Grant Count Reload value
+  Enable/disable Program PSF0 Grant Count Reload value
+  $EN_DIS
 **/
-  UINT8                       UnusedUpdSpace5[3];
+  UINT8                       GrantCount;
+
+/** Offset 0x0222
+**/
+  UINT8                       Rsvd05[2];

 /** Offset 0x0224 - Temporary MMIO address for GMADR
  Obsolete field now and it has been extended to 64 bit address, used GmAdr64
@@ -1055,7 +1067,7 @@ typedef struct {

 /** Offset 0x0289
 **/
-  UINT8                       UnusedUpdSpace6[7];
+  UINT8                       Rsvd06[7];

 /** Offset 0x0290 - Temporary MMIO address for GMADR
  The reference code will use this as Temporary MMIO address space to access GMADR
@@ -1081,7 +1093,7 @@ typedef struct {

 /** Offset 0x029B
 **/
-  UINT8                       UnusedUpdSpace7;
+  UINT8                       Rsvd07;

 /** Offset 0x029C - SA/Uncore Voltage Override
  The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override
@@ -1118,7 +1130,7 @@ typedef struct {

 /** Offset 0x02A3
 **/
-  UINT8                       UnusedUpdSpace8;
+  UINT8                       Rsvd08;

 /** Offset 0x02A4 - Memory VDDQ Voltage
  DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts
@@ -1165,11 +1177,18 @@ typedef struct {
 **/
  UINT8                       RealtimeMemoryFrequency;

-/** Offset 0x02B0 - SaPreMemProductionRsvd
+/** Offset 0x02B0 - OC Safe Mode
+  0: Disabled, 1(Default): Enabled. Ignored unless SpdProfileSelected is an XMP Profile.
+  If enabled, MRC will use less aggressive controls when training memory.
+  $EN_DIS
+**/
+  UINT8                       OCSafeMode;
+
+/** Offset 0x02B1 - SaPreMemProductionRsvd
  Reserved for SA Pre-Mem Production
  $EN_DIS
 **/
-  UINT8                       SaPreMemProductionRsvd[97];
+  UINT8                       SaPreMemProductionRsvd[96];

 /** Offset 0x0311 - Enable Gt CLOS
  0(Default)=Disable, 1=Enable
@@ -1594,7 +1613,7 @@ typedef struct {

 /** Offset 0x03D1
 **/
-  UINT8                       UnusedUpdSpace9;
+  UINT8                       Rsvd09;

 /** Offset 0x03D2 - Ring voltage override
  The ring voltage override which is applied to the entire range of cpu ring frequencies.
@@ -1646,7 +1665,7 @@ typedef struct {

 /** Offset 0x03DD
 **/
-  UINT8                       UnusedUpdSpace10;
+  UINT8                       Rsvd10;

 /** Offset 0x03DE - Atom L2 Voltage Override
  The atom L2 voltage override which is applied to the entire range of atom L2 frequencies.
@@ -1692,7 +1711,7 @@ typedef struct {
  UINT8                       GtCepEnable;

 /** Offset 0x03F2 - Enable CPU DLVR bypass mode support
-  Control for enabling/disabling CPU DLVR bypass mode). <b>0: Disable</b>; 1: Enable
+  DEPRECATED
  $EN_DIS
 **/
  UINT8                       DlvrBypassModeEnable;
@@ -1715,7 +1734,7 @@ typedef struct {

 /** Offset 0x03F5
 **/
-  UINT8                       UnusedUpdSpace11[1];
+  UINT8                       Rsvd11[1];

 /** Offset 0x03F6 - Core VF Point Offset
  Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -1847,7 +1866,7 @@ typedef struct {

 /** Offset 0x049D
 **/
-  UINT8                       UnusedUpdSpace12[3];
+  UINT8                       Rsvd12[3];

 /** Offset 0x04A0 - CPU BCLK OC Frequency
  CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
@@ -1905,7 +1924,7 @@ typedef struct {

 /** Offset 0x04B3
 **/
-  UINT8                       UnusedUpdSpace13;
+  UINT8                       Rsvd13;

 /** Offset 0x04B4 - GT ICCMAX
  GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
@@ -1966,7 +1985,7 @@ typedef struct {

 /** Offset 0x04BD
 **/
-  UINT8                       UnusedUpdSpace14[3];
+  UINT8                       Rsvd14[3];

 /** Offset 0x04C0 - Short term Power Limit value for custom cTDP level 1
  Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
@@ -1981,11 +2000,18 @@ typedef struct {
 **/
  UINT8                       Etvb;

-/** Offset 0x04C5 - ReservedCpuPreMem
+/** Offset 0x04C5 - UnderVolt Protection
+  When UnderVolt Protection is enabled, user will be not be able to program under
+  voltage in OS runtime. 0: Disabled; <b>1: Enabled</b>
+  $EN_DIS
+**/
+  UINT8                       UnderVoltProtection;
+
+/** Offset 0x04C6 - ReservedCpuPreMem
  Reserved for Cpu Pre-Mem
  $EN_DIS
 **/
-  UINT8                       ReservedCpuPreMem[7];
+  UINT8                       ReservedCpuPreMem[6];

 /** Offset 0x04CC - BiosGuard
  Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -2005,7 +2031,7 @@ typedef struct {

 /** Offset 0x04CF
 **/
-  UINT8                       UnusedUpdSpace15;
+  UINT8                       Rsvd15;

 /** Offset 0x04D0 - PrmrrSize
  Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2258,7 +2284,7 @@ typedef struct {

 /** Offset 0x0745
 **/
-  UINT8                       UnusedUpdSpace16;
+  UINT8                       Rsvd16;

 /** Offset 0x0746 - SMBUS Base Address
  SMBUS Base Address (IO space).
@@ -2292,7 +2318,7 @@ typedef struct {

 /** Offset 0x0789
 **/
-  UINT8                       UnusedUpdSpace17[3];
+  UINT8                       Rsvd17[3];

 /** Offset 0x078C - Clk Req GPIO Pin
  Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values.
@@ -2364,7 +2390,7 @@ typedef struct {

 /** Offset 0x07F5
 **/
-  UINT8                       UnusedUpdSpace18[3];
+  UINT8                       Rsvd18[3];

 /** Offset 0x07F8 - DMIC<N> Data Pin Muxing
  Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -2426,7 +2452,7 @@ typedef struct {

 /** Offset 0x0811
 **/
-  UINT8                       UnusedUpdSpace19[3];
+  UINT8                       Rsvd19[3];

 /** Offset 0x0814 - Serial Io Uart Debug BaudRate
  Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@@ -2454,7 +2480,7 @@ typedef struct {

 /** Offset 0x081B
 **/
-  UINT8                       UnusedUpdSpace20;
+  UINT8                       Rsvd20;

 /** Offset 0x081C - Serial Io Uart Debug Mmio Base
  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
@@ -3317,7 +3343,7 @@ typedef struct {

 /** Offset 0x08BB
 **/
-  UINT8                       UnusedUpdSpace21;
+  UINT8                       Rsvd21;

 /** Offset 0x08BC - Post Code Output Port
  This option configures Post Code Output Port
@@ -3344,7 +3370,7 @@ typedef struct {

 /** Offset 0x08C1
 **/
-  UINT8                       UnusedUpdSpace22[3];
+  UINT8                       Rsvd22[3];

 /** Offset 0x08C4 - BCLK RFI Frequency
  Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@@ -3525,7 +3551,7 @@ typedef struct {

 /** Offset 0x08F1
 **/
-  UINT8                       UnusedUpdSpace23[3];
+  UINT8                       Rsvd23[3];

 /** Offset 0x08F4 - PMR Size
  Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -3539,7 +3565,7 @@ typedef struct {

 /** Offset 0x08F9
 **/
-  UINT8                       UnusedUpdSpace24;
+  UINT8                       Rsvd24;

 /** Offset 0x08FA - Delta T12 Power Cycle Delay required in ms
  Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate
@@ -3560,15 +3586,21 @@ typedef struct {
 **/
  UINT8                       OemT12DelayOverride;

-/** Offset 0x08FE - SaPreMemTestRsvd
+/** Offset 0x08FE - DQS Offset Adjust Training
+  Enable/Disable DQS Offset Adjust Training
+  $EN_DIS
+**/
+  UINT8                       DQSOFFSETADJUST;
+
+/** Offset 0x08FF - SaPreMemTestRsvd
  Reserved for SA Pre-Mem Test
  $EN_DIS
 **/
-  UINT8                       SaPreMemTestRsvd[89];
+  UINT8                       SaPreMemTestRsvd[88];

 /** Offset 0x0957
 **/
-  UINT8                       UnusedUpdSpace25;
+  UINT8                       Rsvd25;

 /** Offset 0x0958 - TotalFlashSize
  Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@@ -3652,7 +3684,7 @@ typedef struct {

 /** Offset 0x0972
 **/
-  UINT8                       UnusedUpdSpace26[2];
+  UINT8                       Rsvd26[2];

 /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
  Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
@@ -3689,7 +3721,7 @@ typedef struct {

 /** Offset 0x0A97
 **/
-  UINT8                       UnusedUpdSpace27;
+  UINT8                       Rsvd27;

 /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
  Select RX pin muxing for SerialIo UART used for debug
@@ -3751,7 +3783,7 @@ typedef struct {

 /** Offset 0x0AB2
 **/
-  UINT8                       UnusedUpdSpace28[6];
+  UINT8                       Rsvd28[6];

 /** Offset 0x0AB8 - IbeccErrInjAddress
  Address to match against for ECC error injection
@@ -3780,7 +3812,7 @@ typedef struct {

 /** Offset 0x0AD5
 **/
-  UINT8                       UnusedUpdSpace29[3];
+  UINT8                       Rsvd29[3];

 /** Offset 0x0AD8 - Debug Value
  Debug Value
@@ -3843,7 +3875,7 @@ typedef struct {

 /** Offset 0x0AEB
 **/
-  UINT8                       UnusedUpdSpace30[5];
+  UINT8                       Rsvd30[5];

 /** Offset 0x0AF0 - EccErrInjAddress
  Address to match against for ECC error injection
@@ -3911,7 +3943,7 @@ typedef struct {

 /** Offset 0x0B0D
 **/
-  UINT8                       UnusedUpdSpace31;
+  UINT8                       Rsvd31;

 /** Offset 0x0B0E - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB
  Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
@@ -3983,13 +4015,31 @@ typedef struct {
 **/
  UINT8                       OverloadSAM;

-/** Offset 0x0B2D
+/** Offset 0x0B2D - Time Measure
+  Time Measure: 0(Default)=Disable, 1=Enable
+  $EN_DIS
 **/
-  UINT8                       UnusedUpdSpace32[5];
+  UINT8                       MrcTimeMeasure;

-/** Offset 0x0B32
+/** Offset 0x0B2E -  Dfe Gain
+   Dfe Gain. 0:0 default value, 1: 1, 2: 2, 3: 3, 9: -1, 10: -2, 11: -3
+  0:0, 1:1, 2:2, 3:3, 9:-1, 10:-2, 11:-3
 **/
-  UINT8                       ReservedFspmUpd2[6];
+  UINT8                       DfeGain;
+
+/** Offset 0x0B2F - CsPiStartHighinEct
+  Cs Pi Start with High value in Ect: 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       CsPiStartHighinEct;
+
+/** Offset 0x0B30
+**/
+  UINT8                       Rsvd32[4];
+
+/** Offset 0x0B34
+**/
+  UINT8                       ReservedFspmUpd2[4];
 } FSP_M_CONFIG;

 /** Fsp M UPD Configuration
@@ -4010,7 +4060,7 @@ typedef struct {

 /** Offset 0x0B38
 **/
-  UINT8                       UnusedUpdSpace33[6];
+  UINT8                       Rsvd33[6];

 /** Offset 0x0B3E
 **/
--- a/models/addw3/AlderLakeFspBinPkg/Include/FspsUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file

-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>

 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -125,7 +125,7 @@ typedef struct {

 /** Offset 0x0056
 **/
-  UINT8                       UnusedUpdSpace0[2];
+  UINT8                       Rsvd00[2];

 /** Offset 0x0058 - MicrocodeRegionBase
  Memory Base of Microcode Updates
@@ -163,7 +163,7 @@ typedef struct {

 /** Offset 0x0072
 **/
-  UINT8                       UnusedUpdSpace1[2];
+  UINT8                       Rsvd01[2];

 /** Offset 0x0074 - SATA DEVSLP GPIO Pin
  Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values.
@@ -190,7 +190,7 @@ typedef struct {

 /** Offset 0x00AF
 **/
-  UINT8                       UnusedUpdSpace2;
+  UINT8                       Rsvd02;

 /** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
  The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
@@ -238,7 +238,7 @@ typedef struct {

 /** Offset 0x00C2
 **/
-  UINT8                       UnusedUpdSpace3[2];
+  UINT8                       Rsvd03[2];

 /** Offset 0x00C4 - PCH HDA Verb Table Pointer
  Pointer to Array of pointers to Verb Table.
@@ -306,7 +306,7 @@ typedef struct {

 /** Offset 0x010A
 **/
-  UINT8                       UnusedUpdSpace4[2];
+  UINT8                       Rsvd04[2];

 /** Offset 0x010C - Default BaudRate for each Serial IO UART
  Set default BaudRate Supported from 0 - default to 6000000
@@ -346,7 +346,7 @@ typedef struct {

 /** Offset 0x0152
 **/
-  UINT8                       UnusedUpdSpace5[2];
+  UINT8                       Rsvd05[2];

 /** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
  Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
@@ -661,7 +661,7 @@ typedef struct {

 /** Offset 0x038F
 **/
-  UINT8                       UnusedUpdSpace6;
+  UINT8                       Rsvd06;

 /** Offset 0x0390 - PCH TSN MAC Address High Bits
  Set TSN MAC Address High.
@@ -697,7 +697,7 @@ typedef struct {

 /** Offset 0x03ED
 **/
-  UINT8                       UnusedUpdSpace7[3];
+  UINT8                       Rsvd07[3];

 /** Offset 0x03F0 - Power button debounce configuration
  Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
@@ -750,7 +750,7 @@ typedef struct {

 /** Offset 0x03FD
 **/
-  UINT8                       UnusedUpdSpace8;
+  UINT8                       Rsvd08;

 /** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states
  Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
@@ -812,7 +812,7 @@ typedef struct {

 /** Offset 0x040B
 **/
-  UINT8                       UnusedUpdSpace9;
+  UINT8                       Rsvd09[1];

 /** Offset 0x040C - Pointer of ChipsetInit Binary
  ChipsetInit Binary Pointer.
@@ -830,9 +830,11 @@ typedef struct {
 **/
  UINT8                       PchFivrDynPm;

-/** Offset 0x0415
+/** Offset 0x0415 - FIVR VCCST ICCMax Control
+  Enable/Disable FIVR VCCST ICCMax Control.
+  $EN_DIS
 **/
-  UINT8                       UnusedUpdSpace10;
+  UINT8                       PchFivrVccstIccMaxControl;

 /** Offset 0x0416 - External V1P05 Icc Max Value
  Granularity of this setting is 1mA and maximal possible value is 500mA
@@ -859,7 +861,7 @@ typedef struct {

 /** Offset 0x041D
 **/
-  UINT8                       UnusedUpdSpace11[3];
+  UINT8                       Rsvd10[3];

 /** Offset 0x0420 - Extended BIOS Direct Read Decode Range base
  Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
@@ -879,7 +881,7 @@ typedef struct {

 /** Offset 0x0429
 **/
-  UINT8                       UnusedUpdSpace12[3];
+  UINT8                       Rsvd11[3];

 /** Offset 0x042C - Pointer of SYNPS PHY Binary
  ChipsetInit Binary Pointer.
@@ -1020,7 +1022,7 @@ typedef struct {

 /** Offset 0x0455
 **/
-  UINT8                       UnusedUpdSpace13;
+  UINT8                       Rsvd12;

 /** Offset 0x0456 - OS Timer
  16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
@@ -1056,7 +1058,7 @@ typedef struct {

 /** Offset 0x04AF
 **/
-  UINT8                       UnusedUpdSpace14[1];
+  UINT8                       Rsvd13[1];

 /** Offset 0x04B0 - PCIE RP Detect Timeout Ms
  The number of milliseconds within 0~65535 in reference code will wait for link to
@@ -1244,7 +1246,7 @@ typedef struct {

 /** Offset 0x058D
 **/
-  UINT8                       UnusedUpdSpace15[3];
+  UINT8                       Rsvd14[3];

 /** Offset 0x0590 - VMD Variable
  VMD Variable Pointer.
@@ -1326,7 +1328,7 @@ typedef struct {

 /** Offset 0x05B1
 **/
-  UINT8                       UnusedUpdSpace16[1];
+  UINT8                       Rsvd15[1];

 /** Offset 0x05B2 - ITBT DMA LTR
  TCSS DMA1, DMA2 LTR value
@@ -1362,7 +1364,7 @@ typedef struct {

 /** Offset 0x05C7
 **/
-  UINT8                       UnusedUpdSpace17[1];
+  UINT8                       Rsvd16[1];

 /** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
  Latency Tolerance Reporting, Snoop Latency Override Value.
@@ -1414,7 +1416,7 @@ typedef struct {

 /** Offset 0x05F3
 **/
-  UINT8                       UnusedUpdSpace18[1];
+  UINT8                       Rsvd17[1];

 /** Offset 0x05F4 - Imon slope correction
  PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
@@ -1441,7 +1443,7 @@ typedef struct {

 /** Offset 0x0612
 **/
-  UINT8                       UnusedUpdSpace19[2];
+  UINT8                       Rsvd18[2];

 /** Offset 0x0614 - Thermal Design Current time window
  PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
@@ -1490,7 +1492,7 @@ typedef struct {

 /** Offset 0x063B
 **/
-  UINT8                       UnusedUpdSpace20[1];
+  UINT8                       Rsvd19[1];

 /** Offset 0x063C - Thermal Design Current current limit
  PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
@@ -1559,7 +1561,7 @@ typedef struct {

 /** Offset 0x0687
 **/
-  UINT8                       UnusedUpdSpace21;
+  UINT8                       Rsvd20;

 /** Offset 0x0688 - CpuBistData
  Pointer CPU BIST Data
@@ -1596,7 +1598,7 @@ typedef struct {

 /** Offset 0x0693
 **/
-  UINT8                       UnusedUpdSpace22[1];
+  UINT8                       Rsvd21[1];

 /** Offset 0x0694 - VR Voltage Limit
  PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
@@ -1615,12 +1617,12 @@ typedef struct {
  UINT8                       EnableVsysCritical;

 /** Offset 0x06A1 - Vsys Full Scale
-  Vsys Full Scale, Range is 0-255
+  DEPRECATED
 **/
  UINT8                       VsysFullScale;

 /** Offset 0x06A2 - Vsys Critical Threshold
-  Vsys Critical Threshold, Range is 0-255
+  DEPRECATED
 **/
  UINT8                       VsysCriticalThreshold;

@@ -1663,10 +1665,11 @@ typedef struct {

 /** Offset 0x06AB
 **/
-  UINT8                       UnusedUpdSpace23[1];
+  UINT8                       Rsvd22[1];

 /** Offset 0x06AC - VR Fast Vmode ICC Limit support
-  PCODE MMIO Mailbox: VR Fast Vmode ICC Limit support. 0-255A in 1/4 A units. 400 = 100A
+  PCODE MMIO Mailbox: The non-zero value will only be effective by setting the corresponding
+  EnableFastVmode to 1. 0-510A in 1/4 A units. 400 = 100A
 **/
  UINT16                      IccLimit[5];

@@ -1703,7 +1706,7 @@ typedef struct {

 /** Offset 0x06BD
 **/
-  UINT8                       UnusedUpdSpace24;
+  UINT8                       Rsvd23;

 /** Offset 0x06BE - Min Voltage for C8
  PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
@@ -1748,11 +1751,38 @@ typedef struct {
 **/
  UINT8                       VrPowerDeliveryDesign;

-/** Offset 0x06CB - ReservedCpuPostMemProduction
+/** Offset 0x06CB - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+  Enable/Disable VR FastVmode; The value will only be effective by enabling the corresponding
+  CEP.<b>0: Disable</b>; 1: Enable.For all VR by domain
+  0: Disable, 1: Enable
+**/
+  UINT8                       EnableFastVmode[5];
+
+/** Offset 0x06D0 - Vsys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      VsysFullScale1;
+
+/** Offset 0x06D4 - Vsys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      VsysCriticalThreshold1;
+
+/** Offset 0x06D8 - Psys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      PsysFullScale;
+
+/** Offset 0x06DC - Psys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      PsysCriticalThreshold;
+
+/** Offset 0x06E0 - ReservedCpuPostMemProduction
  Reserved for CPU Post-Mem Production
  $EN_DIS
 **/
-  UINT8                       ReservedCpuPostMemProduction[32];
+  UINT8                       ReservedCpuPostMemProduction[11];

 /** Offset 0x06EB - Enable Power Optimizer
  Enable DMI Power Optimizer on PCH side.
@@ -1957,9 +1987,10 @@ typedef struct {
 **/
  UINT8                       ThcPort1Assignment;

-/** Offset 0x0896
+/** Offset 0x0896 - Touch Host Controller Port 1 Hid Over Spi Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
 **/
-  UINT8                       UnusedUpdSpace25[2];
+  UINT16                      ThcPort1HidResetSequencingDelay;

 /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
  Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
@@ -2063,7 +2094,12 @@ typedef struct {

 /** Offset 0x09A1
 **/
-  UINT8                       UnusedUpdSpace26[3];
+  UINT8                       Rsvd24;
+
+/** Offset 0x09A2 - Touch Host Controller Port 0 Hid Over Spi Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
+**/
+  UINT16                      ThcPort0HidResetSequencingDelay;

 /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
  Allows to select the downstream port preset value that will be used during phase
@@ -2352,7 +2388,7 @@ typedef struct {

 /** Offset 0x0A45
 **/
-  UINT8                       UnusedUpdSpace27;
+  UINT8                       Rsvd25;

 /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
  Custimized T0Level value.
@@ -2527,7 +2563,7 @@ typedef struct {

 /** Offset 0x0A6B
 **/
-  UINT8                       UnusedUpdSpace28;
+  UINT8                       Rsvd26;

 /** Offset 0x0A6C - Thermal Device Temperature
  Decides the temperature.
@@ -2557,7 +2593,7 @@ typedef struct {

 /** Offset 0x0A8B
 **/
-  UINT8                       UnusedUpdSpace29;
+  UINT8                       Rsvd27;

 /** Offset 0x0A8C - xHCI High Idle Time LTR override
  Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -2624,7 +2660,7 @@ typedef struct {

 /** Offset 0x0A9F
 **/
-  UINT8                       UnusedUpdSpace30[1];
+  UINT8                       Rsvd28[1];

 /** Offset 0x0AA0 - BgpdtHash[4]
  BgpdtHash values
@@ -2638,7 +2674,7 @@ typedef struct {

 /** Offset 0x0AC4
 **/
-  UINT8                       UnusedUpdSpace31[4];
+  UINT8                       Rsvd29[4];

 /** Offset 0x0AC8 - BiosGuardModulePtr
  BiosGuardModulePtr default values
@@ -2671,7 +2707,7 @@ typedef struct {

 /** Offset 0x0ADB
 **/
-  UINT8                       UnusedUpdSpace32;
+  UINT8                       Rsvd30;

 /** Offset 0x0ADC - Change Default SVID
  Change the default SVID used in FSP to programming internal devices. This is only
@@ -2805,7 +2841,7 @@ typedef struct {

 /** Offset 0x0B06
 **/
-  UINT8                       UnusedUpdSpace33[2];
+  UINT8                       Rsvd31[2];

 /** Offset 0x0B08 - PMC ADR source selection
  Specify which sources should cause ADR flow
@@ -2903,7 +2939,7 @@ typedef struct {

 /** Offset 0x0BD1
 **/
-  UINT8                       UnusedUpdSpace34[3];
+  UINT8                       Rsvd32[3];

 /** Offset 0x0BD4 - CPU PCIE device override table pointer
  The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -3180,7 +3216,7 @@ typedef struct {

 /** Offset 0x0CA2
 **/
-  UINT8                       UnusedUpdSpace35[2];
+  UINT8                       Rsvd33[2];

 /** Offset 0x0CA4 - LogoPixelHeight Address
  Address of LogoPixelHeight
@@ -3612,7 +3648,7 @@ typedef struct {

 /** Offset 0x0D2D
 **/
-  UINT8                       UnusedUpdSpace36;
+  UINT8                       Rsvd34;

 /** Offset 0x0D2E - Platform Power Pmax
  PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
@@ -3652,7 +3688,7 @@ typedef struct {

 /** Offset 0x0D3A
 **/
-  UINT8                       UnusedUpdSpace37[2];
+  UINT8                       Rsvd35[2];

 /** Offset 0x0D3C - Package Long duration turbo mode power limit
  Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -3840,11 +3876,29 @@ typedef struct {
 **/
  UINT8                       DualTauBoost;

-/** Offset 0x0D84 - ReservedCpuPostMemTest
+/** Offset 0x0D84 - Is Battery Present
+  BatteryPresent Enable/Disable; <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       StepDownMode;
+
+/** Offset 0x0D85 - Platform ATX Telemetry Unit
+  Set ATX Telemetry Unit in Watts or Percentage; <b>0: Watts</b>; 1: Percent
+**/
+  UINT8                       PlatformAtxTelemetryUnit;
+
+/** Offset 0x0D86 - ProcHot Demotion Algorithm configuration
+  ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable;<b>
+  1: Hardware Default</b>
+  $EN_DIS
+**/
+  UINT8                       ProcHotDemotion;
+
+/** Offset 0x0D87 - ReservedCpuPostMemTest
  Reserved for CPU Post-Mem Test
  $EN_DIS
 **/
-  UINT8                       ReservedCpuPostMemTest[16];
+  UINT8                       ReservedCpuPostMemTest[13];

 /** Offset 0x0D94
 **/
@@ -3897,7 +3951,7 @@ typedef struct {

 /** Offset 0x0DAB
 **/
-  UINT8                       UnusedUpdSpace38[1];
+  UINT8                       Rsvd36[1];

 /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
  Latency Tolerance Reporting, Max Snoop Latency.
@@ -4112,7 +4166,7 @@ typedef struct {

 /** Offset 0x0FCF
 **/
-  UINT8                       UnusedUpdSpace39;
+  UINT8                       Rsvd37;

 /** Offset 0x0FD0 - FspEventHandler
  <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
@@ -4146,7 +4200,7 @@ typedef struct {

 /** Offset 0x0FDB
 **/
-  UINT8                       UnusedUpdSpace40;
+  UINT8                       Rsvd38;

 /** Offset 0x0FDC - HorizontalResolution for PEI Logo
  HorizontalResolution from PEIm Gfx for PEI Logo
@@ -4229,9 +4283,23 @@ typedef struct {

 /** Offset 0x104C
 **/
-  UINT8                       UnusedUpdSpace41[2];
+  UINT8                       Rsvd39[4];

-/** Offset 0x104E
+/** Offset 0x1050 - MemoryBuffer
+  MemoryBuffer address
+**/
+  UINT64                      MemoryBuffer;
+
+/** Offset 0x1058 - MemorySize
+  MemorySize value
+**/
+  UINT32                      MemorySize;
+
+/** Offset 0x105C
+**/
+  UINT8                       Rsvd40[2];
+
+/** Offset 0x105E
 **/
  UINT8                       ReservedFspsUpd[2];
 } FSP_S_CONFIG;
@@ -4252,11 +4320,11 @@ typedef struct {
 **/
  FSP_S_CONFIG                FspsConfig;

-/** Offset 0x1050
+/** Offset 0x1060
 **/
-  UINT8                       UnusedUpdSpace42[6];
+  UINT8                       Rsvd41[6];

-/** Offset 0x1056
+/** Offset 0x1066
 **/
  UINT16                      UpdTerminator;
 } FSPS_UPD;
--- a/models/addw3/AlderLakeFspBinPkg/Include/FsptUpd.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/FsptUpd.h
@@ -1,6 +1,6 @@
 /** @file

-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>

 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -89,7 +89,7 @@ typedef struct {

 /** Offset 0x0063
 **/
-  UINT8                       UnusedUpdSpace0;
+  UINT8                       Rsvd00;

 /** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
  Set default BaudRate Supported from 0 - default to 6000000
@@ -205,7 +205,7 @@ typedef struct {

 /** Offset 0x0093
 **/
-  UINT8                       UnusedUpdSpace1;
+  UINT8                       Rsvd01;

 /** Offset 0x0094 - PcdSerialIo2ndUartBaudRate - FSPT
  Set default BaudRate Supported from 0 - default to 6000000
@@ -311,7 +311,7 @@ typedef struct {

 /** Offset 0x00C1
 **/
-  UINT8                       UnusedUpdSpace2[3];
+  UINT8                       Rsvd02[3];

 /** Offset 0x00C4 - Serial Io SPI Device MMIO Base
  Assigns MMIO for Serial Io SPI controller usage in early stage.
@@ -345,7 +345,7 @@ typedef struct {

 /** Offset 0x00D8
 **/
-  UINT8                       UnusedUpdSpace3[6];
+  UINT8                       Rsvd03[6];

 /** Offset 0x00DE
 **/
--- a/models/addw3/AlderLakeFspBinPkg/Include/GpioConfig.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/GpioConfig.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/GpioSampleDef.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/GpioSampleDef.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/HobUsageDataHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/HobUsageDataHob.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/MemInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/MemInfoHob.h
@@ -47,8 +47,6 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
 #define MAX_NODE        2
 #define MAX_CH          4
 #define MAX_DIMM        2
-// Must match definitions in
-// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
 #define HOB_MAX_SAGV_POINTS 4

 ///
--- a/models/addw3/AlderLakeFspBinPkg/Include/SmbiosCacheInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/SmbiosCacheInfoHob.h
--- a/models/addw3/AlderLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h
+++ b/models/addw3/AlderLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h
--- a/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c
+++ b/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c
--- a/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf
+++ b/models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.bin
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.bin
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.json
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/Vbt.json
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.bin
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.bin
--- a/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.json
+++ b/models/addw3/AlderLakeFspBinPkg/SampleCode/Vbt/VbtAdlP.json
--- a/models/addw3/IntelGopDriver.efi
+++ b/models/addw3/IntelGopDriver.efi
--- a/models/thelio-b1/IntelGopDriver.inf
+++ b/models/thelio-b1/IntelGopDriver.inf
--- a/models/thelio-b1/README.md
+++ b/models/thelio-b1/README.md
@@ -1,6 +1,4 @@
-# System76 Thelio (thelio-b1)
-
-https://system76.com/guides/thelio/b1
+# System76 Adder WS (addw3)

 ## Contents

@@ -10,5 +8,5 @@ https://system76.com/guides/thelio/b1
  - Size: 4 KB
  - HAP: false
 - [ME](./me.rom)
-  - Size: 3060 KB
-  - Version: 12.0.0.1069
+  - Size: 3944 KB
+  - Version: 16.1.25.2091
--- a/models/addw3/README.md.in
+++ b/models/addw3/README.md.in
@@ -0,0 +1 @@
+# System76 Adder WS (addw3)
--- a/models/addw3/chip.txt
+++ b/models/addw3/chip.txt
@@ -0,0 +1 @@
+GD25Q256D
--- a/models/addw3/coreboot-collector.txt
+++ b/models/addw3/coreboot-collector.txt
@@ -0,0 +1,333 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
+PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
+PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
+PCI Device: 0000:00:1b.0: Class 0x00060400, Vendor 0x8086, Device 0x7A44, Revision 0x11
+PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3C, Revision 0x11
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
+PCI Device: 0000:00:1f.3: Class 0x00040100, Vendor 0x8086, Device 0x7A50, Revision 0x11
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
+PCI Device: 0000:00:1f.6: Class 0x00020000, Vendor 0x8086, Device 0x0DC8, Revision 0x11
+PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2820, Revision 0xA1
+PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BD, Revision 0xA1
+PCI Device: 0000:02:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:01.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:02.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:03:03.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
+PCI Device: 0000:04:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x1134, Revision 0x00
+PCI Device: 0000:39:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x1135, Revision 0x00
+PCI Device: 0000:6c:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
+PCI Device: 10000:e0:1d.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 10000:e0:1d.4: Class 0x00060400, Vendor 0x8086, Device 0x7A34, Revision 0x11
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
+## GPIO ##
+600 Series PCH
+GPP_I0 (0x6E,0x00) 0x44000100 0x00000018 0x00000000 0x00000000
+GPP_I1 (0x6E,0x02) 0x44000500 0x00000019 0x00000000 0x00000000
+GPP_I2 (0x6E,0x04) 0x86800100 0x0000001a 0x00000000 0x00000000
+GPP_I3 (0x6E,0x06) 0x44000500 0x0000001b 0x00000000 0x00000000
+GPP_I4 (0x6E,0x08) 0x86800100 0x0000001c 0x00000000 0x00000000
+GPP_I5 (0x6E,0x0A) 0x84000201 0x0000001d 0x00000000 0x00000000
+GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
+GPP_I7 (0x6E,0x0E) 0x44000300 0x00000020 0x00000000 0x00000000
+GPP_I8 (0x6E,0x10) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_I9 (0x6E,0x12) 0x44000300 0x00000022 0x00000000 0x00000000
+GPP_I10 (0x6E,0x14) 0x44000300 0x00000023 0x00000000 0x00000000
+GPP_I11 (0x6E,0x16) 0x84000402 0x00000024 0x00000000 0x00000000
+GPP_I12 (0x6E,0x18) 0x84000402 0x00000025 0x00000000 0x00000000
+GPP_I13 (0x6E,0x1A) 0x84000402 0x00000026 0x00000000 0x00000000
+GPP_I14 (0x6E,0x1C) 0x84000402 0x00000027 0x00000000 0x00000000
+GPP_I15 (0x6E,0x1E) 0x44000300 0x00000028 0x00000000 0x00000000
+GPP_I16 (0x6E,0x20) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_I17 (0x6E,0x22) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_I18 (0x6E,0x24) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_I19 (0x6E,0x26) 0x44000300 0x0000002c 0x00000000 0x00000000
+GPP_I20 (0x6E,0x28) 0x44000300 0x0000002d 0x00000000 0x00000000
+GPP_I21 (0x6E,0x2A) 0x44000300 0x0000002e 0x00000000 0x00000000
+GPP_I22 (0x6E,0x2C) 0x44000200 0x00000030 0x00000000 0x00000000
+GPP_R0 (0x6E,0x32) 0x44000600 0x00000031 0x00000000 0x00000000
+GPP_R1 (0x6E,0x34) 0x44000600 0x00003c32 0x00000000 0x00000000
+GPP_R2 (0x6E,0x36) 0x44000600 0x00003c33 0x00000000 0x00000000
+GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
+GPP_R4 (0x6E,0x3A) 0x44000600 0x00000035 0x00000000 0x00000000
+GPP_R5 (0x6E,0x3C) 0x44000300 0x00000036 0x00000000 0x00000000
+GPP_R6 (0x6E,0x3E) 0x44000300 0x00000037 0x00000000 0x00000000
+GPP_R7 (0x6E,0x40) 0x44000300 0x00000038 0x00000000 0x00000000
+GPP_R8 (0x6E,0x42) 0x84000102 0x00000039 0x00000000 0x00000000
+GPP_R9 (0x6E,0x44) 0x44000502 0x0000003a 0x00000000 0x00000000
+GPP_R10 (0x6E,0x46) 0x44000300 0x0000003b 0x00000000 0x00000000
+GPP_R11 (0x6E,0x48) 0x44000300 0x0000003c 0x00000000 0x00000000
+GPP_R12 (0x6E,0x4A) 0x44000300 0x0000003d 0x00000000 0x00000000
+GPP_R13 (0x6E,0x4C) 0x44000300 0x0000003e 0x00000000 0x00000000
+GPP_R14 (0x6E,0x4E) 0x44000300 0x0000003f 0x00000000 0x00000000
+GPP_R15 (0x6E,0x50) 0x44000300 0x00000040 0x00000000 0x00000000
+GPP_R16 (0x6E,0x52) 0x44000201 0x00000041 0x00000000 0x00000000
+GPP_R17 (0x6E,0x54) 0x44000300 0x00000042 0x00000000 0x00000000
+GPP_R18 (0x6E,0x56) 0x44000300 0x00000043 0x00000000 0x00000000
+GPP_R19 (0x6E,0x58) 0x44000300 0x00000044 0x00000000 0x00000000
+GPP_R20 (0x6E,0x5A) 0x44000300 0x00000045 0x00000000 0x00000000
+GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
+GPP_J0 (0x6E,0x60) 0x44000502 0x00000047 0x00000000 0x00000000
+GPP_J1 (0x6E,0x62) 0x84000600 0x00000048 0x00000000 0x00000000
+GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
+GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
+GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
+GPP_J5 (0x6E,0x6A) 0x44000502 0x0000304c 0x00000000 0x00000000
+GPP_J6 (0x6E,0x6C) 0x44000502 0x0000004d 0x00000000 0x00000000
+GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
+GPP_J8 (0x6E,0x70) 0x44000300 0x00000050 0x00000000 0x00000000
+GPP_J9 (0x6E,0x72) 0x44000300 0x00000051 0x00000000 0x00000000
+GPP_J10 (0x6E,0x74) 0x44000700 0x00001052 0x00000000 0x00000000
+GPP_J11 (0x6E,0x76) 0x44000700 0x00001053 0x00000000 0x00000000
+GPP_B0 (0x6D,0x00) 0x40100102 0x00000050 0x00000000 0x00000000
+GPP_B1 (0x6D,0x02) 0x44000300 0x00000051 0x00000000 0x00000000
+GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
+GPP_B3 (0x6D,0x06) 0x44000201 0x00000053 0x00000000 0x00000000
+GPP_B4 (0x6D,0x08) 0x44000300 0x00000054 0x00000000 0x00000000
+GPP_B5 (0x6D,0x0A) 0x44000300 0x00000055 0x00000000 0x00000000
+GPP_B6 (0x6D,0x0C) 0x44000300 0x00000056 0x00000000 0x00000000
+GPP_B7 (0x6D,0x0E) 0x44000300 0x00000057 0x00000000 0x00000000
+GPP_B8 (0x6D,0x10) 0x44000300 0x00000058 0x00000000 0x00000000
+GPP_B9 (0x6D,0x12) 0x44000300 0x00000059 0x00000000 0x00000000
+GPP_B10 (0x6D,0x14) 0x44000300 0x0000005a 0x00000000 0x00000000
+GPP_B11 (0x6D,0x16) 0x44000300 0x0000005b 0x00000000 0x00000000
+GPP_B12 (0x6D,0x18) 0x44000600 0x0000005c 0x00000000 0x00000000
+GPP_B13 (0x6D,0x1A) 0x44000600 0x0000005d 0x00000000 0x00000000
+GPP_B14 (0x6D,0x1C) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_B15 (0x6D,0x1E) 0x44000102 0x0000005f 0x00000000 0x00000000
+GPP_B16 (0x6D,0x20) 0x44000300 0x00000060 0x00000000 0x00000000
+GPP_B17 (0x6D,0x22) 0x44000300 0x00000061 0x00000000 0x00000000
+GPP_B18 (0x6D,0x24) 0x04000602 0x00000062 0x00000000 0x00000000
+GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
+GPP_B20 (0x6D,0x28) 0x44000700 0x00001064 0x00000000 0x00000000
+GPP_B21 (0x6D,0x2A) 0x42880102 0x00000065 0x00000000 0x00000000
+GPP_B22 (0x6D,0x2C) 0x44000201 0x00000066 0x00000000 0x00000000
+GPP_B23 (0x6D,0x2E) 0x44000200 0x00000067 0x00000800 0x00000000
+GPP_G0 (0x6D,0x30) 0x44000100 0x00000068 0x00000000 0x00000000
+GPP_G1 (0x6D,0x32) 0x44000102 0x00000069 0x00000000 0x00000000
+GPP_G2 (0x6D,0x34) 0x44000700 0x0000106a 0x00000000 0x00000000
+GPP_G3 (0x6D,0x36) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_G4 (0x6D,0x38) 0x44000102 0x0000006c 0x00000000 0x00000000
+GPP_G5 (0x6D,0x3A) 0x44000600 0x0000006d 0x00000000 0x00000000
+GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
+GPP_G7 (0x6D,0x3E) 0x44000100 0x0000006f 0x00000000 0x00000000
+GPP_H0 (0x6D,0x40) 0x44000300 0x00000070 0x00000000 0x00000000
+GPP_H1 (0x6D,0x42) 0x44000102 0x00000071 0x00000000 0x00000000
+GPP_H2 (0x6D,0x44) 0x44000702 0x00000072 0x00000000 0x00000000
+GPP_H3 (0x6D,0x46) 0x44000300 0x00000073 0x00000000 0x00000000
+GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
+GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
+GPP_H6 (0x6D,0x4C) 0x44000702 0x00000076 0x00000000 0x00000000
+GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
+GPP_H8 (0x6D,0x50) 0x44000700 0x00000018 0x00000000 0x00000000
+GPP_H9 (0x6D,0x52) 0x44000700 0x00000019 0x00000000 0x00000000
+GPP_H10 (0x6D,0x54) 0x84000402 0x00000020 0x00000000 0x00000000
+GPP_H11 (0x6D,0x56) 0x84000402 0x00000021 0x00000000 0x00000000
+GPP_H12 (0x6D,0x58) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_H13 (0x6D,0x5A) 0x84000402 0x00000023 0x00000000 0x00000000
+GPP_H14 (0x6D,0x5C) 0x84000402 0x00000024 0x00000000 0x00000000
+GPP_H15 (0x6D,0x5E) 0x84000402 0x00000025 0x00000800 0x00000000
+GPP_H16 (0x6D,0x60) 0x84000402 0x00000026 0x00000000 0x00000000
+GPP_H17 (0x6D,0x62) 0x84000201 0x00000027 0x00000000 0x00000000
+GPP_H18 (0x6D,0x64) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_H19 (0x6D,0x66) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_H20 (0x6D,0x68) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_H21 (0x6D,0x6A) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_H23 (0x6D,0x6E) 0x44000300 0x0000002d 0x00000000 0x00000000
+GPD0 (0x6C,0x00) 0x04000502 0x00003060 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000502 0x00003c61 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x04000702 0x00000062 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000502 0x00003063 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000200 0x00000067 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000600 0x00000068 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000600 0x00000069 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x04000600 0x0000006b 0x00000000 0x00000000
+GPD12 (0x6C,0x18) 0x04000300 0x0000006c 0x00000000 0x00000000
+GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
+GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
+GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
+GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
+GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
+GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
+GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
+GPP_A7 (0x6B,0x20) 0x44000700 0x00003025 0x00000000 0x00000000
+GPP_A8 (0x6B,0x22) 0x44000700 0x00003026 0x00000000 0x00000000
+GPP_A9 (0x6B,0x24) 0x44000700 0x00003027 0x00000000 0x00000000
+GPP_A10 (0x6B,0x26) 0x44000702 0x00003028 0x00000000 0x00000000
+GPP_A11 (0x6B,0x28) 0x44000702 0x00003029 0x00000000 0x00000000
+GPP_A12 (0x6B,0x2A) 0x44000702 0x0000302a 0x00000000 0x00000000
+GPP_A13 (0x6B,0x2C) 0x44000702 0x0000302b 0x00000000 0x00000000
+GPP_A14 (0x6B,0x2E) 0x44000300 0x0000002c 0x00000000 0x00000000
+GPP_C0 (0x6B,0x32) 0x44000402 0x0000002d 0x00000000 0x00000000
+GPP_C1 (0x6B,0x34) 0x44000402 0x0000002e 0x00000000 0x00000000
+GPP_C2 (0x6B,0x36) 0x44000200 0x0000002f 0x00000800 0x00000000
+GPP_C3 (0x6B,0x38) 0x44000c02 0x00000030 0x00000000 0x00000000
+GPP_C4 (0x6B,0x3A) 0x44000c02 0x00000031 0x00000000 0x00000000
+GPP_C5 (0x6B,0x3C) 0x44000200 0x00000032 0x00000000 0x00000000
+GPP_C6 (0x6B,0x3E) 0x44000802 0x00000033 0x00000000 0x00000000
+GPP_C7 (0x6B,0x40) 0x44000802 0x00000034 0x00000000 0x00000000
+GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
+GPP_C9 (0x6B,0x44) 0x44000300 0x00000036 0x00000000 0x00000000
+GPP_C10 (0x6B,0x46) 0x44000201 0x00000037 0x00000000 0x00000000
+GPP_C11 (0x6B,0x48) 0x44000201 0x00000038 0x00000000 0x00000000
+GPP_C12 (0x6B,0x4A) 0x44000300 0x00000039 0x00000000 0x00000000
+GPP_C13 (0x6B,0x4C) 0x44000300 0x0000003a 0x00000000 0x00000000
+GPP_C14 (0x6B,0x4E) 0x44000300 0x0000003b 0x00000000 0x00000000
+GPP_C15 (0x6B,0x50) 0x44000300 0x0000003c 0x00000000 0x00000000
+GPP_C16 (0x6B,0x52) 0x44000402 0x0000003d 0x00000000 0x00000000
+GPP_C17 (0x6B,0x54) 0x44000402 0x0000003e 0x00000000 0x00000000
+GPP_C18 (0x6B,0x56) 0x44000402 0x0000003f 0x00000000 0x00000000
+GPP_C19 (0x6B,0x58) 0x44000402 0x00000040 0x00000000 0x00000000
+GPP_C20 (0x6B,0x5A) 0x44000300 0x00000041 0x00000000 0x00000000
+GPP_C21 (0x6B,0x5C) 0x44000300 0x00000042 0x00000000 0x00000000
+GPP_C22 (0x6B,0x5E) 0x44000300 0x00000043 0x00000000 0x00000000
+GPP_C23 (0x6B,0x60) 0x44000300 0x00000044 0x00000000 0x00000000
+GPP_S0 (0x6A,0x00) 0x44000300 0x01800030 0x00000000 0x00000000
+GPP_S1 (0x6A,0x02) 0x44000300 0x01800031 0x00000000 0x00000000
+GPP_S2 (0x6A,0x04) 0x44000300 0x01800032 0x00000000 0x00000000
+GPP_S3 (0x6A,0x06) 0x44000300 0x01800033 0x00000000 0x00000000
+GPP_S4 (0x6A,0x08) 0x44000300 0x01800034 0x00000000 0x00000000
+GPP_S5 (0x6A,0x0A) 0x44000300 0x01800035 0x00000000 0x00000000
+GPP_S6 (0x6A,0x0C) 0x44000a00 0x01800036 0x00000000 0x00000000
+GPP_S7 (0x6A,0x0E) 0x44000900 0x01800037 0x00000000 0x00000000
+GPP_E0 (0x6A,0x10) 0x44000300 0x00000038 0x00000000 0x00000000
+GPP_E1 (0x6A,0x12) 0x44000300 0x00000039 0x00000000 0x00000000
+GPP_E2 (0x6A,0x14) 0x44000300 0x0000003a 0x00000000 0x00000000
+GPP_E3 (0x6A,0x16) 0x42840103 0x0000003b 0x00000000 0x00000000
+GPP_E4 (0x6A,0x18) 0x44000300 0x0000003c 0x00000000 0x00000000
+GPP_E5 (0x6A,0x1A) 0x44000300 0x0000003d 0x00000000 0x00000000
+GPP_E6 (0x6A,0x1C) 0x44000300 0x0000003e 0x00000000 0x00000000
+GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
+GPP_E8 (0x6A,0x20) 0x44000600 0x00000040 0x00000000 0x00000000
+GPP_E9 (0x6A,0x22) 0x44000602 0x00000041 0x00000800 0x00000000
+GPP_E10 (0x6A,0x24) 0x44000602 0x00000042 0x00000800 0x00000000
+GPP_E11 (0x6A,0x26) 0x44000602 0x00000043 0x00000800 0x00000000
+GPP_E12 (0x6A,0x28) 0x44000602 0x00000044 0x00000000 0x00000000
+GPP_E13 (0x6A,0x2A) 0x44000300 0x00000045 0x00000000 0x00000000
+GPP_E14 (0x6A,0x2C) 0x44000300 0x00000046 0x00000000 0x00000000
+GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
+GPP_E16 (0x6A,0x30) 0x44000300 0x00000048 0x00000000 0x00000000
+GPP_E17 (0x6A,0x32) 0x44000102 0x00001049 0x00000000 0x00000000
+GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
+GPP_E19 (0x6A,0x36) 0x44000300 0x0000004b 0x00000000 0x00000000
+GPP_E20 (0x6A,0x38) 0x44000300 0x0000004c 0x00000000 0x00000000
+GPP_E21 (0x6A,0x3A) 0x44000300 0x0000004d 0x00000000 0x00000000
+GPP_K0 (0x6A,0x3E) 0x42800102 0x0000004e 0x00000000 0x00000000
+GPP_K1 (0x6A,0x40) 0x44000300 0x00000050 0x00000000 0x00000000
+GPP_K2 (0x6A,0x42) 0x44000300 0x00000051 0x00000000 0x00000000
+GPP_K3 (0x6A,0x44) 0x84000201 0x00000052 0x00000000 0x00000000
+GPP_K4 (0x6A,0x46) 0x04000200 0x00000053 0x00000000 0x00000000
+GPP_K5 (0x6A,0x48) 0x44000300 0x00000054 0x00000000 0x00000000
+GPP_K6 (0x6A,0x4A) 0x44000b02 0x00003055 0x00000000 0x00000000
+GPP_K7 (0x6A,0x4C) 0x44000b00 0x00001056 0x00000000 0x00000000
+GPP_K8 (0x6A,0x4E) 0x44000600 0x00000057 0x00000000 0x00000000
+GPP_K9 (0x6A,0x50) 0x44000600 0x00000058 0x00000000 0x00000000
+GPP_K10 (0x6A,0x52) 0x44000b02 0x00003059 0x00000000 0x00000000
+GPP_K11 (0x6A,0x54) 0x44000300 0x0000005a 0x00000000 0x00000000
+GPP_F0 (0x6A,0x5C) 0x44000a02 0x0000005b 0x00000000 0x00000000
+GPP_F1 (0x6A,0x5E) 0x44000300 0x0000005c 0x00000000 0x00000000
+GPP_F2 (0x6A,0x60) 0x84000201 0x0000005d 0x00000000 0x00000000
+GPP_F3 (0x6A,0x62) 0x84000201 0x0000005e 0x00000000 0x00000000
+GPP_F4 (0x6A,0x64) 0x84000201 0x00000060 0x00000000 0x00000000
+GPP_F5 (0x6A,0x66) 0x44000600 0x00000061 0x00000000 0x00000000
+GPP_F6 (0x6A,0x68) 0x44000300 0x00000062 0x00000000 0x00000000
+GPP_F7 (0x6A,0x6A) 0x84000102 0x00000063 0x00000000 0x00000000
+GPP_F8 (0x6A,0x6C) 0x44000100 0x00000064 0x00000000 0x00000000
+GPP_F9 (0x6A,0x6E) 0x44000201 0x00000065 0x00000000 0x00000000
+GPP_F10 (0x6A,0x70) 0x44000300 0x00000066 0x00000000 0x00000000
+GPP_F11 (0x6A,0x72) 0x44000300 0x00000067 0x00000000 0x00000000
+GPP_F12 (0x6A,0x74) 0x44000300 0x00000068 0x00000000 0x00000000
+GPP_F13 (0x6A,0x76) 0x44000300 0x00000069 0x00000000 0x00000000
+GPP_F14 (0x6A,0x78) 0x44000700 0x0000006a 0x00000000 0x00000000
+GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_F16 (0x6A,0x7C) 0x44000300 0x0000006c 0x00000000 0x00000000
+GPP_F17 (0x6A,0x7E) 0x44000102 0x0000006d 0x00000000 0x00000000
+GPP_F18 (0x6A,0x80) 0x84000200 0x0000006e 0x00000000 0x00000000
+GPP_F19 (0x6A,0x82) 0x44000600 0x0000006f 0x00000000 0x00000000
+GPP_F20 (0x6A,0x84) 0x44000600 0x00000070 0x00000000 0x00000000
+GPP_F21 (0x6A,0x86) 0x44000600 0x00000071 0x00000000 0x00000000
+GPP_F22 (0x6A,0x88) 0x44000300 0x00000072 0x00000000 0x00000000
+GPP_F23 (0x6A,0x8A) 0x44000300 0x00000073 0x00000000 0x00000000
+GPP_D0 (0x69,0x20) 0x44000300 0x00000026 0x00000000 0x00000000
+GPP_D1 (0x69,0x22) 0x44000300 0x00000027 0x00000000 0x00000000
+GPP_D2 (0x69,0x24) 0x44000300 0x00000028 0x00000000 0x00000000
+GPP_D3 (0x69,0x26) 0x44000300 0x00000029 0x00000000 0x00000000
+GPP_D4 (0x69,0x28) 0x44000300 0x0000002a 0x00000000 0x00000000
+GPP_D5 (0x69,0x2A) 0x44000300 0x0000002b 0x00000000 0x00000000
+GPP_D6 (0x69,0x2C) 0x44000300 0x0000002c 0x00000000 0x00000000
+GPP_D7 (0x69,0x2E) 0x44000300 0x0000002d 0x00000000 0x00000000
+GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
+GPP_D9 (0x69,0x32) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D10 (0x69,0x34) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D13 (0x69,0x3A) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D14 (0x69,0x3C) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
+GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D22 (0x69,0x4C) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+  vendor_name: Realtek
+  chip_name: ALC256
+  vendor_id: 0x10ec0256
+  subsystem_id: 0x1558a671
+  revision_id: 0x100002
+  0x12: 0x90a60130
+  0x13: 0x40000000
+  0x14: 0x90170110
+  0x18: 0x411111f0
+  0x19: 0x411111f0
+  0x1a: 0x411111f0
+  0x1b: 0x02a11040
+  0x1d: 0x41700001
+  0x1e: 0x411111f0
+  0x21: 0x02211020
+hdaudioC0D2
+  vendor_name: Intel
+  chip_name: Raptorlake HDMI
+  vendor_id: 0x80862818
+  subsystem_id: 0x80860101
+  revision_id: 0x100000
+  0x04: 0x18560010
+  0x06: 0x18560010
+  0x08: 0x18560010
+  0x0a: 0x18560010
+  0x0b: 0x18560010
+  0x0c: 0x18560010
+  0x0d: 0x18560010
+  0x0e: 0x18560010
+  0x0f: 0x18560010
+hdaudioC1D0
+  vendor_name: Nvidia
+  chip_name: Generic HDMI
+  vendor_id: 0x10de00a6
+  subsystem_id: 0x10de0000
+  revision_id: 0x100100
+  0x04: 0x185600f0
+  0x05: 0x585600f0
+  0x06: 0x185600f0
+  0x07: 0x585600f0
--- a/models/addw3/coreboot.config
+++ b/models/addw3/coreboot.config
@@ -0,0 +1,28 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_ADDW3=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+CONFIG_HAVE_GBE_BIN=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_GBE_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/gbe.rom"
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
+CONFIG_POST_IO=n
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_V2=y
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
+
+# Custom FSP
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Fsp.fd"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Include"
+CONFIG_FSP_USE_REPO=n
--- a/models/addw3/ec.config
+++ b/models/addw3/ec.config
@@ -0,0 +1 @@
+BOARD=system76/addw3
--- a/models/addw3/ecspy.txt
+++ b/models/addw3/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 6
+A0: data 1 mirror 1 pot 0 control 00
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 0 mirror 1 pot 0 control 00
+A3: data 1 mirror 1 pot 0 control 80
+A4: data 0 mirror 0 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 0 mirror 1 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 80
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 1 mirror 1 pot 0 control 40
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 40
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 44
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 1 mirror 1 pot 0 control 44
+D4: data 1 mirror 1 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 1 mirror 1 pot 0 control 02
+D7: data 0 mirror 0 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 0 mirror 0 pot 0 control 84
+E3: data 1 mirror 1 pot 0 control 40
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 1 mirror 1 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 40
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 0 mirror 0 pot 0 control 00
+F7: data 0 mirror 0 pot 0 control 80
+G0: data 0 mirror 0 pot 0 control 80
+G1: data 1 mirror 1 pot 0 control 80
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 0 mirror 0 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 0 mirror 0 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 0 mirror 0 pot 0 control 40
+H4: data 1 mirror 1 pot 0 control 80
+H5: data 0 mirror 0 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 80
+H7: data 1 mirror 1 pot 0 control 80
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 00
+I3: data 0 mirror 0 pot 0 control 00
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 1 mirror 1 pot 0 control 80
+I6: data 1 mirror 1 pot 0 control 80
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 1 mirror 1 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 40
+J5: data 0 mirror 0 pot 0 control 40
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 1 mirror 1 pot 0 control 80
+M0: data 0 mirror 0 control 06
+M1: data 1 mirror 0 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 1 control 06
+M5: data 0 mirror 0 control 00
+M6: data 1 mirror 1 control 86
+M7: data 0 mirror 0 control 00
--- a/models/addw3/edk2.config
+++ b/models/addw3/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/addw3/fd.rom
+++ b/models/addw3/fd.rom
--- a/models/addw3/gbe.rom
+++ b/models/addw3/gbe.rom
--- a/models/addw3/gpio.h
+++ b/models/addw3/gpio.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A7, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A13, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A14, NONE),
+	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
+	PAD_NC(GPP_B1, NONE),
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 0, DEEP),
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000),
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+	PAD_NC(GPP_C9, NONE),
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	PAD_CFG_GPO(GPP_C11, 1, DEEP),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	_PAD_CFG_STRUCT(GPP_E3, 0x42840101, 0x0000),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	PAD_NC(GPP_E13, NONE),
+	PAD_NC(GPP_E14, NONE),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, DN_20K, DEEP),
+	PAD_CFG_GPO(GPP_E18, 1, DEEP),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+	PAD_NC(GPP_F1, NONE),
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F3, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F4, 1, PLTRST),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPI(GPP_F7, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, PLTRST),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+	PAD_CFG_NF(GPP_G2, DN_20K, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPI(GPP_H1, NONE, DEEP),
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	PAD_CFG_NF(GPP_H13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H14, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H18, 0, DEEP),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	PAD_CFG_GPO(GPP_H22, 0, DEEP),
+	PAD_NC(GPP_H23, NONE),
+	PAD_CFG_GPI(GPP_I0, NONE, DEEP),
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I2, 0x86800100, 0x0000),
+	PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I4, 0x86800100, 0x0000),
+	PAD_CFG_GPO(GPP_I5, 1, PLTRST),
+	PAD_CFG_GPO(GPP_I6, 0, DEEP),
+	PAD_NC(GPP_I7, NONE),
+	PAD_CFG_GPO(GPP_I8, 0, DEEP),
+	PAD_NC(GPP_I9, NONE),
+	PAD_NC(GPP_I10, NONE),
+	PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
+	PAD_NC(GPP_I15, NONE),
+	PAD_NC(GPP_I16, NONE),
+	PAD_NC(GPP_I17, NONE),
+	PAD_CFG_GPO(GPP_I18, 0, DEEP),
+	PAD_NC(GPP_I19, NONE),
+	PAD_NC(GPP_I20, NONE),
+	PAD_NC(GPP_I21, NONE),
+	PAD_CFG_GPO(GPP_I22, 0, DEEP),
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+	PAD_NC(GPP_J8, NONE),
+	PAD_NC(GPP_J9, NONE),
+	PAD_CFG_NF(GPP_J10, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000),
+	PAD_NC(GPP_K1, NONE),
+	PAD_NC(GPP_K2, NONE),
+	PAD_CFG_GPO(GPP_K3, 1, PLTRST),
+	PAD_CFG_GPO(GPP_K4, 0, PWROK),
+	PAD_NC(GPP_K5, NONE),
+	PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
+	PAD_NC(GPP_K11, NONE),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+	PAD_CFG_GPI(GPP_R8, NONE, PLTRST),
+	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
+	PAD_NC(GPP_R10, NONE),
+	PAD_NC(GPP_R11, NONE),
+	PAD_NC(GPP_R12, NONE),
+	PAD_NC(GPP_R13, NONE),
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
+	PAD_CFG_GPO(GPP_R16, 1, DEEP),
+	PAD_NC(GPP_R17, NONE),
+	PAD_NC(GPP_R18, NONE),
+	PAD_NC(GPP_R19, NONE),
+	PAD_NC(GPP_R20, NONE),
+	PAD_CFG_GPO(GPP_R21, 0, DEEP),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+};
+
+#endif
+
+#endif
--- a/models/addw3/hda_verb.c
+++ b/models/addw3/hda_verb.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x1558a671, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558a671),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+	/* Intel, RaptorlakeHDMI */
+	0x80862818, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+	/* Nvidia, GenericHDMI */
+	0x10de00a6, /* Vendor ID */
+	0x10de0000, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x10de0000),
+	AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x585600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/models/addw3/me.rom
+++ b/models/addw3/me.rom
--- a/models/addw3/vbt.rom
+++ b/models/addw3/vbt.rom
--- a/models/bonw14/edk2.config
+++ b/models/bonw14/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/bonw15/AlderLakeFspBinPkg
+++ b/models/bonw15/AlderLakeFspBinPkg
@@ -0,0 +1 @@
+../addw3/AlderLakeFspBinPkg
--- a/models/bonw15/IntelGopDriver.efi
+++ b/models/bonw15/IntelGopDriver.efi
--- a/models/bonw15/IntelGopDriver.inf
+++ b/models/bonw15/IntelGopDriver.inf
@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IntelGopDriver
+  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.X64]
+  PE32|IntelGopDriver.efi|*
--- a/models/bonw15/README.md
+++ b/models/bonw15/README.md
@@ -0,0 +1,12 @@
+# System76 Bonobo WS (bonw15)
+
+## Contents
+
+- [EC](./ec.rom)
+  - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+  - Size: 4 KB
+  - HAP: false
+- [ME](./me.rom)
+  - Size: 3944 KB
+  - Version: 16.1.25.2091
--- a/models/bonw15/README.md.in
+++ b/models/bonw15/README.md.in
@@ -0,0 +1 @@
+# System76 Bonobo WS (bonw15)
--- a/models/bonw15/chip.txt
+++ b/models/bonw15/chip.txt
@@ -0,0 +1 @@
+GD25Q256D
--- a/models/bonw15/coreboot-collector.txt
+++ b/models/bonw15/coreboot-collector.txt
@@ -0,0 +1,334 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
+PCI Device: 0000:00:01.1: Class 0x00060400, Vendor 0x8086, Device 0xA72D, Revision 0x01
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
+PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
+PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
+PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3E, Revision 0x11
+PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x7A30, Revision 0x11
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
+PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x7A50, Revision 0x11
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
+PCI Device: 0000:02:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x27E0, Revision 0xA1
+PCI Device: 0000:02:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BC, Revision 0xA1
+PCI Device: 0000:03:00.0: Class 0x00020000, Vendor 0x8086, Device 0x3101, Revision 0x03
+PCI Device: 0000:04:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:01.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:02.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:05:03.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
+PCI Device: 0000:06:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x1137, Revision 0x00
+PCI Device: 0000:3a:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x1138, Revision 0x00
+PCI Device: 10000:e0:1b.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 10000:e0:1b.4: Class 0x00060400, Vendor 0x8086, Device 0x7A44, Revision 0x11
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
+## GPIO ##
+600 Series PCH
+GPP_I0 (0x6E,0x00) 0x44000200 0x00000018 0x00000000 0x00000000
+GPP_I1 (0x6E,0x02) 0x86880100 0x00000019 0x00000000 0x00000000
+GPP_I2 (0x6E,0x04) 0x86880100 0x0000001a 0x00000000 0x00000000
+GPP_I3 (0x6E,0x06) 0x86880100 0x0000001b 0x00000000 0x00000000
+GPP_I4 (0x6E,0x08) 0x86880100 0x0000001c 0x00000000 0x00000000
+GPP_I5 (0x6E,0x0A) 0x44000200 0x0000001d 0x00000000 0x00000000
+GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
+GPP_I7 (0x6E,0x0E) 0x44000200 0x00000020 0x00000000 0x00000000
+GPP_I8 (0x6E,0x10) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_I9 (0x6E,0x12) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_I10 (0x6E,0x14) 0x44000200 0x00000023 0x00000000 0x00000000
+GPP_I11 (0x6E,0x16) 0x44000300 0x00000024 0x00000000 0x00000000
+GPP_I12 (0x6E,0x18) 0x44000300 0x00000025 0x00000000 0x00000000
+GPP_I13 (0x6E,0x1A) 0x44000300 0x00000026 0x00000000 0x00000000
+GPP_I14 (0x6E,0x1C) 0x44000300 0x00000027 0x00000000 0x00000000
+GPP_I15 (0x6E,0x1E) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_I16 (0x6E,0x20) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_I17 (0x6E,0x22) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_I18 (0x6E,0x24) 0x44000102 0x0000002b 0x00000000 0x00000000
+GPP_I19 (0x6E,0x26) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_I20 (0x6E,0x28) 0x44000200 0x0000002d 0x00000000 0x00000000
+GPP_I21 (0x6E,0x2A) 0x44000200 0x0000002e 0x00000000 0x00000000
+GPP_I22 (0x6E,0x2C) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_R0 (0x6E,0x32) 0x44000500 0x00000031 0x00000000 0x00000000
+GPP_R1 (0x6E,0x34) 0x44000500 0x00003c32 0x00000000 0x00000000
+GPP_R2 (0x6E,0x36) 0x44000500 0x00003c33 0x00000000 0x00000000
+GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
+GPP_R4 (0x6E,0x3A) 0x44000500 0x00000035 0x00000000 0x00000000
+GPP_R5 (0x6E,0x3C) 0x44000200 0x00000036 0x00000000 0x00000000
+GPP_R6 (0x6E,0x3E) 0x44000200 0x00000037 0x00000000 0x00000000
+GPP_R7 (0x6E,0x40) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_R8 (0x6E,0x42) 0x44000102 0x00000039 0x00000000 0x00000000
+GPP_R9 (0x6E,0x44) 0x44000702 0x0000003a 0x00000000 0x00000000
+GPP_R10 (0x6E,0x46) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_R11 (0x6E,0x48) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_R12 (0x6E,0x4A) 0x44000200 0x0000003d 0x00000000 0x00000000
+GPP_R13 (0x6E,0x4C) 0x44000200 0x0000003e 0x00000000 0x00000000
+GPP_R14 (0x6E,0x4E) 0x44000200 0x0000003f 0x00000000 0x00000000
+GPP_R15 (0x6E,0x50) 0x44000200 0x00000040 0x00000000 0x00000000
+GPP_R16 (0x6E,0x52) 0x44000201 0x00000041 0x00000000 0x00000000
+GPP_R17 (0x6E,0x54) 0x44000200 0x00000042 0x00000000 0x00000000
+GPP_R18 (0x6E,0x56) 0x44000200 0x00000043 0x00000000 0x00000000
+GPP_R19 (0x6E,0x58) 0x44000200 0x00000044 0x00000000 0x00000000
+GPP_R20 (0x6E,0x5A) 0x44000200 0x00000045 0x00000000 0x00000000
+GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
+GPP_J0 (0x6E,0x60) 0x44000500 0x00000047 0x00000000 0x00000000
+GPP_J1 (0x6E,0x62) 0x44000700 0x00000048 0x00000000 0x00000000
+GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
+GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
+GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
+GPP_J5 (0x6E,0x6A) 0x44000500 0x0000304c 0x00000000 0x00000000
+GPP_J6 (0x6E,0x6C) 0x44000500 0x0000004d 0x00000000 0x00000000
+GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
+GPP_J8 (0x6E,0x70) 0x44000102 0x00000050 0x00000000 0x00000000
+GPP_J9 (0x6E,0x72) 0x44000200 0x00000051 0x00000000 0x00000000
+GPP_J10 (0x6E,0x74) 0x44000200 0x00000052 0x00000000 0x00000000
+GPP_J11 (0x6E,0x76) 0x44000200 0x00000053 0x00000000 0x00000000
+GPP_B0 (0x6D,0x00) 0x82900102 0x00000050 0x00000000 0x00000000
+GPP_B1 (0x6D,0x02) 0x44000200 0x00000051 0x00000000 0x00000000
+GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
+GPP_B3 (0x6D,0x06) 0x44000201 0x00000053 0x00000000 0x00000000
+GPP_B4 (0x6D,0x08) 0x44000200 0x00000054 0x00000000 0x00000000
+GPP_B5 (0x6D,0x0A) 0x44000200 0x00000055 0x00000000 0x00000000
+GPP_B6 (0x6D,0x0C) 0x44000200 0x00000056 0x00000000 0x00000000
+GPP_B7 (0x6D,0x0E) 0x44000200 0x00000057 0x00000000 0x00000000
+GPP_B8 (0x6D,0x10) 0x44000200 0x00000058 0x00000000 0x00000000
+GPP_B9 (0x6D,0x12) 0x44000200 0x00000059 0x00000000 0x00000000
+GPP_B10 (0x6D,0x14) 0x44000200 0x0000005a 0x00000000 0x00000000
+GPP_B11 (0x6D,0x16) 0x44000200 0x0000005b 0x00000000 0x00000000
+GPP_B12 (0x6D,0x18) 0x44000700 0x0000005c 0x00000000 0x00000000
+GPP_B13 (0x6D,0x1A) 0x44000700 0x0000005d 0x00000000 0x00000000
+GPP_B14 (0x6D,0x1C) 0x44000600 0x0000005e 0x00000000 0x00000000
+GPP_B15 (0x6D,0x1E) 0x44000200 0x0000005f 0x00000000 0x00000000
+GPP_B16 (0x6D,0x20) 0x44000200 0x00000060 0x00000000 0x00000000
+GPP_B17 (0x6D,0x22) 0x04000201 0x00000061 0x00000000 0x00000000
+GPP_B18 (0x6D,0x24) 0x04000702 0x00000062 0x00000000 0x00000000
+GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
+GPP_B20 (0x6D,0x28) 0x44000200 0x00000064 0x00000000 0x00000000
+GPP_B21 (0x6D,0x2A) 0x44000200 0x00000065 0x00000000 0x00000000
+GPP_B22 (0x6D,0x2C) 0x44000201 0x00000066 0x00000000 0x00000000
+GPP_B23 (0x6D,0x2E) 0x44000102 0x00000067 0x00000800 0x00000000
+GPP_G0 (0x6D,0x30) 0x04000200 0x00000068 0x00000000 0x00000000
+GPP_G1 (0x6D,0x32) 0x44000100 0x00000069 0x00000000 0x00000000
+GPP_G2 (0x6D,0x34) 0x44000100 0x0000106a 0x00000000 0x00000000
+GPP_G3 (0x6D,0x36) 0x44000102 0x0000006b 0x00000000 0x00000000
+GPP_G4 (0x6D,0x38) 0x44000100 0x0000006c 0x00000000 0x00000000
+GPP_G5 (0x6D,0x3A) 0x44000700 0x0000006d 0x00000000 0x00000000
+GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
+GPP_G7 (0x6D,0x3E) 0x42800102 0x0000006f 0x00000000 0x00000000
+GPP_H0 (0x6D,0x40) 0x44000102 0x00000070 0x00000000 0x00000000
+GPP_H1 (0x6D,0x42) 0x44000200 0x00000071 0x00000000 0x00000000
+GPP_H2 (0x6D,0x44) 0x44000100 0x00000072 0x00000000 0x00000000
+GPP_H3 (0x6D,0x46) 0x44000702 0x00000073 0x00000000 0x00000000
+GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
+GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
+GPP_H6 (0x6D,0x4C) 0x44000300 0x00000076 0x00000000 0x00000000
+GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
+GPP_H8 (0x6D,0x50) 0x44000700 0x00000018 0x00000000 0x00000000
+GPP_H9 (0x6D,0x52) 0x44000702 0x00000019 0x00000000 0x00000000
+GPP_H10 (0x6D,0x54) 0x44000502 0x00000020 0x00000000 0x00000000
+GPP_H11 (0x6D,0x56) 0x44000502 0x00000021 0x00000000 0x00000000
+GPP_H12 (0x6D,0x58) 0x44000102 0x00000022 0x00000000 0x00000000
+GPP_H13 (0x6D,0x5A) 0x44000502 0x00000023 0x00000000 0x00000000
+GPP_H14 (0x6D,0x5C) 0x44000500 0x00000024 0x00000000 0x00000000
+GPP_H15 (0x6D,0x5E) 0x44000102 0x00000025 0x00000800 0x00000000
+GPP_H16 (0x6D,0x60) 0x44000102 0x00000026 0x00000000 0x00000000
+GPP_H17 (0x6D,0x62) 0x44000201 0x00000027 0x00000000 0x00000000
+GPP_H18 (0x6D,0x64) 0x44000102 0x00000028 0x00000000 0x00000000
+GPP_H19 (0x6D,0x66) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_H20 (0x6D,0x68) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_H21 (0x6D,0x6A) 0x44000201 0x0000002b 0x00000000 0x00000000
+GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_H23 (0x6D,0x6E) 0x44000102 0x0000002d 0x00000000 0x00000000
+GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000702 0x00003c61 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x42880102 0x00000062 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000100 0x00000067 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000200 0x00000069 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x44000200 0x0000006b 0x00000000 0x00000000
+GPD12 (0x6C,0x18) 0x44000200 0x0000006c 0x00000000 0x00000000
+GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
+GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
+GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
+GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
+GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
+GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
+GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
+GPP_A7 (0x6B,0x20) 0x44000200 0x00000025 0x00000000 0x00000000
+GPP_A8 (0x6B,0x22) 0x44000200 0x00000026 0x00000000 0x00000000
+GPP_A9 (0x6B,0x24) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_A10 (0x6B,0x26) 0x44000500 0x00000028 0x00000000 0x00000000
+GPP_A11 (0x6B,0x28) 0x44000102 0x00003029 0x00000000 0x00000000
+GPP_A12 (0x6B,0x2A) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_A13 (0x6B,0x2C) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_A14 (0x6B,0x2E) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_C0 (0x6B,0x32) 0x44000502 0x0000002d 0x00000000 0x00000000
+GPP_C1 (0x6B,0x34) 0x44000502 0x0000002e 0x00000000 0x00000000
+GPP_C2 (0x6B,0x36) 0x84000102 0x0000002f 0x00000800 0x00000000
+GPP_C3 (0x6B,0x38) 0x44000200 0x00000030 0x00000000 0x00000000
+GPP_C4 (0x6B,0x3A) 0x44000200 0x00000031 0x00000000 0x00000000
+GPP_C5 (0x6B,0x3C) 0x44000502 0x00000032 0x00000000 0x00000000
+GPP_C6 (0x6B,0x3E) 0x44000200 0x00000033 0x00000000 0x00000000
+GPP_C7 (0x6B,0x40) 0x44000200 0x00000034 0x00000000 0x00000000
+GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
+GPP_C9 (0x6B,0x44) 0x44000200 0x00000036 0x00000000 0x00000000
+GPP_C10 (0x6B,0x46) 0x44000200 0x00000037 0x00000000 0x00000000
+GPP_C11 (0x6B,0x48) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_C12 (0x6B,0x4A) 0x44000200 0x00000039 0x00000000 0x00000000
+GPP_C13 (0x6B,0x4C) 0x44000200 0x0000003a 0x00000000 0x00000000
+GPP_C14 (0x6B,0x4E) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_C15 (0x6B,0x50) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_C16 (0x6B,0x52) 0x44000502 0x0000003d 0x00000000 0x00000000
+GPP_C17 (0x6B,0x54) 0x44000502 0x0000003e 0x00000000 0x00000000
+GPP_C18 (0x6B,0x56) 0x44000502 0x0000003f 0x00000000 0x00000000
+GPP_C19 (0x6B,0x58) 0x44000502 0x00000040 0x00000000 0x00000000
+GPP_C20 (0x6B,0x5A) 0x44000102 0x00000041 0x00000000 0x00000000
+GPP_C21 (0x6B,0x5C) 0x44000102 0x00000042 0x00000000 0x00000000
+GPP_C22 (0x6B,0x5E) 0x44000200 0x00000043 0x00000000 0x00000000
+GPP_C23 (0x6B,0x60) 0x44000200 0x00000044 0x00000000 0x00000000
+GPP_S0 (0x6A,0x00) 0x44000200 0x01800030 0x00000000 0x00000000
+GPP_S1 (0x6A,0x02) 0x44000200 0x01800031 0x00000000 0x00000000
+GPP_S2 (0x6A,0x04) 0x44000200 0x01800032 0x00000000 0x00000000
+GPP_S3 (0x6A,0x06) 0x44000200 0x01800033 0x00000000 0x00000000
+GPP_S4 (0x6A,0x08) 0x44000200 0x01800034 0x00000000 0x00000000
+GPP_S5 (0x6A,0x0A) 0x44000200 0x01800035 0x00000000 0x00000000
+GPP_S6 (0x6A,0x0C) 0x44000200 0x01800036 0x00000000 0x00000000
+GPP_S7 (0x6A,0x0E) 0x44000200 0x01800037 0x00000000 0x00000000
+GPP_E0 (0x6A,0x10) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_E1 (0x6A,0x12) 0x44000200 0x00000039 0x00000000 0x00000000
+GPP_E2 (0x6A,0x14) 0x44000200 0x0000003a 0x00000000 0x00000000
+GPP_E3 (0x6A,0x16) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_E4 (0x6A,0x18) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_E5 (0x6A,0x1A) 0x44000200 0x0000003d 0x00000000 0x00000000
+GPP_E6 (0x6A,0x1C) 0x44000200 0x0000003e 0x00000000 0x00000000
+GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
+GPP_E8 (0x6A,0x20) 0x44000500 0x00000040 0x00000000 0x00000000
+GPP_E9 (0x6A,0x22) 0x44000300 0x00000041 0x00000800 0x00000000
+GPP_E10 (0x6A,0x24) 0x44000300 0x00000042 0x00000800 0x00000000
+GPP_E11 (0x6A,0x26) 0x44000300 0x00000043 0x00000800 0x00000000
+GPP_E12 (0x6A,0x28) 0x44000300 0x00000044 0x00000000 0x00000000
+GPP_E13 (0x6A,0x2A) 0x44000200 0x00000045 0x00000000 0x00000000
+GPP_E14 (0x6A,0x2C) 0x44000200 0x00000046 0x00000000 0x00000000
+GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
+GPP_E16 (0x6A,0x30) 0x44000200 0x00000048 0x00000000 0x00000000
+GPP_E17 (0x6A,0x32) 0x44000200 0x00000049 0x00000000 0x00000000
+GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
+GPP_E19 (0x6A,0x36) 0x44000200 0x0000004b 0x00000000 0x00000000
+GPP_E20 (0x6A,0x38) 0x44000200 0x0000004c 0x00000000 0x00000000
+GPP_E21 (0x6A,0x3A) 0x44000200 0x0000004d 0x00000000 0x00000000
+GPP_K0 (0x6A,0x3E) 0x44000200 0x0000004e 0x00000000 0x00000000
+GPP_K1 (0x6A,0x40) 0x44000200 0x00000050 0x00000000 0x00000000
+GPP_K2 (0x6A,0x42) 0x44000200 0x00000051 0x00000000 0x00000000
+GPP_K3 (0x6A,0x44) 0x44000200 0x00000052 0x00000000 0x00000000
+GPP_K4 (0x6A,0x46) 0x44000200 0x00000053 0x00000000 0x00000000
+GPP_K5 (0x6A,0x48) 0x44000200 0x00000054 0x00000000 0x00000000
+GPP_K6 (0x6A,0x4A) 0x44000a02 0x00000055 0x00000000 0x00000000
+GPP_K7 (0x6A,0x4C) 0x44000a02 0x00000056 0x00000000 0x00000000
+GPP_K8 (0x6A,0x4E) 0x44000700 0x00000057 0x00000000 0x00000000
+GPP_K9 (0x6A,0x50) 0x44000700 0x00000058 0x00000000 0x00000000
+GPP_K10 (0x6A,0x52) 0x44000a02 0x00000059 0x00000000 0x00000000
+GPP_K11 (0x6A,0x54) 0x44000200 0x0000005a 0x00000000 0x00000000
+GPP_F0 (0x6A,0x5C) 0x44000200 0x0000005b 0x00000000 0x00000000
+GPP_F1 (0x6A,0x5E) 0x44000200 0x0000005c 0x00000000 0x00000000
+GPP_F2 (0x6A,0x60) 0x44000200 0x0000005d 0x00000000 0x00000000
+GPP_F3 (0x6A,0x62) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_F4 (0x6A,0x64) 0x44000200 0x00000060 0x00000000 0x00000000
+GPP_F5 (0x6A,0x66) 0x84000200 0x00000061 0x00000000 0x00000000
+GPP_F6 (0x6A,0x68) 0x44000200 0x00000062 0x00000000 0x00000000
+GPP_F7 (0x6A,0x6A) 0x44000200 0x00000063 0x00000000 0x00000000
+GPP_F8 (0x6A,0x6C) 0x44000100 0x00000064 0x00000000 0x00000000
+GPP_F9 (0x6A,0x6E) 0x42880102 0x00000065 0x00000000 0x00000000
+GPP_F10 (0x6A,0x70) 0x44000200 0x00000066 0x00000000 0x00000000
+GPP_F11 (0x6A,0x72) 0x44000200 0x00000067 0x00000000 0x00000000
+GPP_F12 (0x6A,0x74) 0x44000200 0x00000068 0x00000000 0x00000000
+GPP_F13 (0x6A,0x76) 0x44000200 0x00000069 0x00000000 0x00000000
+GPP_F14 (0x6A,0x78) 0x44000200 0x0000006a 0x00000000 0x00000000
+GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_F16 (0x6A,0x7C) 0x44000200 0x0000006c 0x00000000 0x00000000
+GPP_F17 (0x6A,0x7E) 0x44000200 0x0000006d 0x00000000 0x00000000
+GPP_F18 (0x6A,0x80) 0x44000200 0x0000006e 0x00000000 0x00000000
+GPP_F19 (0x6A,0x82) 0x44000700 0x0000006f 0x00000000 0x00000000
+GPP_F20 (0x6A,0x84) 0x44000700 0x00000070 0x00000000 0x00000000
+GPP_F21 (0x6A,0x86) 0x44000700 0x00000071 0x00000000 0x00000000
+GPP_F22 (0x6A,0x88) 0x44000201 0x00000072 0x00000000 0x00000000
+GPP_F23 (0x6A,0x8A) 0x44000200 0x00000073 0x00000000 0x00000000
+GPP_D0 (0x69,0x20) 0x44000200 0x00000026 0x00000000 0x00000000
+GPP_D1 (0x69,0x22) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_D2 (0x69,0x24) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_D3 (0x69,0x26) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_D4 (0x69,0x28) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_D5 (0x69,0x2A) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_D6 (0x69,0x2C) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_D7 (0x69,0x2E) 0x44000200 0x0000002d 0x00000000 0x00000000
+GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
+GPP_D9 (0x69,0x32) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D10 (0x69,0x34) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
+GPP_D13 (0x69,0x3A) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D14 (0x69,0x3C) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
+GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
+GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
+GPP_D22 (0x69,0x4C) 0x40000702 0x00000000 0x00000000 0x00000000
+GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+  vendor_name: Realtek
+  chip_name: ALC1220
+  vendor_id: 0x10ec1220
+  subsystem_id: 0x15583702
+  revision_id: 0x100101
+  0x12: 0x90a60130
+  0x14: 0x0421101f
+  0x15: 0x40000000
+  0x16: 0x411111f0
+  0x17: 0x411111f0
+  0x18: 0x04a11040
+  0x19: 0x411111f0
+  0x1a: 0x411111f0
+  0x1b: 0x90170110
+  0x1d: 0x40b7952d
+  0x1e: 0x04451150
+hdaudioC0D2
+  vendor_name: Intel
+  chip_name: Raptorlake HDMI
+  vendor_id: 0x80862818
+  subsystem_id: 0x80860101
+  revision_id: 0x100000
+  0x04: 0x18560010
+  0x06: 0x18560010
+  0x08: 0x18560010
+  0x0a: 0x18560010
+  0x0b: 0x18560010
+  0x0c: 0x18560010
+  0x0d: 0x18560010
+  0x0e: 0x18560010
+  0x0f: 0x18560010
+hdaudioC1D0
+  vendor_name: Nvidia
+  chip_name: Generic HDMI
+  vendor_id: 0x10de00a5
+  subsystem_id: 0x10de0000
+  revision_id: 0x100100
+  0x04: 0x585600f0
+  0x05: 0x185600f0
+  0x06: 0x185600f0
+  0x07: 0x185600f0
--- a/models/bonw15/coreboot.config
+++ b/models/bonw15/coreboot.config
@@ -0,0 +1,28 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_BONW15=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+CONFIG_HAVE_GBE_BIN=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_GBE_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/gbe.rom"
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
+CONFIG_POST_IO=n
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_V2=y
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
+
+# Custom FSP
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Fsp.fd"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Include"
+CONFIG_FSP_USE_REPO=n
--- a/models/bonw15/ec.config
+++ b/models/bonw15/ec.config
@@ -0,0 +1 @@
+BOARD=system76/bonw15
--- a/models/bonw15/ecspy.txt
+++ b/models/bonw15/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 6
+A0: data 1 mirror 1 pot 0 control 80
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 1 mirror 0 pot 0 control 00
+A3: data 0 mirror 0 pot 0 control 00
+A4: data 0 mirror 1 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 0 mirror 0 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 84
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 1 mirror 1 pot 0 control 40
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 40
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 40
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 0 mirror 0 pot 0 control 40
+D4: data 0 mirror 0 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 0 mirror 0 pot 0 control 02
+D7: data 1 mirror 1 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 1 mirror 1 pot 0 control 84
+E3: data 1 mirror 1 pot 0 control 40
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 0 mirror 0 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 40
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 1 mirror 1 pot 0 control 40
+F7: data 1 mirror 1 pot 0 control 80
+G0: data 1 mirror 1 pot 0 control 80
+G1: data 1 mirror 1 pot 0 control 40
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 0 mirror 0 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 0 mirror 0 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 1 mirror 1 pot 0 control 80
+H4: data 0 mirror 0 pot 0 control 80
+H5: data 0 mirror 0 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 40
+H7: data 1 mirror 1 pot 0 control 80
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 80
+I3: data 0 mirror 0 pot 0 control 00
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 1 mirror 1 pot 0 control 40
+I6: data 0 mirror 0 pot 0 control 00
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 1 mirror 1 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 40
+J5: data 1 mirror 1 pot 0 control 80
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 0 mirror 0 pot 0 control 84
+M0: data 0 mirror 0 control 06
+M1: data 0 mirror 0 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 1 control 06
+M5: data 0 mirror 0 control 00
+M6: data 0 mirror 0 control 86
+M7: data 0 mirror 0 control 00
--- a/models/bonw15/edk2.config
+++ b/models/bonw15/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/bonw15/fd.rom
+++ b/models/bonw15/fd.rom
--- a/models/bonw15/gpio.h
+++ b/models/bonw15/gpio.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD2, 0x42880100, 0x0000),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPI(GPD7, NONE, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD9, 0, PWROK),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD11, 0, DEEP),
+	PAD_CFG_GPO(GPD12, 0, DEEP),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+	PAD_CFG_GPO(GPP_A8, 0, DEEP),
+	PAD_CFG_GPO(GPP_A9, 0, DEEP),
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
+	PAD_CFG_GPO(GPP_A13, 0, DEEP),
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000),
+	PAD_CFG_GPO(GPP_B1, 0, DEEP),
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	PAD_CFG_GPO(GPP_B5, 0, DEEP),
+	PAD_CFG_GPO(GPP_B6, 0, DEEP),
+	PAD_CFG_GPO(GPP_B7, 0, DEEP),
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	PAD_CFG_GPO(GPP_B9, 0, DEEP),
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_CFG_GPO(GPP_B11, 0, DEEP),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 1, PWROK),
+	PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_CFG_GPO(GPP_B20, 0, DEEP),
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_C3, 0, DEEP),
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C6, 0, DEEP),
+	PAD_CFG_GPO(GPP_C7, 0, DEEP),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_C9, 0, DEEP),
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+	PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	PAD_CFG_GPO(GPP_C23, 0, DEEP),
+	PAD_CFG_GPO(GPP_D0, 0, DEEP),
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPO(GPP_D4, 0, DEEP),
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	PAD_CFG_GPO(GPP_D7, 0, DEEP),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	PAD_CFG_GPO(GPP_E1, 0, DEEP),
+	PAD_CFG_GPO(GPP_E2, 0, DEEP),
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	PAD_CFG_GPO(GPP_E5, 0, DEEP),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_GPO(GPP_E13, 0, DEEP),
+	PAD_CFG_GPO(GPP_E14, 0, DEEP),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	PAD_CFG_GPO(GPP_E17, 0, DEEP),
+	PAD_CFG_GPO(GPP_E18, 1, DEEP),
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	PAD_CFG_GPO(GPP_F0, 0, DEEP),
+	PAD_CFG_GPO(GPP_F1, 0, DEEP),
+	PAD_CFG_GPO(GPP_F2, 0, DEEP),
+	PAD_CFG_GPO(GPP_F3, 0, DEEP),
+	PAD_CFG_GPO(GPP_F4, 0, DEEP),
+	PAD_CFG_GPO(GPP_F5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F6, 0, DEEP),
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_F9, 0x42880100, 0x0000),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	PAD_CFG_GPO(GPP_F13, 0, DEEP),
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F22, 1, DEEP),
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),
+	PAD_CFG_GPO(GPP_G0, 0, PWROK),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_G7, 0x42800100, 0x0000),
+	PAD_CFG_GPI(GPP_H0, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPI(GPP_H2, NONE, DEEP),
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_NC(GPP_H6, NONE),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H17, 1, DEEP),
+	PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H19, 0, DEEP),
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	PAD_CFG_GPO(GPP_H21, 1, DEEP),
+	PAD_CFG_GPO(GPP_H22, 0, DEEP),
+	PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+	PAD_CFG_GPO(GPP_I0, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000),
+	PAD_CFG_GPO(GPP_I5, 0, DEEP),
+	PAD_CFG_GPO(GPP_I6, 0, DEEP),
+	PAD_CFG_GPO(GPP_I7, 0, DEEP),
+	PAD_CFG_GPO(GPP_I8, 0, DEEP),
+	PAD_CFG_GPO(GPP_I9, 0, DEEP),
+	PAD_CFG_GPO(GPP_I10, 0, DEEP),
+	PAD_NC(GPP_I11, NONE),
+	PAD_NC(GPP_I12, NONE),
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+	PAD_CFG_GPO(GPP_I15, 0, DEEP),
+	PAD_CFG_GPO(GPP_I16, 0, DEEP),
+	PAD_CFG_GPO(GPP_I17, 0, DEEP),
+	PAD_CFG_GPI(GPP_I18, NONE, DEEP),
+	PAD_CFG_GPO(GPP_I19, 0, DEEP),
+	PAD_CFG_GPO(GPP_I20, 0, DEEP),
+	PAD_CFG_GPO(GPP_I21, 0, DEEP),
+	PAD_CFG_GPI(GPP_I22, NONE, DEEP),
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_J8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_J9, 0, DEEP),
+	PAD_CFG_GPO(GPP_J10, 0, DEEP),
+	PAD_CFG_GPO(GPP_J11, 0, DEEP),
+	PAD_CFG_GPO(GPP_K0, 0, DEEP),
+	PAD_CFG_GPO(GPP_K1, 0, DEEP),
+	PAD_CFG_GPO(GPP_K2, 0, DEEP),
+	PAD_CFG_GPO(GPP_K3, 0, DEEP),
+	PAD_CFG_GPO(GPP_K4, 0, DEEP),
+	PAD_CFG_GPO(GPP_K5, 0, DEEP),
+	PAD_CFG_NF(GPP_K6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_K7, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
+	PAD_CFG_GPO(GPP_K11, 0, DEEP),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R5, 0, DEEP),
+	PAD_CFG_GPO(GPP_R6, 0, DEEP),
+	PAD_CFG_GPO(GPP_R7, 0, DEEP),
+	PAD_CFG_GPI(GPP_R8, NONE, DEEP),
+	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R10, 0, DEEP),
+	PAD_CFG_GPO(GPP_R11, 0, DEEP),
+	PAD_CFG_GPO(GPP_R12, 0, DEEP),
+	PAD_CFG_GPO(GPP_R13, 0, DEEP),
+	PAD_CFG_GPO(GPP_R14, 0, DEEP),
+	PAD_CFG_GPO(GPP_R15, 0, DEEP),
+	PAD_CFG_GPO(GPP_R16, 1, DEEP),
+	PAD_CFG_GPO(GPP_R17, 0, DEEP),
+	PAD_CFG_GPO(GPP_R18, 0, DEEP),
+	PAD_CFG_GPO(GPP_R19, 0, DEEP),
+	PAD_CFG_GPO(GPP_R20, 0, DEEP),
+	PAD_CFG_GPO(GPP_R21, 0, DEEP),
+	PAD_CFG_GPO(GPP_S0, 0, DEEP),
+	PAD_CFG_GPO(GPP_S1, 0, DEEP),
+	PAD_CFG_GPO(GPP_S2, 0, DEEP),
+	PAD_CFG_GPO(GPP_S3, 0, DEEP),
+	PAD_CFG_GPO(GPP_S4, 0, DEEP),
+	PAD_CFG_GPO(GPP_S5, 0, DEEP),
+	PAD_CFG_GPO(GPP_S6, 0, DEEP),
+	PAD_CFG_GPO(GPP_S7, 0, DEEP),
+};
+
+#endif
+
+#endif
--- a/models/bonw15/hda_verb.c
+++ b/models/bonw15/hda_verb.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15583702, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15583702),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+	/* Intel, RaptorlakeHDMI */
+	0x80862818, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+	/* Nvidia, GenericHDMI */
+	0x10de00a5, /* Vendor ID */
+	0x10de0000, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x10de0000),
+	AZALIA_PIN_CFG(0, 0x04, 0x585600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/models/bonw15/me.rom
+++ b/models/bonw15/me.rom
--- a/models/bonw15/vbt.rom
+++ b/models/bonw15/vbt.rom
--- a/models/darp5/edk2.config
+++ b/models/darp5/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp6/edk2.config
+++ b/models/darp6/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp7/README.md
+++ b/models/darp7/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 5116 KB
-  - Version: 15.0.35.2039
+  - Version: 15.0.41.2158
--- a/models/darp7/coreboot.config
+++ b/models/darp7/coreboot.config
@@ -2,8 +2,7 @@ CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP7=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
--- a/models/darp7/edk2.config
+++ b/models/darp7/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp7/me.rom
+++ b/models/darp7/me.rom
--- a/models/darp7/microcode.rom
+++ b/models/darp7/microcode.rom
--- a/models/darp8/FSP
+++ b/models/darp8/FSP
@@ -1 +0,0 @@
-../gaze17-3050/FSP
--- a/models/darp8/README.md
+++ b/models/darp8/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 4824 KB
-  - Version: 16.0.15.1810
+  - Version: 16.0.15.1829
--- a/models/darp8/coreboot.config
+++ b/models/darp8/coreboot.config
@@ -1,13 +1,8 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP8=y
-CONFIG_ADD_FSP_BINARIES=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
-CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include"
-CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp.fd"
-CONFIG_FSP_FULL_FD=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
--- a/models/darp8/edk2.config
+++ b/models/darp8/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/darp8/me.rom
+++ b/models/darp8/me.rom
--- a/models/darp8/microcode.rom
+++ b/models/darp8/microcode.rom
--- a/models/galp2/edk2.config
+++ b/models/galp2/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp3-b/edk2.config
+++ b/models/galp3-b/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp3-c/edk2.config
+++ b/models/galp3-c/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp3/edk2.config
+++ b/models/galp3/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp4/edk2.config
+++ b/models/galp4/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp5/README.md
+++ b/models/galp5/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 5116 KB
-  - Version: 15.0.35.2039
+  - Version: 15.0.41.2158
--- a/models/galp5/coreboot.config
+++ b/models/galp5/coreboot.config
@@ -2,8 +2,7 @@ CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP5=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
--- a/models/galp5/edk2.config
+++ b/models/galp5/edk2.config
@@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
-#SECURE_BOOT_ENABLE=TRUE
+SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
--- a/models/galp5/me.rom
+++ b/models/galp5/me.rom
--- a/models/galp5/microcode.rom
+++ b/models/galp5/microcode.rom
--- a/models/galp6/IntelGopDriver.efi
+++ b/models/galp6/IntelGopDriver.efi
--- a/models/galp6/IntelGopDriver.inf
+++ b/models/galp6/IntelGopDriver.inf
@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IntelGopDriver
+  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.X64]
+  PE32|IntelGopDriver.efi|*
--- a/models/galp6/README.md
+++ b/models/galp6/README.md
@@ -0,0 +1,12 @@
+# System76 Galago Pro (galp6)
+
+## Contents
+
+- [EC](./ec.rom)
+  - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+  - Size: 4 KB
+  - HAP: false
+- [ME](./me.rom)
+  - Size: 4824 KB
+  - Version: 16.0.15.1829
--- a/models/galp6/README.md.in
+++ b/models/galp6/README.md.in
@@ -0,0 +1 @@
+# System76 Galago Pro (galp6)
--- a/models/galp6/chip.txt
+++ b/models/galp6/chip.txt
@@ -0,0 +1 @@
+MX25L25635F/MX25L25645G
--- a/models/galp6/coreboot-collector.txt
+++ b/models/galp6/coreboot-collector.txt
@@ -0,0 +1,256 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x4621, Revision 0x02
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x4626, Revision 0x0C
+PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0x461D, Revision 0x02
+PCI Device: 0000:00:06.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:07.0: Class 0x00060400, Vendor 0x8086, Device 0x466E, Revision 0x02
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0x464F, Revision 0x02
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0x467D, Revision 0x01
+PCI Device: 0000:00:0d.0: Class 0x000C0330, Vendor 0x8086, Device 0x461E, Revision 0x02
+PCI Device: 0000:00:0d.2: Class 0x000C0340, Vendor 0x8086, Device 0x463E, Revision 0x02
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0x467F, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x51ED, Revision 0x01
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x51EF, Revision 0x01
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x51F0, Revision 0x01
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x51E8, Revision 0x01
+PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x51E9, Revision 0x01
+PCI Device: 0000:00:15.2: Class 0x000C8000, Vendor 0x8086, Device 0x51EA, Revision 0x01
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x51E0, Revision 0x01
+PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x51B0, Revision 0x01
+PCI Device: 0000:00:1d.1: Class 0x00060400, Vendor 0x8086, Device 0x51B1, Revision 0x01
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x5182, Revision 0x01
+PCI Device: 0000:00:1f.3: Class 0x00040380, Vendor 0x8086, Device 0x51C8, Revision 0x01
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x51A3, Revision 0x01
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x51A4, Revision 0x01
+PCI Device: 0000:2a:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
+PCI Device: 0000:2b:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
+PCI Device: 10000:e0:06.0: Class 0x00060400, Vendor 0x8086, Device 0x464D, Revision 0x02
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x15B7, Device 0x5019, Revision 0x01
+## GPIO ##
+600 Series PCH-LP
+GPP_B0 (0x6E,0x00) 0x44000700 0x0003c018 0x00000100 0x00000000
+GPP_B1 (0x6E,0x02) 0x44000700 0x0003c019 0x00000100 0x00000000
+GPP_B2 (0x6E,0x04) 0x44000200 0x0000001a 0x00000000 0x00000000
+GPP_B3 (0x6E,0x06) 0x44000102 0x0000001b 0x00000000 0x00000000
+GPP_B4 (0x6E,0x08) 0x44000102 0x0000001c 0x00000000 0x00000000
+GPP_B5 (0x6E,0x0A) 0x44000902 0x0000001d 0x00000000 0x00000000
+GPP_B6 (0x6E,0x0C) 0x44000902 0x0000001e 0x00000000 0x00000000
+GPP_B7 (0x6E,0x0E) 0x44000200 0x0000001f 0x00000000 0x00000000
+GPP_B8 (0x6E,0x10) 0x44000200 0x00000020 0x00000000 0x00000000
+GPP_B9 (0x6E,0x12) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_B10 (0x6E,0x14) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_B11 (0x6E,0x16) 0x04000702 0x00000023 0x00000000 0x00000000
+GPP_B12 (0x6E,0x18) 0x44000700 0x0003c024 0x00000000 0x00000000
+GPP_B13 (0x6E,0x1A) 0x44000700 0x0003c025 0x00000000 0x00000000
+GPP_B14 (0x6E,0x1C) 0x44000500 0x00000026 0x00000000 0x00000000
+GPP_B15 (0x6E,0x1E) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_B16 (0x6E,0x20) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_B17 (0x6E,0x22) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_B18 (0x6E,0x24) 0x44000102 0x0000002a 0x00000100 0x00000000
+GPP_B19 (0x6E,0x26) 0x44000200 0x0000002b 0x00000000 0x00000000
+GPP_B20 (0x6E,0x28) 0x44000200 0x0000002c 0x00000000 0x00000000
+GPP_B21 (0x6E,0x2A) 0x44000200 0x0000002d 0x00000000 0x00000000
+GPP_B22 (0x6E,0x2C) 0x44000200 0x0000002e 0x00000000 0x00000000
+GPP_B23 (0x6E,0x2E) 0x44000102 0x0000002f 0x00000000 0x00000000
+GPP_T2 (0x6E,0x38) 0x44000200 0x00000032 0x00000000 0x00000000
+GPP_T3 (0x6E,0x3A) 0x44000200 0x00000033 0x00000000 0x00000000
+GPP_A0 (0x6E,0x54) 0x44000700 0x0003f040 0x00000100 0x00000000
+GPP_A1 (0x6E,0x56) 0x44000702 0x0003f041 0x00000100 0x00000000
+GPP_A2 (0x6E,0x58) 0x44000700 0x0003f042 0x00000100 0x00000000
+GPP_A3 (0x6E,0x5A) 0x44000700 0x0003f043 0x00000100 0x00000000
+GPP_A4 (0x6E,0x5C) 0x44000700 0x0003f044 0x00000100 0x00000000
+GPP_A5 (0x6E,0x5E) 0x44000702 0x00003045 0x00000100 0x00000000
+GPP_A6 (0x6E,0x60) 0x44000200 0x00000046 0x00000100 0x00000000
+GPP_A7 (0x6E,0x62) 0x44000200 0x00000047 0x00000000 0x00000000
+GPP_A8 (0x6E,0x64) 0x44000200 0x00000048 0x00000000 0x00000000
+GPP_A9 (0x6E,0x66) 0x44000700 0x0003d049 0x00000100 0x00000000
+GPP_A10 (0x6E,0x68) 0x44000700 0x0003c04a 0x00000100 0x00000000
+GPP_A11 (0x6E,0x6A) 0x44000200 0x0000004b 0x00000000 0x00000000
+GPP_A12 (0x6E,0x6C) 0x44000102 0x0000004c 0x00000000 0x00000000
+GPP_A13 (0x6E,0x6E) 0x84000201 0x0000004d 0x00000000 0x00000000
+GPP_A14 (0x6E,0x70) 0x44000201 0x0000004e 0x00000000 0x00000000
+GPP_A15 (0x6E,0x72) 0x44000102 0x0000004f 0x00000000 0x00000000
+GPP_A16 (0x6E,0x74) 0x44000702 0x00000050 0x00000000 0x00000000
+GPP_A17 (0x6E,0x76) 0x80800102 0x00000051 0x00000000 0x00000000
+GPP_A18 (0x6E,0x78) 0x44000500 0x00024052 0x00000000 0x00000000
+GPP_A19 (0x6E,0x7A) 0x44000102 0x00000053 0x00000000 0x00000000
+GPP_A20 (0x6E,0x7C) 0x44000200 0x00000054 0x00000000 0x00000000
+GPP_A21 (0x6E,0x7E) 0x44000200 0x00000055 0x00000100 0x00000000
+GPP_A22 (0x6E,0x80) 0x84000201 0x00000056 0x00000000 0x00000000
+GPP_A23 (0x6E,0x82) 0x44000200 0x00000057 0x00000100 0x00000000
+GPP_S0 (0x6D,0x00) 0x44000200 0x0180006c 0x00000000 0x00000000
+GPP_S1 (0x6D,0x02) 0x44000200 0x0180006d 0x00000000 0x00000000
+GPP_S2 (0x6D,0x04) 0x44000200 0x0180006e 0x00000000 0x00000000
+GPP_S3 (0x6D,0x06) 0x44000200 0x0180006f 0x00000000 0x00000000
+GPP_S4 (0x6D,0x08) 0x44000200 0x01800070 0x00000000 0x00000000
+GPP_S5 (0x6D,0x0A) 0x44000200 0x01800071 0x00000000 0x00000000
+GPP_S6 (0x6D,0x0C) 0x44000200 0x01800072 0x00000000 0x00000000
+GPP_S7 (0x6D,0x0E) 0x44000200 0x01800073 0x00000000 0x00000000
+GPP_H0 (0x6D,0x10) 0x84000201 0x00000074 0x00000000 0x00000000
+GPP_H1 (0x6D,0x12) 0x44000102 0x00000075 0x00000000 0x00000000
+GPP_H2 (0x6D,0x14) 0x44000102 0x00000076 0x00000000 0x00000000
+GPP_H3 (0x6D,0x16) 0x44000102 0x00000077 0x00000000 0x00000000
+GPP_H4 (0x6D,0x18) 0x44000502 0x00000018 0x00000000 0x00000000
+GPP_H5 (0x6D,0x1A) 0x44000502 0x00000019 0x00000000 0x00000000
+GPP_H6 (0x6D,0x1C) 0x44000502 0x0000001a 0x00000000 0x00000000
+GPP_H7 (0x6D,0x1E) 0x44000502 0x0000001b 0x00000000 0x00000000
+GPP_H8 (0x6D,0x20) 0x44000902 0x0000001c 0x00000000 0x00000000
+GPP_H9 (0x6D,0x22) 0x44000900 0x0000001d 0x00000000 0x00000000
+GPP_H10 (0x6D,0x24) 0x44000902 0x0000001e 0x00000000 0x00000000
+GPP_H11 (0x6D,0x26) 0x44000900 0x0000001f 0x00000000 0x00000000
+GPP_H12 (0x6D,0x28) 0x44000200 0x00000020 0x00000000 0x00000000
+GPP_H13 (0x6D,0x2A) 0x44000200 0x00000021 0x00000000 0x00000000
+GPP_H14 (0x6D,0x2C) 0x44000200 0x00000022 0x00000000 0x00000000
+GPP_H15 (0x6D,0x2E) 0x44000500 0x0003c023 0x00000000 0x00000000
+GPP_H16 (0x6D,0x30) 0x44000200 0x00000024 0x00000000 0x00000000
+GPP_H17 (0x6D,0x32) 0x44000502 0x0003c025 0x00000000 0x00000000
+GPP_H18 (0x6D,0x34) 0x44000700 0x0003c026 0x00000000 0x00000000
+GPP_H19 (0x6D,0x36) 0x44000200 0x00000027 0x00000000 0x00000000
+GPP_H20 (0x6D,0x38) 0x44000102 0x00000028 0x00000000 0x00000000
+GPP_H21 (0x6D,0x3A) 0x44000200 0x00000029 0x00000000 0x00000000
+GPP_H22 (0x6D,0x3C) 0x44000200 0x0000002a 0x00000000 0x00000000
+GPP_H23 (0x6D,0x3E) 0x44000b02 0x0000002b 0x00000000 0x00000000
+GPP_D0 (0x6D,0x40) 0x44000201 0x0000002c 0x00000000 0x00000000
+GPP_D1 (0x6D,0x42) 0x44000102 0x0000002d 0x00000000 0x00000000
+GPP_D2 (0x6D,0x44) 0x44000200 0x0000002e 0x00000000 0x00000000
+GPP_D3 (0x6D,0x46) 0x44000200 0x0000002f 0x00000000 0x00000000
+GPP_D4 (0x6D,0x48) 0x44000200 0x00000030 0x00000000 0x00000000
+GPP_D5 (0x6D,0x4A) 0x44000700 0x00000031 0x00000000 0x00000000
+GPP_D6 (0x6D,0x4C) 0x44000200 0x00000032 0x00000000 0x00000000
+GPP_D7 (0x6D,0x4E) 0x44000702 0x00000033 0x00000000 0x00000000
+GPP_D8 (0x6D,0x50) 0x44000200 0x00000034 0x00000000 0x00000000
+GPP_D9 (0x6D,0x52) 0x44000200 0x00000035 0x00000100 0x00000000
+GPP_D10 (0x6D,0x54) 0x44000102 0x00003c36 0x00000100 0x00000000
+GPP_D11 (0x6D,0x56) 0x44000200 0x00000037 0x00000100 0x00000000
+GPP_D12 (0x6D,0x58) 0x44000102 0x00003c38 0x00000100 0x00000000
+GPP_D13 (0x6D,0x5A) 0x44000102 0x00000039 0x00000000 0x00000000
+GPP_D14 (0x6D,0x5C) 0x84000201 0x0000003a 0x00000000 0x00000000
+GPP_D15 (0x6D,0x5E) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_D16 (0x6D,0x60) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_D17 (0x6D,0x62) 0x44000200 0x0000003d 0x00000000 0x00000000
+GPP_D18 (0x6D,0x64) 0x44000200 0x0000003e 0x00000000 0x00000000
+GPP_D19 (0x6D,0x66) 0x44000200 0x0000003f 0x00000000 0x00000000
+GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000700 0x00003c61 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x04000102 0x00003c62 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000102 0x00000067 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x44000500 0x00000069 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x04000600 0x0000006b 0x00000000 0x00000000
+GPP_C0 (0x6A,0x00) 0x44000502 0x0003c06e 0x00000000 0x00000000
+GPP_C1 (0x6A,0x02) 0x44000502 0x0003c06f 0x00000000 0x00000000
+GPP_C2 (0x6A,0x04) 0x44000102 0x00000070 0x00000800 0x00000000
+GPP_C3 (0x6A,0x06) 0x44000502 0x00000071 0x00000000 0x00000000
+GPP_C4 (0x6A,0x08) 0x44000502 0x00000072 0x00000000 0x00000000
+GPP_C5 (0x6A,0x0A) 0x84000201 0x00000073 0x00000000 0x00000000
+GPP_C6 (0x6A,0x0C) 0x44000502 0x00000074 0x00000000 0x00000000
+GPP_C7 (0x6A,0x0E) 0x44000502 0x00000075 0x00000000 0x00000000
+GPP_C8 (0x6A,0x10) 0x44000300 0x00000076 0x00000000 0x00000000
+GPP_C9 (0x6A,0x12) 0x44000300 0x00000077 0x00000000 0x00000000
+GPP_C10 (0x6A,0x14) 0x44000300 0x00000018 0x00000000 0x00000000
+GPP_C11 (0x6A,0x16) 0x44000300 0x00000019 0x00000000 0x00000000
+GPP_C12 (0x6A,0x18) 0x44000300 0x0000001a 0x00000000 0x00000000
+GPP_C13 (0x6A,0x1A) 0x44000300 0x0000001b 0x00000000 0x00000000
+GPP_C14 (0x6A,0x1C) 0x44000300 0x0000001c 0x00000000 0x00000000
+GPP_C15 (0x6A,0x1E) 0x44000300 0x0000001d 0x00000000 0x00000000
+GPP_C16 (0x6A,0x20) 0x44000300 0x0000001e 0x00000000 0x00000000
+GPP_C17 (0x6A,0x22) 0x44000300 0x0000001f 0x00000000 0x00000000
+GPP_C18 (0x6A,0x24) 0x44000300 0x00000020 0x00000000 0x00000000
+GPP_C19 (0x6A,0x26) 0x44000300 0x00000021 0x00000000 0x00000000
+GPP_C20 (0x6A,0x28) 0x44000300 0x00000022 0x00000000 0x00000000
+GPP_C21 (0x6A,0x2A) 0x44000300 0x00000023 0x00000000 0x00000000
+GPP_C22 (0x6A,0x2C) 0x44000300 0x00000024 0x00000000 0x00000000
+GPP_C23 (0x6A,0x2E) 0x44000300 0x00000025 0x00000000 0x00000000
+GPP_F0 (0x6A,0x30) 0x44000500 0x0003c056 0x00000100 0x00000000
+GPP_F1 (0x6A,0x32) 0x44000502 0x0003f057 0x00000100 0x00000000
+GPP_F2 (0x6A,0x34) 0x44000500 0x0003c058 0x00000100 0x00000000
+GPP_F3 (0x6A,0x36) 0x44000500 0x0003f059 0x00000100 0x00000000
+GPP_F4 (0x6A,0x38) 0x44000500 0x0003c05a 0x00000100 0x00000000
+GPP_F5 (0x6A,0x3A) 0x44000900 0x0003c05b 0x00000100 0x00000000
+GPP_F6 (0x6A,0x3C) 0x44000502 0x0000005c 0x00000100 0x00000000
+GPP_F7 (0x6A,0x3E) 0x44000201 0x0000005d 0x00000000 0x00000000
+GPP_F8 (0x6A,0x40) 0x44000200 0x0000005e 0x00000000 0x00000000
+GPP_F9 (0x6A,0x42) 0x44000200 0x0000005f 0x00000000 0x00000000
+GPP_F10 (0x6A,0x44) 0x44000201 0x00000060 0x00000000 0x00000000
+GPP_F11 (0x6A,0x46) 0x44000102 0x00000061 0x00000000 0x00000000
+GPP_F12 (0x6A,0x48) 0x84000102 0x00000062 0x00000100 0x00000000
+GPP_F13 (0x6A,0x4A) 0x84000102 0x00000063 0x00000000 0x00000000
+GPP_F14 (0x6A,0x4C) 0x44000102 0x00000064 0x00000000 0x00000000
+GPP_F15 (0x6A,0x4E) 0x44000102 0x00000065 0x00000000 0x00000000
+GPP_F16 (0x6A,0x50) 0x44000201 0x00000066 0x00000100 0x00000000
+GPP_F17 (0x6A,0x52) 0x44000200 0x00000067 0x00000000 0x00000000
+GPP_F18 (0x6A,0x54) 0x44000200 0x00000068 0x00000000 0x00000000
+GPP_F19 (0x6A,0x56) 0x44000702 0x00000069 0x00000000 0x00000000
+GPP_F20 (0x6A,0x58) 0x84000201 0x0003c06a 0x00000000 0x00000000
+GPP_F21 (0x6A,0x5A) 0x44000200 0x0003c06b 0x00000000 0x00000000
+GPP_F22 (0x6A,0x5C) 0x44000200 0x0003c06c 0x00000000 0x00000000
+GPP_F23 (0x6A,0x5E) 0x44000200 0x0003c06d 0x00000000 0x00000000
+GPP_E0 (0x6A,0x6E) 0x44000102 0x00000026 0x00000000 0x00000000
+GPP_E1 (0x6A,0x70) 0x40100102 0x00003027 0x00000000 0x00000000
+GPP_E2 (0x6A,0x72) 0x44000200 0x00000028 0x00000000 0x00000000
+GPP_E3 (0x6A,0x74) 0x44000201 0x00000029 0x00000000 0x00000000
+GPP_E4 (0x6A,0x76) 0x84000200 0x00000030 0x00000000 0x00000000
+GPP_E5 (0x6A,0x78) 0x44000300 0x00000031 0x00000000 0x00000000
+GPP_E6 (0x6A,0x7A) 0x44000102 0x00000032 0x00000900 0x00000000
+GPP_E7 (0x6A,0x7C) 0x44000102 0x00000033 0x00000000 0x00000000
+GPP_E8 (0x6A,0x7E) 0x44000100 0x00000034 0x00000000 0x00000000
+GPP_E9 (0x6A,0x80) 0x44000502 0x00000035 0x00000800 0x00000000
+GPP_E10 (0x6A,0x82) 0x44000102 0x00000036 0x00000800 0x00000000
+GPP_E11 (0x6A,0x84) 0x44000102 0x00000037 0x00000800 0x00000000
+GPP_E12 (0x6A,0x86) 0x44000200 0x00000038 0x00000000 0x00000000
+GPP_E13 (0x6A,0x88) 0x44000100 0x00000039 0x00000000 0x00000000
+GPP_E14 (0x6A,0x8A) 0x44000702 0x0002403a 0x00000000 0x00000000
+GPP_E15 (0x6A,0x8C) 0x44000200 0x0000003b 0x00000000 0x00000000
+GPP_E16 (0x6A,0x8E) 0x44000200 0x0000003c 0x00000000 0x00000000
+GPP_E17 (0x6A,0x90) 0x44000100 0x0000003d 0x00000000 0x00000000
+GPP_E18 (0x6A,0x92) 0x44000300 0x00003c3e 0x00000000 0x00000000
+GPP_E19 (0x6A,0x94) 0x44000300 0x00003c3f 0x00000000 0x00000000
+GPP_E20 (0x6A,0x96) 0x44000200 0x00000040 0x00000100 0x00000000
+GPP_E21 (0x6A,0x98) 0x44000102 0x00003c41 0x00000100 0x00000000
+GPP_E22 (0x6A,0x9A) 0x44000200 0x00000042 0x00000000 0x00000000
+GPP_E23 (0x6A,0x9C) 0x44000200 0x00000043 0x00000000 0x00000000
+GPP_R0 (0x69,0x00) 0x44000500 0x0003c058 0x00000000 0x00000000
+GPP_R1 (0x69,0x02) 0x44000500 0x0003fc59 0x00000000 0x00000000
+GPP_R2 (0x69,0x04) 0x44000500 0x0003fc5a 0x00000000 0x00000000
+GPP_R3 (0x69,0x06) 0x44000500 0x0003fc5b 0x00000000 0x00000000
+GPP_R4 (0x69,0x08) 0x44000500 0x0003c05c 0x00000000 0x00000000
+GPP_R5 (0x69,0x0A) 0x44000102 0x0000005d 0x00000000 0x00000000
+GPP_R6 (0x69,0x0C) 0x44000102 0x0000005e 0x00000000 0x00000000
+GPP_R7 (0x69,0x0E) 0x44000102 0x0000005f 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+  vendor_name: Realtek
+  chip_name: ALC256
+  vendor_id: 0x10ec0256
+  subsystem_id: 0x15584041
+  revision_id: 0x100002
+  0x12: 0x90a60130
+  0x13: 0x40000000
+  0x14: 0x90170110
+  0x18: 0x411111f0
+  0x19: 0x411111f0
+  0x1a: 0x411111f0
+  0x1b: 0x411111f0
+  0x1d: 0x41700001
+  0x1e: 0x411111f0
+  0x21: 0x02211020
+hdaudioC0D2
+  vendor_name: Intel
+  chip_name: Alderlake-P HDMI
+  vendor_id: 0x8086281c
+  subsystem_id: 0x80860101
+  revision_id: 0x100000
+  0x04: 0x18560010
+  0x06: 0x18560010
+  0x08: 0x18560010
+  0x0a: 0x18560010
+  0x0b: 0x18560010
+  0x0c: 0x18560010
+  0x0d: 0x18560010
+  0x0e: 0x18560010
+  0x0f: 0x18560010
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Tim Crawford	799ed79449	coreboot: Fix USB2 on USB-C for gaze18, serw13 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-22 08:41:26 -06:00
Jeremy Soller	218f91800a	Update ec	2023-03-21 20:35:28 -06:00
Jeremy Soller	c1d8c59151	Update EC	2023-03-21 20:07:27 -06:00
Jeremy Soller	40f54be14d	Update coreboot	2023-03-21 19:56:40 -06:00
Jeremy Soller	fd8b7072e8	Update EC	2023-03-21 19:52:26 -06:00
Jeremy Soller	1b5efa53ea	Update coreboot and ec	2023-03-21 13:41:25 -06:00
Jeremy Soller	14b9fc4c58	Update coreboot	2023-03-20 08:14:46 -06:00
Jeremy Soller	80844605e5	Update coreboot	2023-03-17 09:12:09 -06:00
Jeremy Soller	24cf0f0ae5	Update EC	2023-03-15 12:41:56 -06:00
Jeremy Soller	bd32163194	Update coreboot	2023-03-10 13:29:41 -07:00
Tim Crawford	445579e2e9	ec: Fix gaze18 keyboard backlight Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-09 12:58:28 -07:00
Tim Crawford	c78ef82126	edk2: Update Secure Boot keys and DBX Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-09 12:57:55 -07:00
Tim Crawford	b1a5cb3bed	gaze18: Add edk2.config Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-09 12:57:12 -07:00
Jeremy Soller	16ea64a1a7	bonw15: disable BootGuard and PTT	2023-03-08 11:04:42 -07:00
Jeremy Soller	8d43f0b4ba	Add config files for bonw15	2023-03-08 11:01:23 -07:00
Jeremy Soller	60f6621a96	Add extract for bonw15	2023-03-08 10:45:59 -07:00
Jeremy Soller	7919bcf824	Update firmware-update	2023-03-07 12:48:17 -07:00
Jeremy Soller	35c3869e3e	Update firmware-setup	2023-03-07 12:28:42 -07:00
Tim Crawford	b8c0ab0f30	edk2: Add minimal UI for Secure Boot Enable SecureBootConfigDxe with a stripped down UI. It allows users to enable or disable Secure Boot and reset the key data to the defaults. That's it. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-07 10:22:09 -07:00
Tim Crawford	ec114b2385	edk2: Enable Secure Boot support This enables support for Secure Boot. It is not recommended to enable Secure Boot. There is no firmware UI for managing the state or keys. The system will default to disabled in Setup Mode: $ mokutil --sb-state SecureBoot disabled Platform is in Setup Mode This is sufficient to install Windows 11. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-07 10:22:09 -07:00
Jeremy Soller	8ad772a884	Update coreboot and ec	2023-03-07 10:01:40 -07:00
Jeremy Soller	4328edbcf0	Update EC	2023-03-07 10:01:40 -07:00
Jeremy Soller	9b3b018688	Update firmware-update	2023-03-07 10:01:40 -07:00
Jeremy Soller	b1268ce48e	Update EC	2023-03-07 10:01:40 -07:00
Jeremy Soller	a6787eb4b6	Update coreboot	2023-03-07 10:01:40 -07:00
Jeremy Soller	e4bec20de5	Update coreboot	2023-03-07 10:01:40 -07:00
Jeremy Soller	a88b0b1613	Firmware security support	2023-03-07 10:01:40 -07:00
Jeremy Soller	26b46f19be	Update firmware-setup	2023-03-06 16:21:08 -07:00
Jeremy Soller	eff504109c	Update EDK2	2023-03-06 15:02:08 -07:00
Jeremy Soller	be21f603b9	Update EC	2023-03-06 14:58:09 -07:00
Jeremy Soller	4ce7fd1954	Update firmware-update	2023-03-06 14:58:03 -07:00
Tim Crawford	9efa3f36e3	Update coreboot and EC Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-03-06 12:02:11 -07:00
Jeremy Soller	d9f3a8ed93	Update coreboot	2023-03-03 10:44:07 -07:00
Jeremy Soller	751c914811	Update EC	2023-03-03 09:58:07 -07:00
Jeremy Soller	a3f105acf6	Update ec	2023-03-03 09:31:19 -07:00
Jeremy Soller	1c8ba80e97	Update coreboot	2023-03-03 09:17:20 -07:00
Jeremy Soller	e70043ca8a	Update coreboot	2023-03-01 09:51:42 -07:00
Jeremy Soller	d69bd4c25d	addw3: add GBE firmware and update coreboot	2023-02-28 14:57:13 -07:00
Jeremy Soller	de333a0b52	Update EC	2023-02-28 12:25:20 -07:00
Jeremy Soller	a185e1c167	Update coreboot	2023-02-28 12:22:09 -07:00
Jeremy Soller	d73f99cf06	Update coreboot	2023-02-27 14:25:54 -07:00
Jeremy Soller	a379a4e446	Update coreboot	2023-02-27 13:44:12 -07:00
Jeremy Soller	c9f99efea0	Update coreboot	2023-02-27 13:01:32 -07:00
Jeremy Soller	57f4e45477	Update coreboot	2023-02-27 12:30:22 -07:00
Jeremy Soller	df3633fc66	Update coreboot	2023-02-27 12:16:35 -07:00
Jeremy Soller	04e309fb5a	Update coreboot	2023-02-27 11:52:25 -07:00
Jeremy Soller	5f72a75115	Update coreboot	2023-02-27 08:47:30 -07:00
Jeremy Soller	d92498355d	Update coreboot	2023-02-25 20:36:48 -07:00
Jeremy Soller	52a416abe5	Update EC	2023-02-24 15:27:16 -07:00
Jeremy Soller	70938f6a4b	Update EC	2023-02-22 21:02:10 -07:00
Jeremy Soller	45391317e5	Update coreboot	2023-02-22 19:07:31 -07:00
Jeremy Soller	a9a38cc709	Update coreboot and ec	2023-02-22 15:49:57 -07:00
Jeremy Soller	b1308d43a4	Update ec	2023-02-22 14:37:03 -07:00
Jeremy Soller	da09a291d7	Update coreboot	2023-02-22 14:32:26 -07:00
Jeremy Soller	2d5d0fdf04	Update coreboot and ec	2023-02-22 14:28:55 -07:00
Jeremy Soller	d6d7131609	Update coreboot	2023-02-22 12:57:12 -07:00
Jeremy Soller	abd244ea96	Update coreboot and ec	2023-02-22 12:41:37 -07:00
Jeremy Soller	41728698ce	Update firmware-update	2023-02-22 11:46:41 -07:00
Jeremy Soller	2dda038952	Use RPL-H FSP for oryp11	2023-02-22 11:31:13 -07:00
Tim Crawford	40f9305ce2	serw13: Fix symlink to FSP Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-22 10:21:11 -07:00
Tim Crawford	3f99789509	gaze18: Symlink FSP, add chip.txt Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-22 10:18:11 -07:00
Tim Crawford	40843fbf53	gaze18: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-22 09:54:22 -07:00
Jeremy Soller	4937a74306	Update coreboot	2023-02-22 08:17:29 -07:00
Jeremy Soller	e00ff92929	Update coreboot and ec	2023-02-22 08:09:34 -07:00
Jeremy Soller	9d7ef8fb3a	Apply model renames to configs and readmes	2023-02-22 08:09:24 -07:00
Jeremy Soller	24ae446ef4	Rename gaze18-3050 to gaze18	2023-02-22 08:06:02 -07:00
Jeremy Soller	403c82cd8e	Rename gaze18-40x0 to addw3	2023-02-22 08:05:47 -07:00
Jeremy Soller	c30161a28a	Rename addp3 to oryp11	2023-02-22 08:05:25 -07:00
Jeremy Soller	94e6d375fa	Rename oryp11 to serw13	2023-02-22 08:05:15 -07:00
Jeremy Soller	5a89066f02	Update coreboot and EC	2023-02-21 20:09:01 -07:00
Jeremy Soller	02b6c688e0	Update coreboot	2023-02-21 15:43:52 -07:00
Jeremy Soller	76299a9043	Update ec	2023-02-21 14:55:28 -07:00
Jeremy Soller	f90becc96f	Disable bootguard and PTT on addp3	2023-02-21 14:03:54 -07:00
Jeremy Soller	b28a954926	Add FSP and configs for addp3	2023-02-21 14:03:39 -07:00
Tim Crawford	c09333e944	Revert "gaze18-3050: Update CSME" This reverts commit `062ff0364b`. The RPL-HX tools were used to regenerate the CSME, but the RPL-P tools need to be used. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-21 13:46:44 -07:00
Jeremy Soller	f8659ec3e5	Add addp3 extract	2023-02-21 13:32:49 -07:00
Tim Crawford	062ff0364b	gaze18-3050: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-21 11:53:17 -07:00
Tim Crawford	ab7600f44d	coreboot: Drop RUN_FSP_GOP selection Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-16 10:37:01 -07:00
Jeremy Soller	20e5a30b8d	Update ec	2023-02-15 19:05:04 -07:00
Jeremy Soller	3c481f5385	Update coreboot	2023-02-15 16:18:47 -07:00
Jeremy Soller	e2e62c413b	Update coreboot	2023-02-13 15:35:36 -07:00
Jeremy Soller	3ee1f1b614	Update coreboot	2023-02-10 12:56:42 -07:00
Jeremy Soller	748ba007e0	Update coreboot	2023-02-10 12:44:32 -07:00
Jeremy Soller	8c761d7aed	Update ec	2023-02-10 12:25:18 -07:00
Jeremy Soller	db73252a07	Update coreboot	2023-02-10 12:23:14 -07:00
Tim Crawford	afe6fc5f73	oryp11: Add ec.config, symlink and use FSP Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-10 11:53:20 -07:00
Jeremy Soller	ba551a077c	Update EC	2023-02-10 10:59:52 -07:00
Jeremy Soller	d2a6191ec0	Update coreboot	2023-02-10 10:47:22 -07:00
Jeremy Soller	9b5cdd2841	Update intel-spi	2023-02-10 10:27:54 -07:00
Jeremy Soller	8913ab4aa8	Update firmware-update	2023-02-10 10:18:49 -07:00
Jeremy Soller	3aebb0423e	Update firmware-update	2023-02-10 10:06:21 -07:00
Jeremy Soller	0977863fef	Update coreboot	2023-02-10 09:39:57 -07:00
Tim Crawford	8e90fec1ea	oryp11: Add config files - Specify chip.txt for external flashing - Copy IntelGopDriver.inf so GOP is used - Copy edk2.config to build with correct configs Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-09 09:22:58 -07:00
Tim Crawford	ef2ddd819a	docs: Add section for smart amp to porting notes Document how to find the Realtek smart amp init data from the proprietary firmware image. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-08 15:00:48 -07:00
Tim Crawford	836cbb0720	oryp11: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-08 13:07:19 -07:00
Tim Crawford	e74b939c4b	Add coreboot configs for oryp11, gaze18-3050 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-08 09:54:08 -07:00
Jeremy Soller	fc2979310b	Update coreboot	2023-02-08 08:28:11 -07:00
Jeremy Soller	02f8ee9934	Update coreboot	2023-02-08 08:15:28 -07:00
Jeremy Soller	6996a4cc89	Add FSP for gaze18-40x0	2023-02-07 15:58:22 -07:00
Jeremy Soller	69e429e2b4	Add chip.txt for gaze18	2023-02-07 15:37:47 -07:00
Jeremy Soller	7d984696d0	Disable bootguard for gaze18	2023-02-07 15:37:39 -07:00
Jeremy Soller	bbbafdea1f	Fix compilation of edk2	2023-02-07 14:34:11 -07:00
Jeremy Soller	00df2028b7	Update coreboot and add gaze18-40x0 configs	2023-02-07 14:33:57 -07:00
Tim Crawford	bd4b768ef2	models: Add oryp11 blobs Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-03 11:22:33 -07:00
Tim Crawford	d5001a6b6f	models: Add oryp11 extract Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-03 11:20:04 -07:00
Jeremy Soller	7775e64b6a	Add gaze18-40x0 extract	2023-02-02 09:29:13 -07:00
Jeremy Soller	5c5ab76c47	Update coreboot-collector	2023-02-02 09:27:59 -07:00
Jeremy Soller	78f21bab79	Update coreboot-collector	2023-02-02 08:49:34 -07:00
Tim Crawford	09c761ca68	models: Add gaze18-3050 dump Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-01 12:07:07 -07:00
Tim Crawford	56994a28fc	modeltool: Update edition, deps Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-02-01 12:06:10 -07:00
Tim Crawford	b337ac66fb	ec: Fix WLAN power on Configure WLAN GPIOs at the correct point so they are enabled at boot. Fixes: `5f1ef1731e` ("ec: Fix power off issues on ADL and TGL") Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-21 10:01:00 -07:00
Tim Crawford	5f1ef1731e	ec: Fix power off issues on ADL and TGL - adl-p: Fix case where system gets stuck in S5 due to power loss - tgl-u: Fix case where system gets stuck in S5 due to power loss - galp5: Fix power off failing due to WLAN GPIO Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-18 09:16:22 -07:00
Tim Crawford	5e1da18565	ec: Apply PMC hack to all ADL boards For some reason, all the ADL boards are now failing to enter S0ix. Apply the PMC hack to the remaining ADL boards. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-18 07:45:49 -07:00
Tim Crawford	b3f0b544d7	Ask for kernel version for bug reports Issues may depend on changes that happened in the kernel, such as: - TBT using software CM instead of firmware CM - TGL GPIO communities changing to match Windows - Removal of `intel_backlight` Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-17 11:51:35 -07:00
Tim Crawford	addd02860a	Update Rust toolchain to 2022-03-18 Match the toolchain used by Redox. Update firmware-setup and firmware-update for using the new toolchain. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-16 09:39:05 -07:00
Tim Crawford	7291bc7d39	coreboot: Disable SATA DevSlp on S0ix boards After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0#, DevSlp blocks S0ix entry. Disable it for now on TGL-U and ADL-P. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-14 13:21:45 -07:00
Tim Crawford	13d410e6e1	coreboot: Fix ACPI brightness controls on ADL Hook up GMA ACPI brightness controls for ADL and set the gfx register for ADL boards. Fixes backlight controls on Windows 10 and Linux 6.1. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-10 14:23:12 -07:00
Tim Crawford	ec7f2adb2e	changelog: Use past tense Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-04 17:24:51 -06:00
Tim Crawford	4718ec4b3e	coreboot: Remove CPU PCIe RP RTD3 configs Remove CPU PCIe RP RTD3 config on TGL-U and ADL-P. Fixes suspend with some drives, such as WD Blue. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-11-02 15:45:02 -06:00
Tim Crawford	b39e1944a5	lemp11: Apply PMC hack to fix S0ix Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-10-17 18:43:49 -06:00
Tim Crawford	4136ef8f2b	ec: Fix KB backlight color with custom values Reload PWM counters when they reach 0 instead of immediately. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-10-14 10:16:47 -06:00
Tim Crawford	28f94e2d84	lemp11: Remove CARD RTD3 config Fixes board failing to reach S0ix most of the time. lemp11 still sometimes fails to reach C10, but plugging/removing AC adapter still works to fix it. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-10-11 17:16:40 -06:00
Tim Crawford	91a491fb95	ec: Fix charger values - charger: Limit charger values to max valid value - charger/bq24780s: Set RSENSE ratio option - charger/bq24780s: Fix charge current mask - oryp[5-8]: Reduce charge current to 2A Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-10-10 10:09:32 -06:00
Jeremy Soller	aa797d2e00	Update coreboot	2022-09-26 12:11:14 -06:00
Tim Crawford	5a479a20c8	coreboot: Fix brightness controls The `gfx` register got dropped during some rebase. Add them back. Fixes brightness controls on Windows for oryp8, gaze16, lemp9. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-09-23 15:56:01 -06:00
Tim Crawford	f64430a6b1	models: Remove thelio-b1 This model could not be ported, and so was never supported. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-09-23 12:28:57 -06:00
leviport	74e75ff8e4	Merge pull request #350 from system76/oryp9-b Add oryp10	2022-09-07 12:49:21 -06:00
Tim Crawford	3e594a6d4b	Update EC - Fix signal used to detect S0ix - Fix value to start/stop charging at Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-09-07 11:30:52 -06:00
Tim Crawford	280f061470	oryp10: Update CSME - Disable Boot Guard - Disable PTT - Disable locking the descriptor Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-09-06 09:48:49 -06:00
Tim Crawford	1169a60ca5	oryp10: Add Oryx Pro 10 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-09-06 09:48:49 -06:00
Tim Crawford	87b0a4903c	scripts: Build crossgcc with multiple cores Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-09-01 16:23:31 -06:00
Tim Crawford	161895da77	scripts: Install deps without confirmation This makes `dep.sh` usable from CI. Also update the package lists before installing on debian/ubuntu. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-29 12:55:07 -06:00
Tim Crawford	7160b01929	scripts: Install Rust with stable toolchain The trick of using `show` to install components requires a default toolchain be set. Assume users with Rust installed already have one set, and use stable for new installs. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-29 10:10:34 -06:00
Tim Crawford	9754d7d8a9	scripts: Drop some unneeded deps - coreboot no longer requires Python 2 for the FSP - nasm is provided by the coreboot toolchain Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-29 10:10:34 -06:00
Tim Crawford	f311c8b10f	scripts: Build coreboot toolchain as part of deps Front load building the toolchain binaries when installing deps instead of during the first board build. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-29 10:10:34 -06:00
Tim Crawford	42814e6e5c	scripts: Build edk2 using coreboot toolchain Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-29 10:10:34 -06:00
leviport	2680d93538	docs (flashing): Remove chip package info (#348 ) Since there are now two different chip package types used in our laptops, mentioning only one may cause confusion.	2022-08-12 13:42:42 -06:00
Tim Crawford	ba68c9901c	coreboot: Fix intel-microcode submodule Intel rewrote the git history for the new release. Use the tagged commit for the microcode-20220510 release to fix clones. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-10 12:36:10 -06:00
Tim Crawford	1c03ebeba9	Update CSME for TGL-H and TGL-U to 15.0.41.2158v2 - TGL-U ID: 729569 - TGL-H ID: 729571 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-10 12:36:10 -06:00
Tim Crawford	26f97c8d88	galp6: Add support for new board - Update submodules to support the new board - Add board to list of supported models Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-03 17:29:54 -06:00
Tim Crawford	db2a47337a	galp6: Update CSME Disable Boot Guard, PTT, and locking of the descriptor. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-03 17:29:54 -06:00
Daniel Sutton	6a97accff4	galp6: Add Galago Pro 6	2022-08-03 17:29:54 -06:00
Tim Crawford	302c1eedd6	Update CSME for ADL-P to 16.0.15.1810v8 - ID: 735206 - Updated: 2022-06-23 - Version: 16.0.15.1810v8 ADL-P The reported version is 16.0.15.1829. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-03 17:29:54 -06:00
Tim Crawford	6d4ccd9aeb	changelog: Add some missing details The coreboot rebase for gaze17 brought in a lot of fixes for other boards. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-03 17:29:54 -06:00
Tim Crawford	6ff4ccfbcb	coreboot: rebase on 37bf8c6dd590 Update coreboot and switch boards to use public releases of blobs. - TGL-U microcode: revision 0xa4 - TGL-H microcode: revision 0x3e - ADL microcode: revision 0x41c - ADL FSP: C.0.69.74 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-08-03 17:29:54 -06:00
John Wiggins	7e4a92c854	Merge pull request #339 from system76/spipi-update Set spipi to new name instead of IP address	2022-07-27 12:28:59 -06:00
John Wiggins	584bc40189	Set spipi to new name instead of IP address Improved config script so the spipi config file doesn't have to be updated with the IP address of the raspberry pi.	2022-07-27 12:20:29 -06:00
Tim Crawford	00cebe9042	gaze17-3050: Update 3050 variant - Update EC and coreboot to support the new board - Update README and CHANGELOG with the new board - Add `chip.txt` to allow external flashing Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-27 10:12:02 -06:00
Tim Crawford	46d6040dbd	gaze17-3050: Update CSME Disable Boot Guard, PTT, and locking of the descriptor. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-27 10:12:02 -06:00
Tim Crawford	2e133ed72e	docs: Add things to dump before porting Information required for porting may not be in the schematics and require inspection while running the proprietary firmware. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-27 10:12:02 -06:00
Tim Crawford	ae6aa72ceb	oryp9: Fix power off on battery power, sync fans Adjust power limits to prevent the system powering off while compiling the kernel on battery power in NVIDIA graphics mode. Sync CPU and GPU fans to mitigate thermal issues. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-20 16:17:25 -06:00
Tim Crawford	8b8344ac6c	changelog: Add oryp9, update darp8 and lemp11 The lemp11 fix was released as the original firmware. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-13 14:12:17 -06:00
Tim Crawford	db6deb884a	readme: Add ADL boards to supported models Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-13 14:12:17 -06:00
Tim Crawford	966f29601b	oryp9: Update CSME Disable Boot Guard, PTT, and locking of the descriptor. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-13 14:12:17 -06:00
Tim Crawford	132e3ab1f3	oryp9: Add Oryx Pro 9 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-13 14:12:17 -06:00