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coreboot: Disable SATA DevSlp on S0ix boards

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After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0#,
DevSlp blocks S0ix entry. Disable it for now on TGL-U and ADL-P.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-11-14 12:57:49 -07:00
committed by Tim Crawford
parent 13d410e6e1
commit 7291bc7d39
2 changed files with 4 additions and 2 deletions
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CHANGELOG.md
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@ -4,12 +4,14 @@ Changes are identified by the date of the released firmware including them. If
you are running System76 Open Firmware, opening the boot menu will show this
date followed by an underscore and a short git revision.
## 2022-11-10
## 2022-11-14
- lemp11: Added workaround to force S0ix entry on suspend
- tgl-u: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives
- adl-p: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives
- adl-p: Fixed ACPI brightness controls on Windows 10 and Linux 6.1
- adl-p: Disabled SATA DevSlp to fix S0ix entry
- tgl-u: Disabled SATA DevSlp to fix S0ix entry
## 2022-10-14

2
coreboot

Submodule coreboot updated: 923476d15a...421b2ecbb0