50 lines
2.1 KiB
C
50 lines
2.1 KiB
C
/** @file
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Header file for SMBIOS Cache Info HOB
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@copyright
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Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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System Management BIOS (SMBIOS) Reference Specification v3.1.0
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dated 2016-Nov-16 (DSP0134)
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http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
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**/
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#ifndef _SMBIOS_CACHE_INFO_HOB_H_
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#define _SMBIOS_CACHE_INFO_HOB_H_
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#include <Uefi.h>
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#include <Pi/PiHob.h>
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#pragma pack(1)
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///
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/// SMBIOS Cache Info HOB Structure
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///
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typedef struct {
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UINT16 ProcessorSocketNumber;
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UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
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UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
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UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
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UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
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UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
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UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
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UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
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UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
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UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
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UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
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UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
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//
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// Add for smbios 3.1.0
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//
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UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
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UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
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/**
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String Buffer - each string terminated by NULL "0x00"
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String buffer terminated by double NULL "0x0000"
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**/
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} SMBIOS_CACHE_INFO;
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#pragma pack()
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#endif // _SMBIOS_CACHE_INFO_HOB_H_
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