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soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter

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Tested on system76 galp3-c

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e
This commit is contained in:
Jeremy Soller
2019-02-20 16:33:33 -07:00
parent 946ecabd31
commit 00b535505d
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/cannonlake/fsp_params.c
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@ -219,6 +219,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = config->clock_gate_8254;
params->Enable8254ClockGatingOnS3 = config->clock_gate_8254;
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));