Merge remote-tracking branch 'upstream/master' into galp5

Change-Id: Idb9f8389e2f1b16091f06f2a786e44968b566be3

.gitignore

@@ -1,6 +1,3 @@
-payloads/libpayload/install/
-payloads/nvramcui/build
-payloads/nvramcui/libpayload
 junit.xml
 abuild*.xml
 .config
@@ -11,46 +8,8 @@ defconfig
 .ccwrap
 build/
 coreboot-builds/
-payloads/coreinfo/lpbuild/
+coreboot-builds*/
-payloads/coreinfo/lp.config*
+
-payloads/external/depthcharge/depthcharge/
-payloads/external/FILO/filo/
-payloads/external/GRUB2/grub2/
-payloads/external/LinuxBoot/linuxboot/
-payloads/external/SeaBIOS/seabios/
-payloads/external/tianocore/tianocore/
-payloads/external/tint/tint/
-payloads/external/U-Boot/u-boot/
-payloads/external/Memtest86Plus/memtest86plus/
-payloads/external/iPXE/ipxe/
-util/crossgcc/acpica-unix-*/
-util/crossgcc/binutils-*/
-util/crossgcc/build-*BINUTILS/
-util/crossgcc/build-*EXPAT/
-util/crossgcc/build-*GCC/
-util/crossgcc/build-*GDB/
-util/crossgcc/build-*GMP/
-util/crossgcc/build-*LIBELF/
-util/crossgcc/build-*MPC/
-util/crossgcc/build-*MPFR/
-util/crossgcc/build-*PYTHON/
-util/crossgcc/build-*LVM/
-util/crossgcc/build-*IASL/
-util/crossgcc/expat-*/
-util/crossgcc/gcc-*/
-util/crossgcc/gdb-*/
-util/crossgcc/gmp-*/
-util/crossgcc/libelf-*/
-util/crossgcc/mingwrt-*/
-util/crossgcc/mpc-*/
-util/crossgcc/mpfr-*/
-util/crossgcc/Python-*/
-util/crossgcc/*.src/
-util/crossgcc/tarballs/
-util/crossgcc/w32api-*/
-util/crossgcc/xgcc/
-util/crossgcc/xgcc-*/
-util/crossgcc/xgcc
 site-local
 
 *.\#
@@ -66,7 +25,8 @@ site-local
 *.pyc
 *.sw[po]
 /*.rom
-coreboot-builds*/
+.test
+.dependencies
 
 # Development friendly files
 tags
@@ -76,60 +36,9 @@ tags
 xgcc/
 tarballs/
 
-#
+# editor backup files, temporary files, IDE project files
-# KDE editors create lots of backup files whenever
-# a file is edited, so just ignore them
 *~
 *.kate-swp
-# Ignore Kdevelop project file
 *.kdev4
 
-util/*/.dependencies
-util/*/.test
-util/amdfwtool/amdfwtool
-util/archive/archive
-util/bincfg/bincfg
-util/board_status/board-status
-util/bucts/bucts
-util/cbfstool/cbfs-compression-tool
-util/cbfstool/cbfstool
-util/cbfstool/fmaptool
-util/cbfstool/ifwitool
-util/cbfstool/rmodtool
-util/cbmem/.dependencies
-util/cbmem/cbmem
-util/ectool/ectool
-util/futility/futility
-util/genprof/genprof
-util/getpir/getpir
-util/ifdtool/ifdtool
-util/intelmetool/intelmetool
-util/inteltool/.dependencies
-util/inteltool/inteltool
-util/intelp2m/intelp2m
-util/intelp2m/generate/gpio.h
-util/intelvbttool/intelvbttool
-util/msrtool/Makefile
-util/msrtool/Makefile.deps
-util/msrtool/msrtool
-util/nvramtool/.dependencies
-util/nvramtool/nvramtool
-util/pmh7tool/pmh7tool
-util/runfw/googlesnow
-util/superiotool/superiotool
-util/vgabios/testbios
-util/autoport/autoport
-util/kbc1126/kbc1126_ec_dump
-util/kbc1126/kbc1126_ec_insert
-util/spd_tools/*/gen_spd
-util/spd_tools/*/gen_part_id
-
-Documentation/*.aux
-Documentation/*.idx
-Documentation/*.log
-Documentation/*.toc
-Documentation/*.out
-Documentation/*.pdf
-Documentation/_build
-
 doxygen/*

Documentation/.gitignore

@@ -0,0 +1,7 @@
+*.aux
+*.idx
+*.log
+*.toc
+*.out
+*.pdf
+_build

Documentation/lib/fw_config.md

@@ -73,18 +73,18 @@ return true.
 
 ## Firmware Configuration Value
 
-The 32bit value used as the firmware configuration bitmask is meant to be determined at runtime
+The 64-bit value used as the firmware configuration bitmask is meant to be determined at runtime
 but could also be defined at compile time if needed.
 
 There are two supported sources for providing this information to coreboot.
 
 ### CBFS
 
-The value can be provided with a 32bit raw value in CBFS that is read by coreboot.  The value
+The value can be provided with a 64-bit raw value in CBFS that is read by coreboot.  The value
 can be set at build time but also adjusted in an existing image with `cbfstool`.
 
 To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a
-raw 32bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`.
+raw 64-bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`.
 
 When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified
 file in CBFS use the value it contains when matching fields and options.
@@ -291,8 +291,8 @@ field and option to check.
 struct fw_config {
 	const char *field_name;
 	const char *option_name;
-	uint32_t mask;
+	uint64_t mask;
-	uint32_t value;
+	uint64_t value;
 };
 ```
 

Documentation/mainboard/purism/librem_mini.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [Purism Librem Mini].
 
 ```eval_rst
 +------------------+--------------------------------------------------+
-| CPU              | Intel Core i7-8565U                              |
+| CPU              | Intel Core i7-8565U/8665U                        |
 +------------------+--------------------------------------------------+
 | PCH              | Whiskey Lake / Cannon Point LP                   |
 +------------------+--------------------------------------------------+
@@ -91,14 +91,15 @@ desoldering it from the mainboard.
 ## Known issues
 
  * SeaBIOS can be finicky with detecting USB devices
- * Booting can sometimes hang when a bootsplash image is used with SeaBIOS
+ * Mode switching with VGA option ROM display init can be slow and sometimes hangs
-   and VGA option ROM display init, related to display mode changing
+ * Some SATA devices on the 2.5" interface can have issues operating at 6 Gbps,
- * Issues with some SATA devices have been mitigated by limiting the SATA speed to 3Gbps
+   despite the HSIO PHY settings being set optimally via experimentation. These devices
-   until the correct HSIO PHY settings can be determined.
+   may show errors in dmesg and drop down to 3 Gbps, but should not fail to boot.
+   The same issue is present on the AMI vendor firmware.
 
 ## Working
 
- * External displays via HDMI/DislpayPort with VGA option ROM or FSP/GOP init
+ * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
   (no libgfxinit support yet)
  * SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi

MAINTAINERS

@@ -694,8 +694,13 @@ OPTION ROM EXECUTION & X86EMU
 F:	src/device/oprom/
 
 CBFS
-F:	src/include/cbfs.h
+M:	Julius Werner <jwerner@chromium.org>
-F:	src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
+F:	src/include/cbfs*
+F:	src/commonlib/bsd/include/commonlib/bsd/cbfs*
+F:	src/commonlib/bsd/cbfs*
+F:	src/lib/cbfs.c
+
+CBFSTOOL
 F:	util/cbfstool/
 
 CBMEM

Makefile

@@ -440,10 +440,10 @@ doxygen_simple:
 doxyplatform doxygen_platform: $(obj)/project_filelist.txt
 	echo
 	echo "Building doxygen documentation for $(CONFIG_MAINBOARD_PART_NUMBER)"
-	export DOXYGEN_OUTPUT_DIR="$(DOXYGEN_OUTPUT_DIR)/$(CONFIG_MAINBOARD_VENDOR)/$(CONFIG_MAINBOARD_PART_NUMBER)"; \
+	export DOXYGEN_OUTPUT_DIR="$$( echo $(DOXYGEN_OUTPUT_DIR)/$(call strip_quotes, $(CONFIG_MAINBOARD_VENDOR))_$(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER)) | sed 's|[^A-Za-z0-9/]|_|g' )"; \
 	mkdir -p "$$DOXYGEN_OUTPUT_DIR"; \
 	export DOXYFILES="$$(cat $(obj)/project_filelist.txt | grep -v '\.ld$$' | sed 's/\.aml/\.dsl/' | tr '\n' ' ')"; \
-	export DOXYGEN_PLATFORM="$(CONFIG_MAINBOARD_DIR) ($(CONFIG_MAINBOARD_PART_NUMBER)) version $(KERNELVERSION)"; \
+	export DOXYGEN_PLATFORM="$(call strip_quotes, $(CONFIG_MAINBOARD_DIR)) \($(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER))\) version $(KERNELVERSION)"; \
 	$(DOXYGEN) Documentation/doxygen/Doxyfile.coreboot_platform
 
 doxyclean: doxygen-clean

configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100

@@ -1,4 +1,7 @@
-# Not meant for actual use. Exercises, among other things:
+# Not meant for actual use, but rather to build-test individual options.
+# If keeping this combination of options buildable becomes too hard in
+# the future, then this config can be split into several smaller chunks.
+# Exercises, among other things:
 # + Code coverage
 # + UBSAN
 # + Debug options
@@ -6,6 +9,7 @@
 # + Silicon Image SIL3114 driver
 # + Genesys Logic GL9763E driver
 # + EM100 support
+# + SMM module loader V2
 CONFIG_COVERAGE=y
 CONFIG_UBSAN=y
 CONFIG_VENDOR_ASROCK=y
@@ -41,4 +45,5 @@ CONFIG_DEBUG_COVERAGE=y
 CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
 CONFIG_HAVE_EM100_SUPPORT=y
+CONFIG_X86_SMM_LOADER_VERSION2=y
 CONFIG_EM100=y

configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi

@@ -0,0 +1,41 @@
+# Not meant for actual use, but rather to build-test individual options.
+# If keeping this combination of options buildable becomes too hard in
+# the future, then this config can be split into several smaller chunks.
+# Exercises, among other things:
+# + SMMSTORE
+# + OXPCIE support
+# + FSP MP init
+# + EM100Pro SPI console
+# + Debug options
+CONFIG_VENDOR_PORTWELL=y
+CONFIG_CONSOLE_POST=y
+# CONFIG_CONSOLE_SERIAL is not set
+CONFIG_ENABLE_BUILTIN_COM1=y
+CONFIG_ONBOARD_MEM_KINGSTON=y
+CONFIG_USE_INTEL_FSP_MP_INIT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y
+CONFIG_SOC_INTEL_DEBUG_CONSENT=y
+CONFIG_PCIEXP_HOTPLUG=y
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
+CONFIG_SOFTWARE_I2C=y
+CONFIG_SMMSTORE=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+CONFIG_DRIVERS_UART_OXPCIE=y
+CONFIG_DRIVERS_GENESYSLOGIC_GL9755=y
+CONFIG_DISPLAY_HOBS=y
+CONFIG_DISPLAY_VBT=y
+CONFIG_DISPLAY_FSP_ENTRY_POINTS=y
+CONFIG_DISPLAY_UPD_DATA=y
+CONFIG_EM100PRO_SPI_CONSOLE=y
+CONFIG_DISPLAY_MTRRS=y
+CONFIG_GDB_STUB=y
+CONFIG_GDB_WAIT=y
+CONFIG_FATAL_ASSERTS=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_SMBUS=y
+CONFIG_DEBUG_SMI=y
+CONFIG_DEBUG_PERIODIC_SMI=y
+CONFIG_DEBUG_MALLOC=y
+CONFIG_DEBUG_CONSOLE_INIT=y
+CONFIG_REALMODE_DEBUG=y
+CONFIG_DEBUG_BOOT_STATE=y

payloads/coreinfo/.gitignore

@@ -0,0 +1,2 @@
+lpbuild/
+lp.config*

payloads/coreinfo/Kconfig

@@ -42,6 +42,15 @@ config PAYLOAD_INFO_VERSION
 	help
 	  The version number of this payload.
 
+config LTO
+	bool "Use link time optimization (LTO)"
+	default n
+	help
+	  Compile with link time optimization. This can often decrease the
+	  final binary size, but may increase compilation time. This option
+	  is most effective when LTO is also enabled in libpayload, which
+	  is done separately.
+
 endmenu
 
 menu "Modules"

payloads/coreinfo/Makefile

@@ -76,9 +76,13 @@ ifneq ($(strip $(HAVE_DOTCONFIG)),)
 include $(src)/.config
 real-all: $(TARGET)
 
+ifeq ($(CONFIG_LTO),y)
+CFLAGS += -flto
+endif
+
 $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload
 	printf "    LPCC       $(subst $(CURDIR)/,,$(@)) (LINK)\n"
-	$(LPCC) -o $@ $(OBJS)
+	$(LPCC) $(CFLAGS) -o $@ $(OBJS)
 	$(OBJCOPY) --only-keep-debug $@ $(TARGET).debug
 	$(OBJCOPY) --strip-debug $@
 	$(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@

payloads/external/.gitignore

@@ -0,0 +1,10 @@
+depthcharge/depthcharge/
+FILO/filo/
+GRUB2/grub2/
+LinuxBoot/linuxboot/
+SeaBIOS/seabios/
+tianocore/tianocore/
+tint/tint/
+U-Boot/u-boot/
+Memtest86Plus/memtest86plus/
+iPXE/ipxe/

payloads/external/FILO/Kconfig

@@ -5,9 +5,9 @@ choice
 	default FILO_STABLE
 
 config FILO_STABLE
-	bool "0.6.0"
+	bool "tested"
 	help
-	  Stable FILO version
+	  Tested FILO version
 
 config FILO_MASTER
 	bool "HEAD"

payloads/external/FILO/Makefile

@@ -1,6 +1,6 @@
 TAG-$(CONFIG_FILO_MASTER)=origin/master
 NAME-$(CONFIG_FILO_MASTER)=MASTER
-TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad
+TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412
 NAME-$(CONFIG_FILO_STABLE)=STABLE
 
 project_git_repo=https://review.coreboot.org/filo.git

payloads/libpayload/.gitignore

@@ -0,0 +1 @@
+install/

payloads/libpayload/Kconfig

@@ -79,6 +79,14 @@ config COMPILER_LLVM_CLANG
 
 endchoice
 
+config LTO
+	bool "Use link time optimization (LTO)"
+	default n
+	depends on COMPILER_GCC
+	help
+	  Compile with link time optimization. This can often decrease the
+	  final binary size, but may increase compilation time.
+
 config REMOTEGDB
 	bool "Remote GDB stub"
 	default n

payloads/libpayload/Makefile.inc

@@ -64,6 +64,10 @@ CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla
 CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
 CFLAGS += -Wstrict-aliasing -Wshadow -Werror
 
+ifeq ($(CONFIG_LP_LTO),y)
+CFLAGS += -flto
+endif
+
 $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER)
 	cmp $@ $< 2>/dev/null || cp $< $@
 

payloads/libpayload/arch/x86/timer.c

@@ -33,6 +33,10 @@
 
 #include <libpayload.h>
 #include <arch/rdtsc.h>
+#include <arch/cpuid.h>
+#include <arch/msr.h>
+
+#define MSR_PLATFORM_INFO		0xce
 
 /**
  * @ingroup arch
@@ -41,11 +45,11 @@
 uint32_t cpu_khz;
 
 /**
- * Calculate the speed of the processor for use in delays.
+ * @brief Measure the speed of the processor for use in delays
  *
  * @return The CPU speed in kHz.
  */
-unsigned int get_cpu_speed(void)
+static unsigned int calibrate_pit(void)
 {
 	unsigned long long start, end;
 	const uint32_t clock_rate = 1193182; // 1.193182 MHz
@@ -71,7 +75,116 @@ unsigned int get_cpu_speed(void)
 	 * clock_rate / (interval * 1000). Multiply that by the number of
 	 * measured clocks to get the kHz value.
 	 */
-	cpu_khz = (end - start) * clock_rate / (1000 * interval);
+	return (end - start) * clock_rate / (1000 * interval);
+}
+
+/**
+ * @brief Calculates the core clock frequency via CPUID 0x15
+ *
+ * Newer Intel CPUs report their core clock in CPUID leaf 0x15. Early models
+ * supporting this leaf didn't provide the nominal crystal frequency in ecx,
+ * hence we use hard coded values for them.
+ */
+static int get_cpu_khz_xtal(void)
+{
+	uint32_t ecx, edx, num, denom;
+	uint64_t nominal;
+
+	if (cpuid_max() < 0x15)
+		return -1;
+	cpuid(0x15, denom, num, ecx, edx);
+
+	if (denom == 0 || num == 0)
+		return -1;
+
+	if (ecx != 0) {
+		nominal = ecx;
+	} else {
+		if (cpuid_family() != 6)
+			return -1;
+
+		switch (cpuid_model()) {
+		case SKYLAKE_U_Y:
+		case SKYLAKE_S_H:
+		case KABYLAKE_U_Y:
+		case KABYLAKE_S_H:
+			nominal = 24000000;
+			break;
+		case APOLLOLAKE:
+			nominal = 19200000;
+			break;
+		default:
+			return -1;
+		}
+	}
+
+	return nominal * num / denom / 1000;
+}
+
+/**
+ * @brief Returns three times the bus clock in kHz
+ *
+ * The result of calculations with the returned value shall be divided by 3.
+ * This helps to avoid rounding errors.
+ */
+static int get_bus_khz_x3(void)
+{
+	if (cpuid_family() != 6)
+		return -1;
+
+	switch (cpuid_model()) {
+	case NEHALEM:
+		return 400 * 1000; /* 133 MHz */
+	case SANDYBRIDGE:
+	case IVYBRIDGE:
+	case HASWELL:
+	case HASWELL_U:
+	case HASWELL_GT3E:
+	case BROADWELL:
+	case BROADWELL_U:
+		return 300 * 1000; /* 100 MHz */
+	default:
+		return -1;
+	}
+}
+
+/**
+ * @brief Returns the calculated CPU frequency
+ *
+ * Over the years, multiple ways to discover the CPU frequency have been
+ * exposed through CPUID and MSRs. Try the most recent and accurate first
+ * (crystal information in CPUID leaf 0x15) and then fall back to older
+ * methods.
+ *
+ * This should cover all Intel Core i processors at least. For older
+ * processors we fall back to the PIT calibration.
+ */
+static int get_cpu_khz_fast(void)
+{
+	/* Try core crystal clock frequency first (supposed to be more accurate). */
+	const int cpu_khz_xtal = get_cpu_khz_xtal();
+	if (cpu_khz_xtal > 0)
+		return cpu_khz_xtal;
+
+	/* Try `bus clock * speedstep multiplier`. */
+	const int bus_x3 = get_bus_khz_x3();
+	if (bus_x3 <= 0)
+		return -1;
+	/*
+	 * Systems with an invariant TSC report the multiplier (maximum
+	 * non-turbo ratio) in MSR_PLATFORM_INFO[15:8].
+	 */
+	const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff;
+	return bus_x3 * mult / 3;
+}
+
+unsigned int get_cpu_speed(void)
+{
+	const int cpu_khz_fast = get_cpu_khz_fast();
+	if (cpu_khz_fast > 0)
+		cpu_khz = (unsigned int)cpu_khz_fast;
+	else
+		cpu_khz = calibrate_pit();
 
 	return cpu_khz;
 }

payloads/libpayload/include/coreboot_tables.h

@@ -80,6 +80,7 @@ enum {
 	CB_TAG_TCPA_LOG			= 0x0036,
 	CB_TAG_FMAP			= 0x0037,
 	CB_TAG_SMMSTOREV2		= 0x0039,
+	CB_TAG_BOARD_CONFIG		= 0x0040,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
@@ -260,12 +261,6 @@ struct cb_x86_rom_mtrr {
 	uint32_t index;
 };
 
-struct cb_strapping_id {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t id_code;
-};
-
 struct cb_spi_flash {
 	uint32_t tag;
 	uint32_t size;
@@ -317,6 +312,16 @@ struct cb_mmc_info {
 	int32_t early_cmd1_status;
 };
 
+struct cb_board_config {
+	uint32_t tag;
+	uint32_t size;
+
+	struct cbuint64 fw_config;
+	uint32_t board_id;
+	uint32_t ram_code;
+	uint32_t sku_id;
+};
+
 #define CB_MAX_SERIALNO_LENGTH	32
 
 struct cb_cmos_option_table {

payloads/libpayload/include/sysinfo.h

@@ -108,10 +108,17 @@ struct sysinfo_t {
 	uintptr_t acpi_gnvs;
 
 #define UNDEFINED_STRAPPING_ID	(~0)
+#define UNDEFINED_FW_CONFIG	~((uint64_t)0)
 	u32		board_id;
 	u32		ram_code;
 	u32		sku_id;
 
+	/*
+	 * A payload using this field is responsible for ensuring it checks its
+	 * value against UNDEFINED_FW_CONFIG before using it.
+	 */
+	u64		fw_config;
+
 	uintptr_t	wifi_calibration;
 	uint64_t	ramoops_buffer;
 	uint32_t	ramoops_buffer_size;

payloads/libpayload/include/x86/arch/cpuid.h

@@ -64,4 +64,20 @@ static inline unsigned int cpuid_model(void)
 	return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4;
 }
 
+enum intel_fam6_model {
+	NEHALEM		= 0x25,
+	SANDYBRIDGE	= 0x2a,
+	IVYBRIDGE	= 0x3a,
+	HASWELL		= 0x3c,
+	BROADWELL_U	= 0x3d,
+	HASWELL_U	= 0x45,
+	HASWELL_GT3E	= 0x46,
+	BROADWELL	= 0x47,
+	SKYLAKE_U_Y	= 0x4e,
+	APOLLOLAKE	= 0x5c,
+	SKYLAKE_S_H	= 0x5e,
+	KABYLAKE_U_Y	= 0x8e,
+	KABYLAKE_S_H	= 0x9e,
+};
+
 #endif

payloads/libpayload/libc/coreboot.c

@@ -143,22 +143,13 @@ static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info)
 	info->acpi_gnvs = get_cbmem_addr(ptr);
 }
 
-static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info)
 {
-	struct cb_strapping_id *const cbbid = (struct cb_strapping_id *)ptr;
+	struct cb_board_config *const config = (struct cb_board_config *)ptr;
-	info->board_id = cbbid->id_code;
+	info->fw_config = cb_unpack64(config->fw_config);
-}
+	info->board_id = config->board_id;
-
+	info->ram_code = config->ram_code;
-static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info)
+	info->sku_id = config->sku_id;
-{
-	struct cb_strapping_id *const ram_code = (struct cb_strapping_id *)ptr;
-	info->ram_code = ram_code->id_code;
-}
-
-static void cb_parse_sku_id(unsigned char *ptr, struct sysinfo_t *info)
-{
-	struct cb_strapping_id *const sku_id = (struct cb_strapping_id *)ptr;
-	info->sku_id = sku_id->id_code;
 }
 
 #if CONFIG(LP_NVRAM)
@@ -290,6 +281,7 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 	info->board_id = UNDEFINED_STRAPPING_ID;
 	info->ram_code = UNDEFINED_STRAPPING_ID;
 	info->sku_id = UNDEFINED_STRAPPING_ID;
+	info->fw_config = UNDEFINED_FW_CONFIG;
 
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
@@ -381,14 +373,8 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_ACPI_GNVS:
 			cb_parse_acpi_gnvs(ptr, info);
 			break;
-		case CB_TAG_BOARD_ID:
+		case CB_TAG_BOARD_CONFIG:
-			cb_parse_board_id(ptr, info);
+			cb_parse_board_config(ptr, info);
-			break;
-		case CB_TAG_RAM_CODE:
-			cb_parse_ram_code(ptr, info);
-			break;
-		case CB_TAG_SKU_ID:
-			cb_parse_sku_id(ptr, info);
 			break;
 		case CB_TAG_WIFI_CALIBRATION:
 			cb_parse_wifi_calibration(ptr, info);

payloads/nvramcui/.gitignore

@@ -0,0 +1,2 @@
+build
+libpayload

src/Kconfig

@@ -915,6 +915,15 @@ config DEBUG_MALLOC
 
 	  If unsure, say N.
 
+# Only visible if DEBUG_SPEW (8) is set.
+config DEBUG_RESOURCES
+	bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8
+	default n
+	help
+	  This option enables additional PCI memory and IO debug messages.
+	  Note: This option will increase the size of the coreboot image.
+	  If unsure, say N.
+
 config DEBUG_CONSOLE_INIT
 	bool "Debug console initialisation code"
 	default n
@@ -1114,6 +1123,16 @@ config TRACE
 	  of calling function. Please note some printk related functions
 	  are omitted from trace to have good looking console dumps.
 
+config DEBUG_FUNC
+	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
+	default n
+	help
+	  This option enables additional function entry and exit debug messages
+	  for select functions. If supported, this is less output than
+	  the TRACE option.
+	  Note: This option will increase the size of the coreboot image.
+	  If unsure, say N.
+
 config DEBUG_COVERAGE
 	bool "Debug code coverage"
 	default n

src/commonlib/Makefile.inc

@@ -30,6 +30,13 @@ ramstage-y += cbfs.c
 smm-y += cbfs.c
 postcar-y += cbfs.c
 
+bootblock-y += bsd/cbfs_private.c
+verstage-y += bsd/cbfs_private.c
+romstage-y += bsd/cbfs_private.c
+postcar-y += bsd/cbfs_private.c
+ramstage-y += bsd/cbfs_private.c
+smm-y += bsd/cbfs_private.c
+
 decompressor-y += bsd/lz4_wrapper.c
 bootblock-y += bsd/lz4_wrapper.c
 verstage-y += bsd/lz4_wrapper.c

src/commonlib/bsd/cbfs_private.c

@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
+
+#include <commonlib/bsd/cbfs_private.h>
+#include <assert.h>
+
+static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer)
+{
+	const size_t devsize = cbfs_dev_size(dev);
+	DEBUG("Looking for next file @%#zx...\n", *offset);
+	*offset = ALIGN_UP(*offset, CBFS_ALIGNMENT);
+	while (*offset + sizeof(*buffer) < devsize) {
+		if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer))
+			return CB_CBFS_IO;
+
+		if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0)
+			return CB_SUCCESS;
+
+		*offset += CBFS_ALIGNMENT;
+	}
+
+	DEBUG("End of CBFS reached\n");
+	return CB_CBFS_NOT_FOUND;
+}
+
+cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset,
+						      const union cbfs_mdata *mdata,
+						      size_t already_read, void *arg),
+		   void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags flags)
+{
+	const bool do_hash = CBFS_ENABLE_HASHING && metadata_hash;
+	struct vb2_digest_context dc;
+	vb2_error_t vbrv;
+
+	assert(CBFS_ENABLE_HASHING || (!metadata_hash && !(flags & CBFS_WALK_WRITEBACK_HASH)));
+	if (do_hash && (vbrv = vb2_digest_init(&dc, metadata_hash->algo))) {
+		ERROR("Metadata hash digest (%d) init error: %#x\n", metadata_hash->algo, vbrv);
+		return CB_ERR_ARG;
+	}
+
+	size_t offset = 0;
+	cb_err_t ret_header;
+	cb_err_t ret_walker = CB_CBFS_NOT_FOUND;
+	union cbfs_mdata mdata;
+	while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) {
+		const uint32_t attr_offset = be32toh(mdata.h.attributes_offset);
+		const uint32_t data_offset = be32toh(mdata.h.offset);
+		const uint32_t data_length = be32toh(mdata.h.len);
+		const uint32_t type = be32toh(mdata.h.type);
+		const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2);
+
+		DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n",
+		      offset, type, attr_offset, data_offset, data_length);
+		if (data_offset > sizeof(mdata)) {
+			ERROR("File metadata @%#zx too large\n", offset);
+			goto next_file;
+		}
+
+		if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY))
+			goto next_file;
+
+		/* When hashing we need to read everything. Otherwise skip the attributes.
+		   attr_offset may be 0, which means there are no attributes. */
+		ssize_t todo;
+		if (do_hash || attr_offset == 0)
+			todo = data_offset - sizeof(mdata.h);
+		else
+			todo = attr_offset - sizeof(mdata.h);
+		if (todo <= 0 || data_offset < attr_offset) {
+			ERROR("Corrupt file header @%#zx\n", offset);
+			goto next_file;
+		}
+
+		/* Read the rest of the metadata (filename, and possibly attributes). */
+		assert(todo > 0 && todo <= sizeof(mdata) - sizeof(mdata.h));
+		if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h),
+				  offset + sizeof(mdata.h), todo) != todo)
+			return CB_CBFS_IO;
+		DEBUG("File name: '%s'\n", mdata.filename);
+
+		if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset))
+			return CB_ERR;
+
+		if (walker && ret_walker == CB_CBFS_NOT_FOUND)
+			ret_walker = walker(dev, offset, &mdata, sizeof(mdata.h) + todo, arg);
+
+		/* Return IO errors immediately. For others, finish the hash first if needed. */
+		if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash))
+			return ret_walker;
+
+next_file:
+		offset += data_offset + data_length;
+	}
+
+	if (ret_header != CB_CBFS_NOT_FOUND)
+		return ret_header;
+
+	if (do_hash) {
+		uint8_t real_hash[VB2_MAX_DIGEST_SIZE];
+		size_t hash_size = vb2_digest_size(metadata_hash->algo);
+		if (vb2_digest_finalize(&dc, real_hash, hash_size))
+			return CB_ERR;
+		if (flags & CBFS_WALK_WRITEBACK_HASH)
+			memcpy(metadata_hash->raw, real_hash, hash_size);
+		else if (memcmp(metadata_hash->raw, real_hash, hash_size) != 0)
+			return CB_CBFS_HASH_MISMATCH;
+	}
+
+	return ret_walker;
+}
+
+cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src,
+				 size_t already_read, cbfs_dev_t dev, size_t offset)
+{
+	/* First, copy the stuff that cbfs_walk() already read for us. */
+	memcpy(dst, src, already_read);
+
+	/* Then read in whatever metadata may be left (will only happen in non-hashing case). */
+	const size_t todo = be32toh(src->h.offset) - already_read;
+	assert(todo <= sizeof(*dst) - already_read);
+	if (todo && cbfs_dev_read(dev, dst->raw + already_read, offset + already_read,
+				  todo) != todo)
+		return CB_CBFS_IO;
+	return CB_SUCCESS;
+}
+
+struct cbfs_lookup_args {
+	union cbfs_mdata *mdata_out;
+	const char *name;
+	size_t namesize;
+	size_t *data_offset_out;
+};
+
+static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata,
+			      size_t already_read, void *arg)
+{
+	struct cbfs_lookup_args *args = arg;
+
+	/* Check if the name we're looking for could fit, then we can safely memcmp() it. */
+	if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) ||
+	    memcmp(args->name, mdata->filename, args->namesize) != 0)
+		return CB_CBFS_NOT_FOUND;
+
+	LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len));
+	if (cbfs_copy_fill_metadata(args->mdata_out, mdata, already_read, dev, offset))
+		return CB_CBFS_IO;
+
+	*args->data_offset_out = offset + be32toh(mdata->h.offset);
+	return CB_SUCCESS;
+}
+
+cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
+		     size_t *data_offset_out, struct vb2_hash *metadata_hash)
+{
+	struct cbfs_lookup_args args = {
+		.mdata_out = mdata_out,
+		.name = name,
+		.namesize = strlen(name) + 1,	/* Count trailing \0 so we can memcmp() it. */
+		.data_offset_out = data_offset_out,
+	};
+	return cbfs_walk(dev, lookup_walker, &args, metadata_hash, 0);
+}

src/commonlib/bsd/include/commonlib/bsd/cb_err.h

@@ -34,6 +34,11 @@ enum cb_err {
 	CB_I2C_PROTOCOL_ERROR	= -302,	/**< Data lost or spurious slave
 					     device response, try again? */
 	CB_I2C_TIMEOUT		= -303, /**< Transmission timed out */
+
+	/* CBFS errors */
+	CB_CBFS_IO		= -400, /**< Underlying I/O error */
+	CB_CBFS_NOT_FOUND	= -401, /**< File not found in directory */
+	CB_CBFS_HASH_MISMATCH	= -402, /**< Master hash validation failed */
 };
 
 /* Don't typedef the enum directly, so the size is unambiguous for serialization. */

src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h

@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
+
+#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_
+#define _COMMONLIB_BSD_CBFS_PRIVATE_H_
+
+
+#include <commonlib/bsd/cb_err.h>
+#include <commonlib/bsd/cbfs_serialized.h>
+#include <endian.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <vb2_sha.h>
+
+/*
+ * This header implements low-level CBFS access APIs that can be shared across different
+ * host applications (e.g. coreboot, libpayload, cbfstool). For verification purposes it
+ * implements the metadata hashing part but not the file hashing part, so the host application
+ * will need to verify file hashes itself after loading each file. Host applications that use
+ * verification should implement wrapper APIs that combine the lookup, loading and hashing steps
+ * into a single, safe function call and outside of the code implementing those APIs should not
+ * be accessing the low-level APIs in this file directly (e.g. coreboot SoC/driver code should
+ * never directly #include this file, and always use the higher level APIs in src/lib/cbfs.c).
+ *
+ * <cbfs_glue.h> needs to be provided by the host application using this CBFS library. It must
+ * define the following type, macros and functions:
+ *
+ * cbfs_dev_t		An opaque type representing a CBFS storage backend.
+ * CBFS_ENABLE_HASHING	Should be 0 to avoid linking hashing features, 1 otherwise. (Only for
+ *			metadata hashing. Host application needs to check file hashes itself.)
+ * ERROR(...)		printf-style macro to print errors.
+ * LOG(...)		printf-style macro to print normal-operation log messages.
+ * DEBUG(...)		printf-style macro to print detailed debug output.
+ *
+ * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size);
+ *			Read |size| bytes starting at |offset| from |dev| into |buffer|.
+ *			Returns amount of bytes read on success and < 0 on error.
+ *			This function *MUST* sanity-check offset/size on its own.
+ *
+ * size_t cbfs_dev_size(cbfs_dev_t dev);
+ *			Return the total size in bytes of the CBFS storage (actual CBFS area).
+ */
+#include <cbfs_glue.h>
+
+/*
+ * Helper structure to allocate space for a blob of metadata on the stack.
+ * NOTE: The fields in any union cbfs_mdata or any of its substructures from cbfs_serialized.h
+ * should always remain in the same byte order as they are stored on flash (= big endian). To
+ * avoid byte-order confusion, fields should always and only be converted to host byte order at
+ * exactly the time they are read from one of these structures into their own separate variable.
+ */
+#define CBFS_METADATA_MAX_SIZE 256
+union cbfs_mdata {
+	struct {
+		struct cbfs_file h;
+		char filename[];
+	};
+	uint8_t raw[CBFS_METADATA_MAX_SIZE];
+};
+
+/* Flags that modify behavior of cbfs_walk(). */
+enum cbfs_walk_flags {
+	/* Write the calculated hash back out to |metadata_hash->hash| rather than comparing it.
+	   |metadata_hash->algo| must still have been initialized by the caller. */
+	CBFS_WALK_WRITEBACK_HASH	= (1 << 0),
+	/* Call |walker| for empty file entries (i.e. entries with one of the CBFS_TYPE_DELETED
+	   types that mark free space in the CBFS). Otherwise, those entries will be skipped.
+	   Either way, these entries are never included in the metadata_hash calculation. */
+	CBFS_WALK_INCLUDE_EMPTY		= (1 << 1),
+};
+
+/*
+ * Traverse a CBFS and call a |walker| callback function for every file. Can additionally
+ * calculate a hash over the metadata of all files in the CBFS. If |metadata_hash| is NULL,
+ * hashing is disabled. If |walker| is NULL, will just traverse and hash the CBFS without
+ * invoking any callbacks (and always return CB_CBFS_NOT_FOUND unless there was another error).
+ *
+ * |arg| and |dev| will be passed through to |walker| unmodified. |offset| is the absolute
+ * offset in |dev| at which the current file metadata starts. |mdata| is a temporary buffer
+ * (only valid for the duration of this call to |walker|) containing already read metadata from
+ * the current file, up to |already_read| bytes. This will always at least contain the header
+ * fields and filename, but may contain more (i.e. attributes), depending on whether hashing is
+ * enabled. |walker| should call into cbfs_copy_fill_medadata() to copy the metadata of a file
+ * to a persistent buffer and automatically load remaining metadata from |dev| as needed based
+ * on the value of |already_read|.
+ *
+ * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further
+ * files. Any other return code will be used as the final return code for cbfs_walk(). It will
+ * return immediately unless it needs to calculate a hash in which case it will still traverse
+ * the remaining CBFS (but not call |walker| anymore).
+ *
+ * Returns, from highest to lowest priority:
+ * CB_CBFS_IO		- There was an IO error with the CBFS device (always considered fatal)
+ * CB_CBFS_HASH_MISMATCH - |metadata_hash| was provided and did not match the CBFS
+ * CB_SUCCESS/<other>	- First non-CB_CBFS_NOT_FOUND code returned by walker()
+ * CB_CBFS_NOT_FOUND	- walker() returned CB_CBFS_NOT_FOUND for every file in the CBFS
+ */
+cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset,
+						      const union cbfs_mdata *mdata,
+						      size_t already_read, void *arg),
+		   void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags);
+
+/*
+ * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata
+ * of a file into a permanent buffer. Will copy the |already_read| metadata from |src| into
+ * |dst| and load remaining metadata from |dev| as required.
+ */
+cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src,
+				 size_t already_read, cbfs_dev_t dev, size_t offset);
+
+/* Find a file named |name| in the CBFS on |dev|. Copy its metadata (including attributes)
+ * into |mdata_out| and pass out the offset to the file data on the CBFS device.
+ * Verify the metadata with |metadata_hash| if provided. */
+cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
+		     size_t *data_offset_out, struct vb2_hash *metadata_hash);
+
+#endif	/* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */

src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h

@@ -4,6 +4,7 @@
 #define _CBFS_SERIALIZED_H_
 
 #include <stdint.h>
+#include <vb2_sha.h>
 
 /** These are standard values for the known compression
     algorithms that coreboot knows about for stages and
@@ -124,12 +125,11 @@ struct cbfs_file_attr_compression {
 	uint32_t decompressed_size;
 } __packed;
 
+/* Actual size in CBFS may be larger/smaller than struct size! */
 struct cbfs_file_attr_hash {
 	uint32_t tag;
 	uint32_t len;
-	uint32_t hash_type;
+	struct vb2_hash hash;
-	/* hash_data is len - sizeof(struct) bytes */
-	uint8_t  hash_data[];
 } __packed;
 
 struct cbfs_file_attr_position {

src/commonlib/cbfs.c

@@ -7,21 +7,6 @@
 #include <string.h>
 #include <vb2_sha.h>
 
-#if !defined(LOG)
-#define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
-#endif
-#if defined(CONFIG)
-
-#if CONFIG(DEBUG_CBFS)
-#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
-#else
-#define DEBUG(x...)
-#endif
-
-#elif !defined(DEBUG)
-#define DEBUG(x...)
-#endif
-
 static size_t cbfs_next_offset(const struct region_device *cbfs,
 				const struct cbfsf *f)
 {

src/commonlib/include/commonlib/cbfs.h

@@ -3,7 +3,7 @@
 #ifndef _COMMONLIB_CBFS_H_
 #define _COMMONLIB_CBFS_H_
 
-#include <commonlib/bsd/cbfs_serialized.h>
+#include <commonlib/bsd/cbfs_private.h>
 #include <commonlib/region.h>
 #include <vb2_api.h>
 
@@ -11,6 +11,7 @@
 struct cbfsf {
 	struct region_device metadata;
 	struct region_device data;
+	union cbfs_mdata mdata;
 };
 
 /* Locate file by name and optional type. Returns 0 on success else < 0 on

src/commonlib/include/commonlib/coreboot_tables.h

@@ -62,15 +62,15 @@ enum {
 	LB_TAG_DMA			= 0x0022,
 	LB_TAG_RAM_OOPS			= 0x0023,
 	LB_TAG_ACPI_GNVS		= 0x0024,
-	LB_TAG_BOARD_ID			= 0x0025,
+	LB_TAG_BOARD_ID			= 0x0025,  /* deprecated */
 	LB_TAG_VERSION_TIMESTAMP	= 0x0026,
 	LB_TAG_WIFI_CALIBRATION		= 0x0027,
-	LB_TAG_RAM_CODE			= 0x0028,
+	LB_TAG_RAM_CODE			= 0x0028,  /* deprecated */
 	LB_TAG_SPI_FLASH		= 0x0029,
 	LB_TAG_SERIALNO			= 0x002a,
 	LB_TAG_MTC			= 0x002b,
 	LB_TAG_VPD			= 0x002c,
-	LB_TAG_SKU_ID			= 0x002d,
+	LB_TAG_SKU_ID			= 0x002d,  /* deprecated */
 	LB_TAG_BOOT_MEDIA_PARAMS	= 0x0030,
 	LB_TAG_CBMEM_ENTRY		= 0x0031,
 	LB_TAG_TSC_INFO			= 0x0032,
@@ -81,6 +81,8 @@ enum {
 	LB_TAG_FMAP			= 0x0037,
 	LB_TAG_PLATFORM_BLOB_VERSION	= 0x0038,
 	LB_TAG_SMMSTOREV2		= 0x0039,
+	LB_TAG_BOARD_CONFIG		= 0x0040,
+	/* The following options are CMOS-related */
 	LB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	LB_TAG_OPTION			= 0x00c9,
 	LB_TAG_OPTION_ENUM		= 0x00ca,
@@ -347,12 +349,6 @@ struct lb_x86_rom_mtrr {
 	uint32_t index;
 };
 
-struct lb_strapping_id {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t id_code;
-};
-
 struct lb_spi_flash {
 	uint32_t tag;
 	uint32_t size;
@@ -416,6 +412,16 @@ struct lb_macs {
 	struct mac_address mac_addrs[0];
 };
 
+struct lb_board_config {
+	uint32_t tag;
+	uint32_t size;
+
+	struct lb_uint64 fw_config;
+	uint32_t board_id;
+	uint32_t ram_code;
+	uint32_t sku_id;
+};
+
 #define MAX_SERIALNO_LENGTH	32
 
 /* The following structures are for the CMOS definitions table */

src/cpu/intel/Makefile.inc

@@ -10,9 +10,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x
+subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
+subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
+subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
 

src/cpu/intel/car/cache_as_ram_symbols.inc

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Trick the linker into supporting x86_64 relocations in 32bit code */
+#if ENV_X86_64
+#define uintptr_t quad
+#else
+#define uintptr_t long
+#endif
+
+rom_mtrr_mask:
+.uintptr_t _rom_mtrr_mask
+
+rom_mtrr_base:
+.uintptr_t _rom_mtrr_base
+
+car_mtrr_mask:
+.uintptr_t _car_mtrr_mask
+
+car_mtrr_start:
+.uintptr_t _car_mtrr_start

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -9,6 +9,8 @@
 
 .global bootblock_pre_c_entry
 
+#include <cpu/intel/car/cache_as_ram_symbols.inc>
+
 .code32
 _cache_as_ram_setup:
 
@@ -83,11 +85,10 @@ addrsize_set_high:
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	wrmsr
 
-
 	post_code(0x23)
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
-	movl	$_car_mtrr_start, %eax
+	movl	car_mtrr_start, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	xorl	%edx, %edx
 	wrmsr
@@ -96,20 +97,20 @@ addrsize_set_high:
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRR_PHYS_MASK(0)), %ecx
 	rdmsr
-	movl	$_car_mtrr_mask, %eax
+	mov	car_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
-	movl	$_rom_mtrr_base, %eax
+	mov	rom_mtrr_base, %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	rdmsr
-	movl	$_rom_mtrr_mask, %eax
+	mov	rom_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
@@ -207,8 +208,19 @@ end_microcode_update:
 	/* Need to align stack to 16 bytes at call instruction. Account for
 	the pushes below. */
 	andl	$0xfffffff0, %esp
-	subl	$4, %esp
 
+#if ENV_X86_64
+
+	#include <cpu/x86/64bit/entry64.inc>
+
+	movd	%mm2, %rdi
+	shlq	$32, %rdi
+	movd	%mm1, %rsi
+	or	%rsi, %rdi
+	movd	%mm0, %rsi
+
+#else
+	subl	$4, %esp
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
 	pushl	%eax	/* BIST */
@@ -216,6 +228,7 @@ end_microcode_update:
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
 	pushl	%eax	/* tsc[31:0] */
+#endif
 
 before_c_entry:
 	post_code(0x29)

src/cpu/intel/common/common_init.c

@@ -130,13 +130,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
 	 */
 	config->regs[CPPC_HIGHEST_PERF] = msr;
 
-	/*
-	 * Nominal Performance -> Guaranteed Performance:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},
-	 */
-	msr.bit_offset = 8;
-	config->regs[CPPC_NOMINAL_PERF] = msr;
-
 	/*
 	 * Lowest Nonlinear Performance -> Most Efficient Performance:
 	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},
@@ -158,6 +151,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
 	msr.bit_offset = 8;
 	config->regs[CPPC_GUARANTEED_PERF] = msr;
 
+	msr.addrl = MSR_PLATFORM_INFO;
+
+	/*
+	 * Nominal Performance -> Maximum Non-Turbo Ratio:
+	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)},
+	 */
+	msr.bit_offset = 8;
+	config->regs[CPPC_NOMINAL_PERF] = msr;
+
 	msr.addrl = IA32_HWP_REQUEST;
 
 	/*

src/cpu/intel/haswell/haswell.h

@@ -84,7 +84,7 @@
 
 /* PCODE MMIO communications live in the MCHBAR. */
 #define BIOS_MAILBOX_INTERFACE			0x5da4
-#define  MAILBOX_RUN_BUSY			(1UL << 31)
+#define  MAILBOX_RUN_BUSY			(1 << 31)
 #define  MAILBOX_BIOS_CMD_READ_PCS		1
 #define  MAILBOX_BIOS_CMD_WRITE_PCS		2
 #define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509

src/cpu/x86/lapic/lapic.c

@@ -3,7 +3,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 
-void do_lapic_init(void)
+void lapic_virtual_wire_mode_init(void)
 {
 	/* this is so interrupts work. This is very limited scope --
 	 * linux will do better later, we hope ...

src/cpu/x86/mp_init.c

@@ -112,7 +112,7 @@ extern char _binary_sipi_vector_start[];
 /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the
  * memory range is already reserved so the OS cannot use it. That region is
  * free to use for AP bringup before SMM is initialized. */
-static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE;
+static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE;
 static const int sipi_vector_location_size = SMM_DEFAULT_SIZE;
 
 struct mp_flight_plan {
@@ -338,16 +338,16 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params)
 
 	setup_default_sipi_vector_params(sp);
 	/* Setup MSR table. */
-	sp->msr_table_ptr = (uint32_t)&mod_loc[module_size];
+	sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size];
 	sp->msr_count = num_msrs;
 	/* Provide pointer to microcode patch. */
-	sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer;
+	sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer;
 	/* Pass on ability to load microcode in parallel. */
 	if (mp_params->parallel_microcode_load)
 		sp->microcode_lock = 0;
 	else
 		sp->microcode_lock = ~0;
-	sp->c_handler = (uint32_t)&ap_init;
+	sp->c_handler = (uintptr_t)&ap_init;
 	ap_count = &sp->ap_count;
 	atomic_set(ap_count, 0);
 
@@ -434,7 +434,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
 	if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
 		printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
 		if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
-			printk(BIOS_DEBUG, "timed out. Aborting.\n");
+			printk(BIOS_ERR, "timed out. Aborting.\n");
 			return -1;
 		}
 		printk(BIOS_DEBUG, "done.\n");
@@ -451,7 +451,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
 	if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
 		printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
 		if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
-			printk(BIOS_DEBUG, "timed out. Aborting.\n");
+			printk(BIOS_ERR, "timed out. Aborting.\n");
 			return -1;
 		}
 		printk(BIOS_DEBUG, "done.\n");
@@ -462,7 +462,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
 			   LAPIC_DM_STARTUP | sipi_vector);
 	printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete...");
 	if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
-		printk(BIOS_DEBUG, "timed out.\n");
+		printk(BIOS_ERR, "timed out.\n");
 		return -1;
 	}
 	printk(BIOS_DEBUG, "done.\n");
@@ -477,7 +477,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
 	if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
 		printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
 		if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
-			printk(BIOS_DEBUG, "timed out. Aborting.\n");
+			printk(BIOS_ERR, "timed out. Aborting.\n");
 			return -1;
 		}
 		printk(BIOS_DEBUG, "done.\n");
@@ -488,14 +488,14 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
 			   LAPIC_DM_STARTUP | sipi_vector);
 	printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete...");
 	if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
-		printk(BIOS_DEBUG, "timed out.\n");
+		printk(BIOS_ERR, "timed out.\n");
 		return -1;
 	}
 	printk(BIOS_DEBUG, "done.\n");
 
 	/* Wait for CPUs to check in. */
-	if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) {
+	if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) {
-		printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n",
+		printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n",
 		       atomic_read(num_aps), ap_count);
 		return -1;
 	}

src/cpu/x86/sipi_vector.S

@@ -121,7 +121,7 @@ _start:
 
 	/* Protect microcode loading. */
 lock_microcode:
-	lock bts $0, microcode_lock
+	lock btsl $0, microcode_lock
 	jc	lock_microcode
 
 load_microcode:

src/cpu/x86/smm/Makefile.inc

@@ -20,7 +20,7 @@ smm-generic-ccopts += -D__SMM__
 smm-c-deps:=$$(OPTION_TABLE_H)
 
 $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm)
-	$(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group
+	$(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group
 
 # change to the target path because objcopy will use the path name in its
 # ELF symbol names.
@@ -76,8 +76,10 @@ $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod
 
 else # CONFIG_SMM_TSEG
 
-$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld
+smm-y += smm.ld
-	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o
+
+$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld)
+	$(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o
 	$(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@
 

src/device/Kconfig

@@ -532,6 +532,17 @@ config PCI_ALLOW_BUS_MASTER
 	  instance, for libpayload based payloads as the drivers don't enable
 	  bus mastering for PCI bridges.
 
+if PCI_ALLOW_BUS_MASTER
+
+config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
+	bool "Any devices"
+	default y
+	help
+	  Allow coreboot to enable PCI bus mastering for any device. The actual
+	  selection of devices depends on the various PCI drivers in coreboot.
+
+endif # PCI_ALLOW_BUS_MASTER
+
 endif # PCI
 
 if PCIEXP_PLUGIN_SUPPORT

src/device/azalia_device.c

@@ -40,7 +40,7 @@ static int codec_detect(u8 *base)
 	int count;
 
 	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1)
+	if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
 		goto no_codec;
 
 	/* clear STATESTS bits (BAR + 0xe)[2:0] */
@@ -62,11 +62,11 @@ static int codec_detect(u8 *base)
 		goto no_codec;
 
 	/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
-	if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1)
+	if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
 		goto no_codec;
 
 	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1)
+	if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
 		goto no_codec;
 
 	/* Read in Codec location (BAR + 0xe)[2..0] */
@@ -166,7 +166,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr);
 
 	/* 1 */
-	if (wait_for_ready(base) == -1) {
+	if (wait_for_ready(base) < 0) {
 		printk(BIOS_DEBUG, "  codec not ready.\n");
 		return;
 	}
@@ -174,7 +174,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	reg32 = (addr << 28) | 0x000f0000;
 	write32(base + HDA_IC_REG, reg32);
 
-	if (wait_for_valid(base) == -1) {
+	if (wait_for_valid(base) < 0) {
 		printk(BIOS_DEBUG, "  codec not valid.\n");
 		return;
 	}
@@ -192,12 +192,12 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 
 	/* 3 */
 	for (i = 0; i < verb_size; i++) {
-		if (wait_for_ready(base) == -1)
+		if (wait_for_ready(base) < 0)
 			return;
 
 		write32(base + HDA_IC_REG, verb[i]);
 
-		if (wait_for_valid(base) == -1)
+		if (wait_for_valid(base) < 0)
 			return;
 	}
 	printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");

src/drivers/intel/fsp2_0/Kconfig

@@ -228,6 +228,7 @@ config FSP_STATUS_GLOBAL_RESET_REQUIRED_8
 
 config FSP_STATUS_GLOBAL_RESET
 	hex
+	depends on SOC_INTEL_COMMON_FSP_RESET
 	default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4
 	default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5
@@ -240,6 +241,13 @@ config FSP_STATUS_GLOBAL_RESET
 	  reset type from SoC Kconfig based on available Kconfig options
 	  FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported.
 
+config SOC_INTEL_COMMON_FSP_RESET
+	bool
+	help
+	  Common code block to handle platform reset request raised by FSP. The FSP
+	  will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that
+	  a reset is required.
+
 if FSP_PEIM_TO_PEIM_INTERFACE
 source "src/drivers/intel/fsp2_0/ppi/Kconfig"
 endif

src/drivers/intel/fsp2_0/Makefile.inc

@@ -2,6 +2,8 @@
 
 ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
 
+bootblock-$(CONFIG_FSP_CAR) += fspt_report.c
+
 romstage-y += debug.c
 romstage-y += hand_off_block.c
 romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c

src/drivers/intel/fsp2_0/fspt_report.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/symbols.h>
+#include <console/console.h>
+#include <fsp/util.h>
+
+/* filled in assembly after FSP-T ran */
+uintptr_t temp_memory_start;
+uintptr_t temp_memory_end;
+
+void report_fspt_output(void)
+{
+	const struct region fsp_car_region = {
+		.offset = temp_memory_start,
+		.size = temp_memory_end - temp_memory_start,
+	};
+	const struct region coreboot_car_region = {
+		.offset = (uintptr_t)_car_region_start,
+		.size = (uintptr_t)_car_region_size,
+	};
+	printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n",
+	       temp_memory_start, temp_memory_end);
+	if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) {
+		printk(BIOS_ERR, "Wrong CAR region used!\n");
+		printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n");
+	}
+}

src/drivers/intel/fsp2_0/include/fsp/util.h

@@ -89,6 +89,7 @@ bool fsp_guid_compare(const uint8_t guid1[16], const uint8_t guid2[16]);
 void fsp_find_bootloader_tolum(struct range_entry *re);
 void fsp_get_version(char *buf);
 void lb_string_platform_blob_version(struct lb_header *header);
+void report_fspt_output(void);
 
 /* Fill in header and validate sanity of component within region device. */
 enum cb_err fsp_validate_component(struct fsp_header *hdr,

src/drivers/ocp/dmi/smbios.c

@@ -9,7 +9,7 @@
 #include <stdio.h>
 #include <string.h>
 #include <soc/soc_util.h>
-#include <soc/cpu.h>
+#include <soc/util.h>
 #include <smbios.h>
 
 #include "ocp_dmi.h"

src/drivers/soundwire/alc711/Kconfig

@@ -0,0 +1,2 @@
+config DRIVERS_SOUNDWIRE_ALC711
+	bool

src/drivers/soundwire/alc711/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC711) += alc711.c

src/drivers/soundwire/alc711/alc711.c

@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_soundwire.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/mipi_ids.h>
+#include <device/soundwire.h>
+#include <stdio.h>
+
+#include "chip.h"
+
+static struct soundwire_address alc711_address = {
+	.version = SOUNDWIRE_VERSION_1_1,
+	.manufacturer_id = MIPI_MFG_ID_REALTEK,
+	.part_id = MIPI_DEV_ID_REALTEK_ALC711,
+	.class = MIPI_CLASS_NONE
+};
+
+static struct soundwire_slave alc711_slave = {
+	.wake_up_unavailable = false,
+	.test_mode_supported = false,
+	.clock_stop_mode1_supported = true,
+	.simplified_clockstopprepare_sm_supported = true,
+	.clockstopprepare_hard_reset_behavior = false,
+	.highPHY_capable = false,
+	.paging_supported = false,
+	.bank_delay_supported = false,
+	.port15_read_behavior = false,
+	.source_port_list = SOUNDWIRE_PORT(2),
+	.sink_port_list = SOUNDWIRE_PORT(1),
+};
+
+static struct soundwire_audio_mode alc711_audio_mode = {
+	/* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */
+	.bus_frequency_configs_count = 12,
+	.bus_frequency_configs = {
+		9600 * KHz,
+		4800 * KHz,
+		2400 * KHz,
+		1200 * KHz,
+		12000 * KHz,
+		6000 * KHz,
+		3000 * KHz,
+		1500 * KHz,
+		12288 * KHz,
+		6144 * KHz,
+		3072 * KHz,
+		1536 * KHz
+	},
+	/* Support 16 KHz to 192 KHz sampling frequency */
+	.sampling_frequency_configs_count = 9,
+	.sampling_frequency_configs = {
+		16 * KHz,
+		22.05 * KHz,
+		24 * KHz,
+		32 * KHz,
+		44.1 * KHz,
+		48 * KHz,
+		88.2 * KHz,
+		96 * KHz,
+		192 * KHz
+	},
+	.prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY
+};
+
+static struct soundwire_dpn alc711_dp = {
+	.port_wordlength_configs_count = 1,
+	.port_wordlength_configs = { 32 },
+	.data_port_type = FULL_DATA_PORT,
+	.max_grouping_supported = BLOCK_GROUP_COUNT_1,
+	.simplified_channelprepare_sm = false,
+	.imp_def_dpn_interrupts_supported = 0,
+	.min_channel_number = 1,
+	.max_channel_number = 2,
+	.modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED |
+			   MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS,
+	.block_packing_mode = true,
+	.port_audio_mode_count = 1,
+	.port_audio_mode_list = { 0 }
+};
+
+static const struct soundwire_codec alc711_codec = {
+	.slave = &alc711_slave,
+	.audio_mode = { &alc711_audio_mode },
+	.dpn = {
+		{
+			/* Data Input for Speaker Path */
+			.port = 1,
+			.sink = &alc711_dp
+		},
+		{
+			/* Data Output for DSP Path */
+			.port = 2,
+			.source = &alc711_dp
+		}
+	}
+
+};
+
+static void soundwire_alc711_fill_ssdt(const struct device *dev)
+{
+	struct drivers_soundwire_alc711_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	struct acpi_dp *dsd;
+
+	if (!dev->enabled || !scope)
+		return;
+
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+
+	/* Set codec address IDs. */
+	alc711_address.link_id = dev->path.generic.id;
+	alc711_address.unique_id = dev->path.generic.subid;
+
+	acpigen_write_ADR_soundwire_device(&alc711_address);
+	acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	dsd = acpi_dp_new_table("_DSD");
+	soundwire_gen_codec(dsd, &alc711_codec, NULL);
+	acpi_dp_write(dsd);
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *soundwire_alc711_acpi_name(const struct device *dev)
+{
+	struct drivers_soundwire_alc711_config *config = dev->chip_info;
+	static char name[5];
+
+	if (config->name)
+		return config->name;
+	snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid);
+	return name;
+}
+
+static struct device_operations soundwire_alc711_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.acpi_name		= soundwire_alc711_acpi_name,
+	.acpi_fill_ssdt		= soundwire_alc711_fill_ssdt,
+};
+
+static void soundwire_alc711_enable(struct device *dev)
+{
+	dev->ops = &soundwire_alc711_ops;
+}
+
+struct chip_operations drivers_soundwire_alc711_ops = {
+	CHIP_NAME("Realtek ALC711 SoundWire Codec")
+	.enable_dev = soundwire_alc711_enable
+};

src/drivers/soundwire/alc711/chip.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__
+#define __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__
+
+struct drivers_soundwire_alc711_config {
+	const char *name;
+	const char *desc;
+};
+
+#endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */

src/drivers/wifi/generic/Makefile.inc

@@ -1,5 +1,12 @@
-ramstage-$(CONFIG_DRIVERS_WIFI_GENERIC) += generic.c
+
+ifeq ($(CONFIG_DRIVERS_WIFI_GENERIC),y)
+
+ramstage-y += generic.c
+ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 
 cbfs-files-$(CONFIG_WIFI_SAR_CBFS)  += wifi_sar_defaults.hex
 wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH))
 wifi_sar_defaults.hex-type := raw
+
+endif

src/drivers/wifi/generic/acpi.c

@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <sar.h>
+#include <wrdd.h>
+
+#include "chip.h"
+#include "wifi_private.h"
+
+/* WRDS Spec Revision */
+#define WRDS_REVISION 0x0
+
+/* EWRD Spec Revision */
+#define EWRD_REVISION 0x0
+
+/* WRDS Domain type */
+#define WRDS_DOMAIN_TYPE_WIFI 0x7
+
+/* EWRD Domain type */
+#define EWRD_DOMAIN_TYPE_WIFI 0x7
+
+/* WGDS Domain type */
+#define WGDS_DOMAIN_TYPE_WIFI 0x7
+
+/*
+ * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0'
+ * The above representation returns unique and consistent name every time
+ * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is
+ * chosen since it contains the bus address of the device.
+ */
+#define WIFI_ACPI_NAME_MAX_LEN 5
+
+__weak int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits)
+{
+	return -1;
+}
+
+static void emit_sar_acpi_structures(const struct device *dev)
+{
+	int i, j, package_size;
+	struct wifi_sar_limits sar_limits;
+	struct wifi_sar_delta_table *wgds;
+
+	/* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */
+	if (dev->vendor != PCI_VENDOR_ID_INTEL)
+		return;
+
+	/* Retrieve the sar limits data */
+	if (get_wifi_sar_limits(&sar_limits) < 0) {
+		printk(BIOS_ERR, "Error: failed from getting SAR limits!\n");
+		return;
+	}
+
+	/*
+	 * Name ("WRDS", Package () {
+	 *   Revision,
+	 *   Package () {
+	 *     Domain Type,	// 0x7:WiFi
+	 *     WiFi SAR BIOS,	// BIOS SAR Enable/disable
+	 *     SAR Table Set	// Set#1 of SAR Table (10 bytes)
+	 *   }
+	 * })
+	 */
+	acpigen_write_name("WRDS");
+	acpigen_write_package(2);
+	acpigen_write_dword(WRDS_REVISION);
+	/* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */
+	package_size = 1 + 1 + BYTES_PER_SAR_LIMIT;
+	acpigen_write_package(package_size);
+	acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI);
+	acpigen_write_dword(CONFIG(SAR_ENABLE));
+	for (i = 0; i < BYTES_PER_SAR_LIMIT; i++)
+		acpigen_write_byte(sar_limits.sar_limit[0][i]);
+	acpigen_pop_len();
+	acpigen_pop_len();
+
+	/*
+	 * Name ("EWRD", Package () {
+	 *   Revision,
+	 *   Package () {
+	 *     Domain Type,		// 0x7:WiFi
+	 *     Dynamic SAR Enable,	// Dynamic SAR Enable/disable
+	 *     Extended SAR sets,	// Number of optional SAR table sets
+	 *     SAR Table Set,		// Set#2 of SAR Table (10 bytes)
+	 *     SAR Table Set,		// Set#3 of SAR Table (10 bytes)
+	 *     SAR Table Set		// Set#4 of SAR Table (10 bytes)
+	 *   }
+	 * })
+	 */
+	acpigen_write_name("EWRD");
+	acpigen_write_package(2);
+	acpigen_write_dword(EWRD_REVISION);
+	/*
+	 * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets'
+	 * + number of bytes for Set#2 & 3 & 4
+	 */
+	package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT;
+	acpigen_write_package(package_size);
+	acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI);
+	acpigen_write_dword(CONFIG(DSAR_ENABLE));
+	acpigen_write_dword(CONFIG_DSAR_SET_NUM);
+	for (i = 1; i < NUM_SAR_LIMITS; i++)
+		for (j = 0; j < BYTES_PER_SAR_LIMIT; j++)
+			acpigen_write_byte(sar_limits.sar_limit[i][j]);
+	acpigen_pop_len();
+	acpigen_pop_len();
+
+	if (!CONFIG(GEO_SAR_ENABLE))
+		return;
+
+	/*
+	 * Name ("WGDS", Package() {
+	 *  Revision,
+	 *  Package() {
+	 *   DomainType,                         // 0x7:WiFi
+	 *   WgdsWiFiSarDeltaGroup1PowerMax1,    // Group 1 FCC 2400 Max
+	 *   WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset
+	 *   WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset
+	 *   WgdsWiFiSarDeltaGroup1PowerMax2,    // Group 1 FCC 5200 Max
+	 *   WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset
+	 *   WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset
+	 *   WgdsWiFiSarDeltaGroup2PowerMax1,    // Group 2 EC Jap 2400 Max
+	 *   WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset
+	 *   WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset
+	 *   WgdsWiFiSarDeltaGroup2PowerMax2,    // Group 2 EC Jap 5200 Max
+	 *   WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset
+	 *   WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset
+	 *   WgdsWiFiSarDeltaGroup3PowerMax1,    // Group 3 ROW 2400 Max
+	 *   WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset
+	 *   WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset
+	 *   WgdsWiFiSarDeltaGroup3PowerMax2,    // Group 3 ROW 5200 Max
+	 *   WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset
+	 *   WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset
+	 *  }
+	 * })
+	 */
+
+	wgds = &sar_limits.wgds;
+	acpigen_write_name("WGDS");
+	acpigen_write_package(2);
+	acpigen_write_dword(wgds->version);
+	/* Emit 'Domain Type' +
+	 * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS)
+	 */
+	package_size = sizeof(sar_limits.wgds.group) + 1;
+	acpigen_write_package(package_size);
+	acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI);
+	for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) {
+		acpigen_write_byte(wgds->group[i].power_max_2400mhz);
+		acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz);
+		acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz);
+		acpigen_write_byte(wgds->group[i].power_max_5200mhz);
+		acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz);
+		acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz);
+	}
+
+	acpigen_pop_len();
+	acpigen_pop_len();
+}
+
+static void wifi_ssdt_write_device(const struct device *dev, const char *path)
+{
+	/* Device */
+	acpigen_write_device(path);
+	acpi_device_write_uid(dev);
+
+	if (dev->chip_ops)
+		acpigen_write_name_string("_DDN", dev->chip_ops->name);
+
+	/* Address */
+	acpigen_write_ADR_pci_device(dev);
+
+	acpigen_pop_len(); /* Device */
+}
+
+static void wifi_ssdt_write_properties(const struct device *dev, const char *scope)
+{
+	const struct drivers_wifi_generic_config *config = dev->chip_info;
+
+	/* Scope */
+	acpigen_write_scope(scope);
+
+	/* Wake capabilities */
+	if (config)
+		acpigen_write_PRW(config->wake, ACPI_S3);
+
+	/* Fill regulatory domain structure */
+	if (CONFIG(HAVE_REGULATORY_DOMAIN)) {
+		/*
+		 * Name ("WRDD", Package () {
+		 *   WRDD_REVISION, // Revision
+		 *   Package () {
+		 *     WRDD_DOMAIN_TYPE_WIFI,   // Domain Type, 7:WiFi
+		 *     wifi_regulatory_domain() // Country Identifier
+		 *   }
+		 * })
+		 */
+		acpigen_write_name("WRDD");
+		acpigen_write_package(2);
+		acpigen_write_integer(WRDD_REVISION);
+		acpigen_write_package(2);
+		acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI);
+		acpigen_write_dword(wifi_regulatory_domain());
+		acpigen_pop_len();
+		acpigen_pop_len();
+	}
+
+	/* Fill Wifi sar related ACPI structures */
+	if (CONFIG(USE_SAR))
+		emit_sar_acpi_structures(dev);
+
+	acpigen_pop_len(); /* Scope */
+
+	printk(BIOS_INFO, "%s: %s %s\n", scope, dev->chip_ops ? dev->chip_ops->name : "",
+	       dev_path(dev));
+}
+
+void wifi_pcie_fill_ssdt(const struct device *dev)
+{
+	const char *path;
+
+	if (!is_dev_enabled(dev))
+		return;
+
+	path = acpi_device_path(dev);
+	if (!path)
+		return;
+
+	wifi_ssdt_write_device(dev, path);
+	wifi_ssdt_write_properties(dev, path);
+}
+
+const char *wifi_pcie_acpi_name(const struct device *dev)
+{
+	static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN];
+
+	/* ACPI 6.3, ASL 20.2.2: (Name Objects Encoding). */
+	snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02X",
+		 (dev_path_encode(dev) & 0xff));
+	return wifi_acpi_name;
+}
+
+void wifi_cnvi_fill_ssdt(const struct device *dev)
+{
+	const char *path;
+
+	if (!is_dev_enabled(dev))
+		return;
+
+	path = acpi_device_path(dev->bus->dev);
+	if (!path)
+		return;
+
+	wifi_ssdt_write_properties(dev, path);
+}

src/drivers/wifi/generic/generic.c

@@ -1,245 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi_device.h>
-#include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <elog.h>
-#include <sar.h>
-#include <smbios.h>
-#include <string.h>
-#include <wrdd.h>
 #include "chip.h"
-
+#include "wifi_private.h"
-/* WRDS Spec Revision */
-#define WRDS_REVISION 0x0
-
-/* EWRD Spec Revision */
-#define EWRD_REVISION 0x0
-
-/* WRDS Domain type */
-#define WRDS_DOMAIN_TYPE_WIFI 0x7
-
-/* EWRD Domain type */
-#define EWRD_DOMAIN_TYPE_WIFI 0x7
-
-/* WGDS Domain type */
-#define WGDS_DOMAIN_TYPE_WIFI 0x7
-
-/*
- * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0'
- * The above representation returns unique and consistent name every time
- * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is
- * chosen since it contains the bus address of the device.
- */
-#define WIFI_ACPI_NAME_MAX_LEN 5
-
-#if CONFIG(HAVE_ACPI_TABLES)
-__weak
-int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits)
-{
-	return -1;
-}
-
-static void emit_sar_acpi_structures(const struct device *dev)
-{
-	int i, j, package_size;
-	struct wifi_sar_limits sar_limits;
-	struct wifi_sar_delta_table *wgds;
-
-	/* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */
-	if (dev->vendor != PCI_VENDOR_ID_INTEL)
-		return;
-
-	/* Retrieve the sar limits data */
-	if (get_wifi_sar_limits(&sar_limits) < 0) {
-		printk(BIOS_ERR, "Error: failed from getting SAR limits!\n");
-		return;
-	}
-
-	/*
-	 * Name ("WRDS", Package () {
-	 *   Revision,
-	 *   Package () {
-	 *     Domain Type,	// 0x7:WiFi
-	 *     WiFi SAR BIOS,	// BIOS SAR Enable/disable
-	 *     SAR Table Set	// Set#1 of SAR Table (10 bytes)
-	 *   }
-	 * })
-	 */
-	acpigen_write_name("WRDS");
-	acpigen_write_package(2);
-	acpigen_write_dword(WRDS_REVISION);
-	/* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */
-	package_size = 1 + 1 + BYTES_PER_SAR_LIMIT;
-	acpigen_write_package(package_size);
-	acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI);
-	acpigen_write_dword(CONFIG(SAR_ENABLE));
-	for (i = 0; i < BYTES_PER_SAR_LIMIT; i++)
-		acpigen_write_byte(sar_limits.sar_limit[0][i]);
-	acpigen_pop_len();
-	acpigen_pop_len();
-
-	/*
-	 * Name ("EWRD", Package () {
-	 *   Revision,
-	 *   Package () {
-	 *     Domain Type,		// 0x7:WiFi
-	 *     Dynamic SAR Enable,	// Dynamic SAR Enable/disable
-	 *     Extended SAR sets,	// Number of optional SAR table sets
-	 *     SAR Table Set,		// Set#2 of SAR Table (10 bytes)
-	 *     SAR Table Set,		// Set#3 of SAR Table (10 bytes)
-	 *     SAR Table Set		// Set#4 of SAR Table (10 bytes)
-	 *   }
-	 * })
-	 */
-	acpigen_write_name("EWRD");
-	acpigen_write_package(2);
-	acpigen_write_dword(EWRD_REVISION);
-	/*
-	 * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets'
-	 * + number of bytes for Set#2 & 3 & 4
-	 */
-	package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT;
-	acpigen_write_package(package_size);
-	acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI);
-	acpigen_write_dword(CONFIG(DSAR_ENABLE));
-	acpigen_write_dword(CONFIG_DSAR_SET_NUM);
-	for (i = 1; i < NUM_SAR_LIMITS; i++)
-		for (j = 0; j < BYTES_PER_SAR_LIMIT; j++)
-			acpigen_write_byte(sar_limits.sar_limit[i][j]);
-	acpigen_pop_len();
-	acpigen_pop_len();
-
-	if (!CONFIG(GEO_SAR_ENABLE))
-		return;
-
-	/*
-	 * Name ("WGDS", Package() {
-	 *  Revision,
-	 *  Package() {
-	 *   DomainType,                         // 0x7:WiFi
-	 *   WgdsWiFiSarDeltaGroup1PowerMax1,    // Group 1 FCC 2400 Max
-	 *   WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset
-	 *   WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset
-	 *   WgdsWiFiSarDeltaGroup1PowerMax2,    // Group 1 FCC 5200 Max
-	 *   WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset
-	 *   WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset
-	 *   WgdsWiFiSarDeltaGroup2PowerMax1,    // Group 2 EC Jap 2400 Max
-	 *   WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset
-	 *   WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset
-	 *   WgdsWiFiSarDeltaGroup2PowerMax2,    // Group 2 EC Jap 5200 Max
-	 *   WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset
-	 *   WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset
-	 *   WgdsWiFiSarDeltaGroup3PowerMax1,    // Group 3 ROW 2400 Max
-	 *   WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset
-	 *   WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset
-	 *   WgdsWiFiSarDeltaGroup3PowerMax2,    // Group 3 ROW 5200 Max
-	 *   WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset
-	 *   WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset
-	 *  }
-	 * })
-	 */
-
-	wgds = &sar_limits.wgds;
-	acpigen_write_name("WGDS");
-	acpigen_write_package(2);
-	acpigen_write_dword(wgds->version);
-	/* Emit 'Domain Type' +
-	 * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS)
-	 */
-	package_size = sizeof(sar_limits.wgds.group) + 1;
-	acpigen_write_package(package_size);
-	acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI);
-	for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) {
-		acpigen_write_byte(wgds->group[i].power_max_2400mhz);
-		acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz);
-		acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz);
-		acpigen_write_byte(wgds->group[i].power_max_5200mhz);
-		acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz);
-		acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz);
-	}
-
-	acpigen_pop_len();
-	acpigen_pop_len();
-}
-
-static void wifi_generic_fill_ssdt(const struct device *dev)
-{
-	const char *path;
-	u32 address;
-	const struct drivers_wifi_generic_config *config = dev->chip_info;
-
-	if (!dev->enabled)
-		return;
-
-	path = acpi_device_path(dev->bus->dev);
-	if (!path)
-		return;
-
-	/* Device */
-	acpigen_write_scope(path);
-	acpigen_write_device(acpi_device_name(dev));
-	acpi_device_write_uid(dev);
-
-	if (dev->chip_ops)
-		acpigen_write_name_string("_DDN", dev->chip_ops->name);
-
-	/* Address */
-	address = PCI_SLOT(dev->path.pci.devfn) & 0xffff;
-	address <<= 16;
-	address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff;
-	acpigen_write_name_dword("_ADR", address);
-
-	/* Wake capabilities */
-	if (config)
-		acpigen_write_PRW(config->wake, ACPI_S3);
-
-	/* Fill regulatory domain structure */
-	if (CONFIG(HAVE_REGULATORY_DOMAIN)) {
-		/*
-		 * Name ("WRDD", Package () {
-		 *   WRDD_REVISION, // Revision
-		 *   Package () {
-		 *     WRDD_DOMAIN_TYPE_WIFI,   // Domain Type, 7:WiFi
-		 *     wifi_regulatory_domain() // Country Identifier
-		 *   }
-		 * })
-		 */
-		acpigen_write_name("WRDD");
-		acpigen_write_package(2);
-		acpigen_write_integer(WRDD_REVISION);
-		acpigen_write_package(2);
-		acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI);
-		acpigen_write_dword(wifi_regulatory_domain());
-		acpigen_pop_len();
-		acpigen_pop_len();
-	}
-
-	/* Fill Wifi sar related ACPI structures */
-	if (CONFIG(USE_SAR))
-		emit_sar_acpi_structures(dev);
-
-	acpigen_pop_len(); /* Device */
-	acpigen_pop_len(); /* Scope */
-
-	printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev),
-	       dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev));
-}
-
-static const char *wifi_generic_acpi_name(const struct device *dev)
-{
-	static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN];
-
-	/* ACPI 6.3, ASL 20.2.2: (Name Objects Encoding). */
-	snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02X",
-		 (dev_path_encode(dev) & 0xff));
-	return wifi_acpi_name;
-}
-#endif
 
 static void wifi_pci_dev_init(struct device *dev)
 {
@@ -247,54 +15,29 @@ static void wifi_pci_dev_init(struct device *dev)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0);
 }
 
-#if CONFIG(GENERATE_SMBIOS_TABLES)
+struct device_operations wifi_pcie_ops = {
-static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current)
-{
-	struct smbios_type_intel_wifi {
-		u8 type;
-		u8 length;
-		u16 handle;
-		u8 str;
-		u8 eos[2];
-	} __packed;
-
-	struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current;
-	int len = sizeof(struct smbios_type_intel_wifi);
-
-	memset(t, 0, sizeof(struct smbios_type_intel_wifi));
-	t->type = 0x85;
-	t->length = len - 2;
-	t->handle = *handle;
-	/* Intel wifi driver expects this string to be in the table 0x85. */
-	t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII");
-
-	len = t->length + smbios_string_table_len(t->eos);
-	*current += len;
-	*handle += 1;
-	return len;
-}
-
-static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current)
-{
-	if (dev->vendor == PCI_VENDOR_ID_INTEL)
-		return smbios_write_intel_wifi(dev, handle, current);
-
-	return 0;
-}
-#endif
-
-struct device_operations wifi_generic_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= wifi_pci_dev_init,
 	.ops_pci		= &pci_dev_ops_pci,
 #if CONFIG(HAVE_ACPI_TABLES)
-	.acpi_name		= wifi_generic_acpi_name,
+	.acpi_name		= wifi_pcie_acpi_name,
-	.acpi_fill_ssdt		= wifi_generic_fill_ssdt,
+	.acpi_fill_ssdt		= wifi_pcie_fill_ssdt,
 #endif
 #if CONFIG(GENERATE_SMBIOS_TABLES)
-	.get_smbios_data	= smbios_write_wifi,
+	.get_smbios_data	= smbios_write_wifi_pcie,
+#endif
+};
+
+struct device_operations wifi_cnvi_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_fill_ssdt		= wifi_cnvi_fill_ssdt,
+#endif
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+	.get_smbios_data	= smbios_write_wifi_cnvi,
 #endif
 };
 
@@ -305,7 +48,10 @@ static void wifi_generic_enable(struct device *dev)
 	if (!config)
 		return;
 
-	dev->ops = &wifi_generic_ops;
+	if (dev->path.type == DEVICE_PATH_PCI)
+		dev->ops = &wifi_pcie_ops;
+	else
+		dev->ops = &wifi_cnvi_ops;
 }
 
 struct chip_operations drivers_wifi_generic_ops = {
@@ -343,18 +89,8 @@ static const unsigned short intel_pci_device_ids[] = {
 	PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI,
 	/* Windstorm Peak */
 	PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI,
-	/* Jefferson Peak */
-	PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI,
-	PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI,
-	PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI,
 	/* Thunder Peak 2 */
 	PCI_DEVICE_ID_TP_9260_SERIES_WIFI,
-	/* Harrison Peak */
-	PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI,
-	PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI,
-	PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI,
-	PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI,
-	PCI_DEVICE_ID_HrP_6SERIES_WIFI,
 	/* Cyclone Peak */
 	PCI_DEVICE_ID_CyP_6SERIES_WIFI,
 	/* Typhoon Peak */
@@ -372,7 +108,7 @@ static const unsigned short intel_pci_device_ids[] = {
  * `wifi_generic_ops`.
  */
 static const struct pci_driver intel_wifi_pci_driver __pci_driver = {
-	.ops		= &wifi_generic_ops,
+	.ops		= &wifi_pcie_ops,
 	.vendor		= PCI_VENDOR_ID_INTEL,
 	.devices	= intel_pci_device_ids,
 };

src/drivers/wifi/generic/smbios.c

@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <smbios.h>
+#include <string.h>
+
+#include "wifi_private.h"
+
+static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current)
+{
+	struct smbios_type_intel_wifi {
+		u8 type;
+		u8 length;
+		u16 handle;
+		u8 str;
+		u8 eos[2];
+	} __packed;
+
+	struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current;
+	int len = sizeof(struct smbios_type_intel_wifi);
+
+	memset(t, 0, sizeof(struct smbios_type_intel_wifi));
+	t->type = 0x85;
+	t->length = len - 2;
+	t->handle = *handle;
+	/* Intel wifi driver expects this string to be in the table 0x85. */
+	t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII");
+
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	*handle += 1;
+	return len;
+}
+
+int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current)
+{
+	if (dev->vendor == PCI_VENDOR_ID_INTEL)
+		return smbios_write_intel_wifi(dev, handle, current);
+
+	return 0;
+}
+
+int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current)
+{
+	return smbios_write_wifi_pcie(dev->bus->dev, handle, current);
+}

src/drivers/wifi/generic/wifi_private.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _WIFI_GENERIC_PRIVATE_H_
+#define _WIFI_GENERIC_PRIVATE_H_
+
+int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current);
+int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current);
+
+const char *wifi_pcie_acpi_name(const struct device *dev);
+void wifi_pcie_fill_ssdt(const struct device *dev);
+
+void wifi_cnvi_fill_ssdt(const struct device *dev);
+
+#endif

src/ec/google/chromeec/chip.h

@@ -3,7 +3,14 @@
 #ifndef EC_GOOGLE_CHROMEEC_CHIP_H
 #define EC_GOOGLE_CHROMEEC_CHIP_H
 
+#include <device/device.h>
+#include <stddef.h>
+
+#define MAX_TYPEC_PORTS		4
+
 struct ec_google_chromeec_config {
+	/* Pointer to PMC Mux connector for each Type-C port */
+	DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS];
 };
 
 #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */

src/ec/google/chromeec/ec.c

@@ -841,9 +841,16 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id)
 	return cbi_get_uint32(id, CBI_TAG_SKU_ID);
 }
 
-int google_chromeec_cbi_get_fw_config(uint32_t *fw_config)
+int google_chromeec_cbi_get_fw_config(uint64_t *fw_config)
 {
-	return cbi_get_uint32(fw_config, CBI_TAG_FW_CONFIG);
+	uint32_t config;
+
+	if (cbi_get_uint32(&config, CBI_TAG_FW_CONFIG))
+		return -1;
+
+	/* FIXME: Yet to determine source of other 32 bits... */
+	*fw_config = (uint64_t)config;
+	return 0;
 }
 
 int google_chromeec_cbi_get_oem_id(uint32_t *id)

src/ec/google/chromeec/ec.h

@@ -83,7 +83,7 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags);
  */
 int google_chromeec_cbi_get_oem_id(uint32_t *id);
 int google_chromeec_cbi_get_sku_id(uint32_t *id);
-int google_chromeec_cbi_get_fw_config(uint32_t *fw_config);
+int google_chromeec_cbi_get_fw_config(uint64_t *fw_config);
 int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize);
 int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize);
 /* version may be stored in CBI as a smaller integer width, but the EC code

src/ec/google/chromeec/ec_acpi.c

@@ -16,14 +16,6 @@
 #define GOOGLE_CHROMEEC_USBC_DEVICE_HID		"GOOG0014"
 #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME	"USBC"
 
-/* Avoid adding a false dependency on an SoC or intel/common */
-extern const struct device *soc_get_pmc_mux_device(int port_number);
-
-__weak const struct device *soc_get_pmc_mux_device(int port_number)
-{
-	return NULL;
-}
-
 const char *google_chromeec_acpi_name(const struct device *dev)
 {
 	/*
@@ -121,36 +113,18 @@ static const char *port_location_to_str(enum ec_pd_port_location port_location)
 static struct usb_pd_port_caps port_caps;
 static void add_port_location(struct acpi_dp *dsd, int port_number)
 {
-	acpi_dp_add_string(dsd, "port-location",
+	acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location));
-			   port_location_to_str(port_caps.port_location));
-}
-
-static int conn_id_to_match;
-
-/* A callback to match a port's connector for dev_find_matching_device_on_bus */
-static bool match_connector(DEVTREE_CONST struct device *dev)
-{
-	if (CONFIG(DRIVERS_INTEL_PMC)) {
-		extern struct chip_operations drivers_intel_pmc_mux_conn_ops;
-
-		return (dev->chip_ops == &drivers_intel_pmc_mux_conn_ops &&
-			dev->path.type == DEVICE_PATH_GENERIC &&
-			dev->path.generic.id == conn_id_to_match);
-	}
-
-	return false;
 }
 
 static void fill_ssdt_typec_device(const struct device *dev)
 {
+	struct ec_google_chromeec_config *config = dev->chip_info;
 	int rv;
 	int i;
 	unsigned int num_ports;
 	struct device *usb2_port;
 	struct device *usb3_port;
 	struct device *usb4_port;
-	const struct device *mux;
-	const struct device *conn;
 
 	if (google_chromeec_get_num_pd_ports(&num_ports))
 		return;
@@ -166,32 +140,28 @@ static void fill_ssdt_typec_device(const struct device *dev)
 		if (rv)
 			continue;
 
-		/* Get the MUX device, and find the matching connector on its bus */
+		if (!config->mux_conn[i])
-		conn = NULL;
+			printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port "
-		mux = soc_get_pmc_mux_device(i);
+			       "#%d\n", i);
-		if (mux) {
-			conn_id_to_match = i;
-			conn = dev_find_matching_device_on_bus(mux->link_list, match_connector);
-		}
 
 		usb2_port = NULL;
 		usb3_port = NULL;
 		usb4_port = NULL;
 		get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port);
 
-		struct typec_connector_class_config config = {
+		struct typec_connector_class_config typec_config = {
 			.power_role = port_caps.power_role_cap,
 			.try_power_role = port_caps.try_power_role_cap,
 			.data_role = port_caps.data_role_cap,
 			.usb2_port = usb2_port,
 			.usb3_port = usb3_port,
 			.usb4_port = usb4_port,
-			.orientation_switch = conn,
+			.orientation_switch = config->mux_conn[i],
-			.usb_role_switch = conn,
+			.usb_role_switch = config->mux_conn[i],
-			.mode_switch = conn,
+			.mode_switch = config->mux_conn[i],
 		};
 
-		acpigen_write_typec_connector(&config, i, add_port_location);
+		acpigen_write_typec_connector(&typec_config, i, add_port_location);
 	}
 
 	acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */

src/ec/hp/kbc1126/Kconfig

@@ -5,6 +5,11 @@ config EC_HP_KBC1126
 	help
 	  Interface to SMSC KBC1126 embedded controller in HP laptops.
 
+config EC_HP_KBC1126_GPE
+	hex
+	depends on EC_HP_KBC1126
+	default 0x16
+
 config EC_HP_KBC1126_ECFW_IN_CBFS
 	bool
 	depends on EC_HP_KBC1126

src/ec/hp/kbc1126/acpi/ec.asl

@@ -4,7 +4,7 @@ Device (EC0)
 {
 	Name (_HID, EISAID("PNP0C09"))
 	Name (_UID, 0)
-	Name (_GPE, 0x16)
+	Name (_GPE, CONFIG_EC_HP_KBC1126_GPE)
 
 	Name (_CRS, ResourceTemplate ()
 	{

src/ec/system76/ec/acpi/ec.asl

@@ -35,7 +35,7 @@ Device (\_SB.PCI0.LPCB.EC0)
 	Method (_REG, 2, Serialized)  // _REG: Region Availability
 	{
 		Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1))))
-		If (((Arg0 == 0x03) && (Arg1 == One))) {
+		If ((Arg0 == 0x03) && (Arg1 == One)) {
 			// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
 			ECOS = 1
 

src/ec/system76/ec/acpi/hid.asl

@@ -30,13 +30,13 @@ Device (HIDD)
 
 		Notify (HIDD, 0xC0)
 		Local0 = Zero
-		While (((Local0 < 0xFA) && HBSY))
+		While ((Local0 < 0xFA) && HBSY)
 		{
 			Sleep (0x04)
 			Local0++
 		}
 
-		If ((HBSY == One))
+		If (HBSY == One)
 		{
 			HBSY = Zero
 			HIDX = Zero

src/include/acpi/acpigen.h

@@ -231,6 +231,10 @@ struct dsm_uuid {
 	void *arg;
 };
 
+#define CPPC_VERSION_1	1
+#define CPPC_VERSION_2	2
+#define CPPC_VERSION_3	3
+
 /*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */
 enum cppc_fields {
 	CPPC_HIGHEST_PERF, /* can be DWORD */

src/include/cbfs_glue.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _CBFS_GLUE_H_
+#define _CBFS_GLUE_H_
+
+#include <commonlib/region.h>
+#include <console/console.h>
+
+#define CBFS_ENABLE_HASHING 0
+
+#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__)
+#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__)
+#define DEBUG(...) do { \
+	if (CONFIG(DEBUG_CBFS)) \
+		printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__); \
+} while (0)
+
+typedef const struct region_device *cbfs_dev_t;
+
+static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size)
+{
+	return rdev_readat(dev, buffer, offset, size);
+}
+
+static inline size_t cbfs_dev_size(cbfs_dev_t dev)
+{
+	return region_device_sz(dev);
+}
+
+#endif	/* _CBFS_GLUE_H_ */

src/include/console/debug.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _CONSOLE_DEBUG_H_
+#define _CONSOLE_DEBUG_H_
+
+#if CONFIG(DEBUG_FUNC)
+#include <console/console.h>
+
+#define FUNC_ENTER() \
+	printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__)
+
+#define FUNC_EXIT() \
+	printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__)
+
+#else /* FUNC_DEBUG */
+
+#define FUNC_ENTER()
+#define FUNC_EXIT()
+
+#endif /* FUNC_DEBUG */
+
+#endif

src/include/cpu/intel/msr.h

@@ -12,4 +12,6 @@
 #define MSR_PIC_MSG_CONTROL	0x2e
 #define  TPR_UPDATES_DISABLE	(1 << 10)
 
+#define MSR_PLATFORM_INFO	0xce
+
 #endif /* CPU_INTEL_MSR_H */

src/include/cpu/x86/lapic.h

@@ -73,7 +73,7 @@ static inline void lapic_write_atomic(unsigned long reg, uint32_t v)
 # define lapic_read_around(x) lapic_read(x)
 # define lapic_write_around(x, y) lapic_write_atomic((x), (y))
 
-void do_lapic_init(void);
+void lapic_virtual_wire_mode_init(void);
 
 /* See if I need to initialize the local APIC */
 static inline int need_lapic_init(void)
@@ -84,7 +84,7 @@ static inline int need_lapic_init(void)
 static inline void setup_lapic(void)
 {
 	if (need_lapic_init())
-		do_lapic_init();
+		lapic_virtual_wire_mode_init();
 	else
 		disable_lapic();
 }

src/include/device/device.h

@@ -261,6 +261,38 @@ void show_one_resource(int debug_level, struct device *dev,
 		       struct resource *resource, const char *comment);
 void show_all_devs_resources(int debug_level, const char *msg);
 
+/* Debug macros */
+#if CONFIG(DEBUG_RESOURCES)
+#include <console/console.h>
+#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \
+	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \
+		"end: 0x%llx, size_kb: 0x%llx\n", \
+		__func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \
+		(base_kb << 10) + (size_kb << 10) - 1, size_kb)
+
+#define LOG_IO_RESOURCE(type, dev, index, base, size) \
+	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \
+		"end: 0x%llx, size: 0x%llx\n", \
+		__func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size)
+#else /* DEBUG_RESOURCES*/
+#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb)
+#define LOG_IO_RESOURCE(type, dev, index, base, size)
+#endif /* DEBUG_RESOURCES*/
+
+#if CONFIG(DEBUG_FUNC)
+#include <console/console.h>
+#define DEV_FUNC_ENTER(dev) \
+	printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \
+		__FILE__, __func__, __LINE__, dev_path(dev))
+
+#define DEV_FUNC_EXIT(dev) \
+	printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \
+		__func__, __LINE__, dev_path(dev))
+#else /* DEBUG_FUNC */
+#define DEV_FUNC_ENTER(dev)
+#define DEV_FUNC_EXIT(dev)
+#endif /* DEBUG_FUNC */
+
 /* Rounding for boundaries.
  * Due to some chip bugs, go ahead and round IO to 16
  */

src/include/device/mipi_ids.h

@@ -20,6 +20,7 @@
 /* Contributing Members */
 #define MIPI_MFG_ID_REALTEK			0x025d
 #define MIPI_DEV_ID_REALTEK_ALC5682		0x5682
+#define MIPI_DEV_ID_REALTEK_ALC711		0x0711
 
 #define MIPI_MFG_ID_MAXIM			0x019f
 #define MIPI_DEV_ID_MAXIM_MAX98373		0x8373

src/include/device/pci.h

@@ -144,7 +144,7 @@ void pci_dev_request_bus_master(pci_devfn_t dev)
 void pci_dev_request_bus_master(struct device *dev)
 #endif /* ENV_PCI_SIMPLE_DEVICE */
 {
-	if (CONFIG(PCI_ALLOW_BUS_MASTER))
+	if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
 		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 }
 

src/include/device/pci_ids.h

@@ -3950,19 +3950,11 @@
 #define PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI	0x08b2
 #define PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI	0x095a
 #define PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI	0x095b
-#define PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI	0x9df0
-#define PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI	0x31dc
-#define PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI	0xa370
 #define PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI	0x24f3
 #define PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI	0x24f4
 #define PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI	0x24fd
 #define PCI_DEVICE_ID_TP_9260_SERIES_WIFI	0x2526
-#define PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI	0x34f0
-#define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI	0xa0f0
-#define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI	0x02f0
-#define PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI	0x06f0
 #define PCI_DEVICE_ID_CyP_6SERIES_WIFI		0x2723
-#define PCI_DEVICE_ID_HrP_6SERIES_WIFI		0x2720
 #define PCI_DEVICE_ID_TyP_6SERIES_WIFI		0x2725
 #define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI	0x51f0
 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI	0x7af0
@@ -3977,6 +3969,26 @@
 #define PCI_DEVICE_ID_INTEL_JSL_DTT		0x4E03
 #define PCI_DEVICE_ID_INTEL_ADL_DTT		0x461d
 
+/* Intel CNVi WiFi/BT device IDs */
+#define PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI	0x02f0
+#define PCI_DEVICE_ID_INTEL_CML_H_CNVI_WIFI	0x06f0
+#define PCI_DEVICE_ID_INTEL_CNL_LP_CNVI_WIFI	0x9df0
+#define PCI_DEVICE_ID_INTEL_CNL_H_CNVI_WIFI	0xa370
+#define PCI_DEVICE_ID_INTEL_GLK_CNVI_WIFI	0x31dc
+#define PCI_DEVICE_ID_INTEL_ICL_CNVI_WIFI	0x34f0
+#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_0	0x4df0
+#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_1	0x4df1
+#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_2	0x4df2
+#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_3	0x4df3
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_0	0xa0f0
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_1	0xa0f1
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_2	0xa0f2
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_3	0xa0f3
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_0	0xa0f5
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1	0xa0f6
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2	0xa0f7
+#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3	0xa0f8
+
 #define PCI_VENDOR_ID_COMPUTONE		0x8e0e
 #define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
 #define PCI_DEVICE_ID_COMPUTONE_PG	0x0302

src/include/fw_config.h

@@ -8,6 +8,8 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#define UNDEFINED_FW_CONFIG	~((uint64_t)0)
+
 /**
  * struct fw_config - Firmware configuration field and option.
  * @field_name: Name of the field that this option belongs to.
@@ -18,8 +20,8 @@
 struct fw_config {
 	const char *field_name;
 	const char *option_name;
-	uint32_t mask;
+	uint64_t mask;
-	uint32_t value;
+	uint64_t value;
 };
 
 /* Generate a pointer to a compound literal of the fw_config structure. */
@@ -30,6 +32,13 @@ struct fw_config {
 	.value = FW_CONFIG_FIELD_##__field##_OPTION_##__option##_VALUE		\
 })
 
+/**
+ * fw_config_get() - Provide firmware configuration value.
+ *
+ * Return 64bit firmware configuration value determined for the system.
+ */
+uint64_t fw_config_get(void);
+
 #if CONFIG(FW_CONFIG)
 
 /**
@@ -53,7 +62,7 @@ void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *a
  *
  * Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL.
 */
-const struct fw_config *fw_config_get_found(uint32_t field_mask);
+const struct fw_config *fw_config_get_found(uint64_t field_mask);
 
 #else
 

src/include/list.h

@@ -18,7 +18,7 @@ void list_insert_before(struct list_node *node, struct list_node *before);
 
 #define list_for_each(ptr, head, member)                                      \
 	for ((ptr) = container_of((head).next, typeof(*(ptr)), member);       \
-		&((ptr)->member);                                       \
+		(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \
 		(ptr) = container_of((ptr)->member.next,                      \
 			typeof(*(ptr)), member))
 

src/lib/cbfs.c

@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <boot_device.h>
 #include <cbfs.h>
+#include <commonlib/bsd/cbfs_private.h>
 #include <commonlib/bsd/compression.h>
 #include <commonlib/endian.h>
 #include <console/console.h>
@@ -15,14 +16,6 @@
 #include <symbols.h>
 #include <timestamp.h>
 
-#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x)
-#define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
-#if CONFIG(DEBUG_CBFS)
-#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
-#else
-#define DEBUG(x...)
-#endif
-
 int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
 {
 	struct region_device rdev;
@@ -30,31 +23,35 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
 	if (cbfs_boot_region_device(&rdev))
 		return -1;
 
-	int ret = cbfs_locate(fh, &rdev, name, type);
+	size_t data_offset;
+	cb_err_t err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL);
 
-	if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) {
+	if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) {
-
+		printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n",
-		/*
+		       name);
-		 * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the
-		 * active RW region, the RO (COREBOOT) region will be used to locate the file.
-		 *
-		 * This functionality makes it possible to avoid duplicate files in the RO
-		 * and RW partitions while maintaining updateability.
-		 *
-		 * Files can be added to the RO_REGION_ONLY config option to use this feature.
-		 */
-		printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name);
 		if (fmap_locate_area_as_rdev("COREBOOT", &rdev))
-			ERROR("RO region not found\n");
+			return -1;
-		else
+		err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL);
-			ret = cbfs_locate(fh, &rdev, name, type);
+	}
+	if (err)
+		return -1;
+
+	size_t msize = be32toh(fh->mdata.h.offset);
+	if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev,
+		       (uintptr_t)&fh->mdata, msize) ||
+	    rdev_chain(&fh->data, &rdev, data_offset, be32toh(fh->mdata.h.len)))
+		return -1;
+	if (type) {
+		if (!*type)
+			*type = be32toh(fh->mdata.h.type);
+		else if (*type != be32toh(fh->mdata.h.type))
+			return -1;
 	}
 
-	if (!ret)
 	if (tspi_measure_cbfs_hook(fh, name))
 		return -1;
 
-	return ret;
+	return 0;
 }
 
 void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)

src/lib/coreboot_table.c

@@ -12,6 +12,7 @@
 #include <boardid.h>
 #include <device/device.h>
 #include <fmap.h>
+#include <fw_config.h>
 #include <stdlib.h>
 #include <cbfs.h>
 #include <cbmem.h>
@@ -213,23 +214,7 @@ static void lb_vbnv(struct lb_header *header)
 __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; }
 __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; }
 __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; }
-
+__weak uint64_t fw_config_get(void) { return UNDEFINED_FW_CONFIG; }
-static void lb_board_id(struct lb_header *header)
-{
-	struct lb_strapping_id  *rec;
-	uint32_t bid = board_id();
-
-	if (bid == UNDEFINED_STRAPPING_ID)
-		return;
-
-	rec = (struct lb_strapping_id *)lb_new_record(header);
-
-	rec->tag = LB_TAG_BOARD_ID;
-	rec->size = sizeof(*rec);
-	rec->id_code = bid;
-
-	printk(BIOS_INFO, "Board ID: %d\n", bid);
-}
 
 static void lb_boot_media_params(struct lb_header *header)
 {
@@ -257,40 +242,6 @@ static void lb_boot_media_params(struct lb_header *header)
 	bmp->fmap_offset = get_fmap_flash_offset();
 }
 
-static void lb_ram_code(struct lb_header *header)
-{
-	struct lb_strapping_id *rec;
-	uint32_t code = ram_code();
-
-	if (code == UNDEFINED_STRAPPING_ID)
-		return;
-
-	rec = (struct lb_strapping_id *)lb_new_record(header);
-
-	rec->tag = LB_TAG_RAM_CODE;
-	rec->size = sizeof(*rec);
-	rec->id_code = code;
-
-	printk(BIOS_INFO, "RAM code: %d\n", code);
-}
-
-static void lb_sku_id(struct lb_header *header)
-{
-	struct lb_strapping_id *rec;
-	uint32_t sid = sku_id();
-
-	if (sid == UNDEFINED_STRAPPING_ID)
-		return;
-
-	rec = (struct lb_strapping_id *)lb_new_record(header);
-
-	rec->tag = LB_TAG_SKU_ID;
-	rec->size = sizeof(*rec);
-	rec->id_code = sid;
-
-	printk(BIOS_INFO, "SKU ID: %d\n", sid);
-}
-
 static void lb_mmc_info(struct lb_header *header)
 {
 	struct lb_mmc_info *rec;
@@ -370,6 +321,24 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 	return mainboard;
 }
 
+static struct lb_board_config *lb_board_config(struct lb_header *header)
+{
+	struct lb_record *rec;
+	struct lb_board_config *config;
+	rec = lb_new_record(header);
+	config = (struct lb_board_config *)rec;
+
+	config->tag = LB_TAG_BOARD_CONFIG;
+	config->size = sizeof(*config);
+
+	config->board_id = board_id();
+	config->ram_code = ram_code();
+	config->sku_id = sku_id();
+	config->fw_config = pack_lb64(fw_config_get());
+
+	return config;
+}
+
 #if CONFIG(USE_OPTION_TABLE)
 static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 {
@@ -536,11 +505,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
 	lb_vbnv(head);
 #endif
 
-	/* Add strapping IDs if available */
-	lb_board_id(head);
-	lb_ram_code(head);
-	lb_sku_id(head);
-
 	/* Pass mmc early init status */
 	lb_mmc_info(head);
 
@@ -563,6 +527,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
 
 	lb_boot_media_params(head);
 
+	/* Board configuration information (including straps) */
+	lb_board_config(head);
+
 	/* Add architecture records. */
 	lb_arch_add_records(head);
 

src/lib/fw_config.c

@@ -7,18 +7,14 @@
 #include <device/device.h>
 #include <ec/google/chromeec/ec.h>
 #include <fw_config.h>
+#include <inttypes.h>
 #include <lib.h>
 #include <stdbool.h>
 #include <stdint.h>
 
-/**
+uint64_t fw_config_get(void)
- * fw_config_get() - Provide firmware configuration value.
- *
- * Return 32bit firmware configuration value determined for the system.
- */
-static uint32_t fw_config_get(void)
 {
-	static uint32_t fw_config_value;
+	static uint64_t fw_config_value;
 	static bool fw_config_value_initialized;
 
 	/* Nothing to prepare if setup is already done. */
@@ -35,7 +31,7 @@ static uint32_t fw_config_get(void)
 			       __func__);
 			fw_config_value = 0;
 		} else {
-			printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%08x\n",
+			printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n",
 			       fw_config_value);
 			return fw_config_value;
 		}
@@ -47,7 +43,7 @@ static uint32_t fw_config_get(void)
 			printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__);
 	}
 
-	printk(BIOS_INFO, "FW_CONFIG value is 0x%08x\n", fw_config_value);
+	printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value);
 	return fw_config_value;
 }
 
@@ -59,7 +55,8 @@ bool fw_config_probe(const struct fw_config *match)
 			printk(BIOS_INFO, "fw_config match found: %s=%s\n", match->field_name,
 			       match->option_name);
 		else
-			printk(BIOS_INFO, "fw_config match found: mask=0x%08x value=0x%08x\n",
+			printk(BIOS_INFO, "fw_config match found: mask=0x%" PRIx64 " value=0x%"
+			       PRIx64 "\n",
 			       match->mask, match->value);
 		return true;
 	}
@@ -70,20 +67,20 @@ bool fw_config_probe(const struct fw_config *match)
 #if ENV_RAMSTAGE
 
 /*
- * The maximum number of fw_config fields is limited by the 32-bit mask that is used to
+ * The maximum number of fw_config fields is limited by the 64-bit mask that is used to
  * represent them.
  */
-#define MAX_CACHE_ELEMENTS	(8 * sizeof(uint32_t))
+#define MAX_CACHE_ELEMENTS	(8 * sizeof(uint64_t))
 
 static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS];
 
-static size_t probe_index(uint32_t mask)
+static size_t probe_index(uint64_t mask)
 {
 	assert(mask);
-	return __ffs(mask);
+	return __ffs64(mask);
 }
 
-const struct fw_config *fw_config_get_found(uint32_t field_mask)
+const struct fw_config *fw_config_get_found(uint64_t field_mask)
 {
 	const struct fw_config *config;
 	config = cached_configs[probe_index(field_mask)];

src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb

@@ -45,70 +45,41 @@ chip northbridge/amd/agesa/family15tn/root_complex
 						end
 						device pnp 2e.6 off end # CIR
 						device pnp 2e.7 on	# GPIO6, GPIO7, GPIO8
-							irq 0xe0 = 0x7f
+							irq 0xf4 = 0xff # GPIO6 i/o
-							irq 0xe1 = 0x10
+
-							irq 0xe2 = 0x00
+							irq 0xe0 = 0x7f # GPIO7 i/o
-							irq 0xe3 = 0x00
+							irq 0xe1 = 0x00 # GPIO7 data
-							irq 0xe4 = 0xff
-							irq 0xe5 = 0xff
-							irq 0xe6 = 0xff
-							irq 0xe7 = 0xff
-							irq 0xec = 0x00
-							irq 0xed = 0xff
-							irq 0xf4 = 0xff
-							irq 0xf5 = 0xff
-							irq 0xf6 = 0x00
-							irq 0xf7 = 0x00
-							irq 0xf8 = 0x00
 						end
-						device pnp 2e.8 off	# WDT1, GPIO0, GPIO1
+						device pnp 2e.008 off	# WDT1
-							io  0x60 = 0x00
+						end
-							irq 0xe0 = 0xff
+						device pnp 2e.108 on	# GPIO0, GPIO1
-							irq 0xe1 = 0xff
+							irq 0xe0 = 0xff # GPIO0 i/o
-							irq 0xe2 = 0xff
+							irq 0xe2 = 0xff # GPIO0 inversion
-							irq 0xe3 = 0xff
+							irq 0xe4 = 0xff # GPIO0 multiplex
-							irq 0xe4 = 0xff
+
-							irq 0xf0 = 0xff
+							irq 0xf0 = 0xff # GPIO1 i/o
-							irq 0xf1 = 0x28
+							irq 0xf4 = 0x08 # GPIO1 multiplex
-							irq 0xf2 = 0x00
+
-							irq 0xf3 = 0x00
+							irq 0xf5 = 0xff # WDT1 control mode
-							irq 0xf4 = 0x08
+							irq 0xf6 = 0x00 # WDT1 counter
-							irq 0xf5 = 0xff
+							irq 0xf7 = 0xff # WDT1 control / status
-							irq 0xf6 = 0x00
-							irq 0xf7 = 0xff
 						end
 						device pnp 2e.009 off	# GPIO8
 						end
 						device pnp 2e.109 on	# GPIO1
 						end
 						device pnp 2e.209 on	# GPIO2
-							irq 0xe0 = 0xff
+							irq 0xe0 = 0xff # GPIO2 i/o
-							irq 0xe1 = 0x90
-							irq 0xe2 = 0x00
-							irq 0xe3 = 0x00
-							irq 0xe9 = 0x00
 						end
 						device pnp 2e.309 on	# GPIO3
-							irq 0xe4 = 0x7f
+							irq 0xe4 = 0x7f # GPIO3 i/o
-							irq 0xe5 = 0x76
+							irq 0xe5 = 0x00 # GPIO3 data
-							irq 0xe6 = 0x00
-							irq 0xe7 = 0x00
-							irq 0xea = 0x00
-							irq 0xfe = 0x00
 						end
 						device pnp 2e.409 on	# GPIO4
-							irq 0xe8 = 0x00
+							irq 0xf0 = 0xff # GPIO4 i/o
-							irq 0xf0 = 0xff
-							irq 0xf1 = 0x7b
-							irq 0xf2 = 0x00
-							irq 0xee = 0x00
 						end
 						device pnp 2e.509 on	# GPIO5
-							irq 0xeb = 0x00
+							irq 0xf4 = 0xff # GPIO5 i/o
-							irq 0xf4 = 0xff
-							irq 0xf5 = 0xef
-							irq 0xf6 = 0x00
-							irq 0xf7 = 0x00
 						end
 						device pnp 2e.609 on	# GPIO6
 						end
@@ -126,10 +97,10 @@ chip northbridge/amd/agesa/family15tn/root_complex
 						end
 						device pnp 2e.d off end	# WDT1
 						device pnp 2e.e off end # CIR WAKE-UP
-						device pnp 2e.f off	# GPIO Push-pull/Open-drain selection
+						device pnp 2e.f on	# GPIO Push-pull/Open-drain selection
 							irq 0xe6 = 7f
 						end
-						device pnp 2e.14 off # PORT80 UART
+						device pnp 2e.14 on	# PORT80 UART
 							irq 0xe0 = 0x00
 						end
 						device pnp 2e.16 off end # Deep Sleep

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -86,10 +86,12 @@ chip soc/intel/cannonlake
 			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 3
 		end
 		device pci 14.1 off end # USB xDCI (OTG)
-		chip drivers/wifi/generic # CNVi wifi
+		device pci 14.3 on
+			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
-			device pci 14.3 on end
+				device generic 0 on end
 			end
+		end  # CNVi wifi
 		device pci 14.5 off end # SDCard
 		device pci 15.0 on	# I2C #0
 			chip drivers/i2c/hid

src/mainboard/example/Kconfig

@@ -0,0 +1,15 @@
+if VENDOR_EXAMPLE
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/example/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/example/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Example"
+
+endif # VENDOR_EXAMPLE

src/mainboard/example/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_EXAMPLE
+	bool "Example boards"

src/mainboard/example/min86/Kconfig

@@ -0,0 +1,14 @@
+if BOARD_EXAMPLE_MIN86
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_EXAMPLE_MIN86
+	select MISSING_BOARD_RESET
+
+config MAINBOARD_DIR
+	default "example/min86"
+
+config MAINBOARD_PART_NUMBER
+	default "Min86"
+
+endif

src/mainboard/example/min86/Kconfig.name

@@ -0,0 +1,11 @@
+config BOARD_EXAMPLE_MIN86
+	bool "Minimal x86 fake board"
+	help
+	  This example mainboard code along with the example/min86 SoC
+	  should serve as a minimal example how a buildable x86 SoC code
+	  base can look like.
+
+	  This can serve, for instance, as a basis to add new SoCs to
+	  coreboot. Starting with a buildable commit should help with
+	  the review of the actual code, and also avoid any regressions
+	  when common coreboot code changes.

src/mainboard/example/min86/board_info.txt

@@ -0,0 +1 @@
+Category: misc

src/mainboard/example/min86/devicetree.cb

@@ -0,0 +1,6 @@
+chip soc/example/min86
+
+	device domain 0 on
+	end
+
+end

src/mainboard/google/auron/devicetree.cb

@@ -26,7 +26,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# EC range is 0x800-0x9ff
 			register "gen1_dec" = "0x00fc0801"
 			register "gen2_dec" = "0x00fc0901"
@@ -83,6 +83,6 @@ chip soc/intel/broadwell
 			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 off end # SMBus
 			device pci 1f.6 on  end # Thermal
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/auron_paine/overridetree.cb

@@ -8,10 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
-#		end
+
+			device pci 1f.2 on  end # SATA Controller
+		end
 	end
 end

src/mainboard/google/auron/variants/auron_yuna/overridetree.cb

@@ -8,10 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x7"
 			register "sata_port1_gen3_dtle" = "0x5"
-#		end
+
+			device pci 1f.2 on  end # SATA Controller
+		end
 	end
 end

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	register "s0ix_enable" = "0"
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			register "sata_devslp_disable" = "0x1"
 
 			register "sio_i2c0_voltage" = "1" # 1.8V
@@ -34,7 +34,8 @@ chip soc/intel/broadwell
 			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.2 on  end # PCIe Port #3 - LAN (becomes RP1)
 			device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
+			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 on  end # SMBus
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/gandof/overridetree.cb

@@ -8,10 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
-#		end
+
+			device pci 1f.2 on  end # SATA Controller
+		end
 	end
 end

src/mainboard/google/auron/variants/lulu/overridetree.cb

@@ -8,10 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
-#		end
+
+			device pci 1f.2 on  end # SATA Controller
+		end
 	end
 end

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -17,7 +17,7 @@ chip soc/intel/broadwell
 	register "s0ix_enable" = "0"
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			register "sata_port0_gen3_tx" = "0x72"
 
 			# Set I2C0 to 1.8V
@@ -36,6 +36,7 @@ chip soc/intel/broadwell
 			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.2 on  end # PCIe Port #3
 			device pci 1d.0 off end # USB2 EHCI
-#		end
+			device pci 1f.2 on  end # SATA Controller
+		end
 	end
 end

src/mainboard/google/dedede/board_info.c

@@ -3,7 +3,7 @@
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 
-int board_info_get_fw_config(uint32_t *fw_config)
+int board_info_get_fw_config(uint64_t *fw_config)
 {
 	return google_chromeec_cbi_get_fw_config(fw_config);
 }

src/mainboard/google/dedede/variants/baseboard/devicetree.cb

@@ -302,10 +302,12 @@ chip soc/intel/jasperlake
 		end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 off end # PMC SRAM
+		device pci 14.3 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
-			device pci 14.3 on  end # CNVi wifi
+				device generic 0 on end
 			end
+		end # CNVi wifi
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C 0
 		device pci 15.1 on  end # I2C 1

src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h

@@ -21,7 +21,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num);
  * @param fw_config	Address where the fw_config is stored.
  * @return 0 on success or negative integer for errors.
  */
-int board_info_get_fw_config(uint32_t *fw_config);
+int board_info_get_fw_config(uint64_t *fw_config);
 
 /* Return memory configuration structure. */
 const struct mb_cfg *variant_memcfg_config(void);

src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc

@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 ## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
 
-SPD_SOURCES = placeholder.spd.hex
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += lp4x-spd-4.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += lp4x-spd-3.hex      # ID = 2(0b0010)  Parts = K4UBE3D4AA-MGCR

src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt

@@ -1 +1,6 @@
 DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:E       0 (0000)
+K4U6E3S4AA-MGCR                0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E1G32D2NP-046 WT:A         1 (0001)
+K4UBE3D4AA-MGCR                2 (0010)

src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt

@@ -1,6 +1,5 @@
-# This is a CSV file containing a list of memory parts used by this variant.
+MT53E512M32D2NP-046 WT:E
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+K4U6E3S4AA-MGCR
-# gen_part_id tool from util/spd_tools/lp4x
+H9HCNNNBKMMLXR-NEE
-# See util/spd_tools/lp4x/README.md for more details and instructions.
+MT53E1G32D2NP-046 WT:A
-
+K4UBE3D4AA-MGCR
-# Part Name