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AGESA,binaryPI boards: Drop invalid MP table files

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If we spot any error in the file, treat it as untested and
broken copy-paste.

Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-12-22 09:49:56 +02:00
parent 27f340e777
commit 0dd6ee783f
53 changed files with 0 additions and 3593 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/amd/gardenia/Kconfig
View File

@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
select AMD_APU_STONEYRIDGE
select AMD_APU_PKG_FP4
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA

148
src/mainboard/amd/gardenia/mptable.c
View File

@@ -1,148 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <soc/southbridge.h>
#include <amdblocks/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), \
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
(intr), (apicid), (pin))
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, \
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
(((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/inagua/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_SMSC_KBC1100
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA

114
src/mainboard/amd/inagua/mptable.c
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/olivehill/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

144
src/mainboard/amd/olivehill/mptable.c
View File

@@ -1,144 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/parmer/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

142
src/mainboard/amd/parmer/mptable.c
View File

@@ -1,142 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/persimmon/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

128
src/mainboard/amd/persimmon/mptable.c
View File

@@ -1,128 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
/* IDE */
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/south_station/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

114
src/mainboard/amd/south_station/mptable.c
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/thatcher/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_SMSC_LPC47N217

142
src/mainboard/amd/thatcher/mptable.c
View File

@@ -1,142 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/amd/union_station/Kconfig
View File

@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA

114
src/mainboard/amd/union_station/mptable.c
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/asrock/e350m1/Kconfig
View File

@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

114
src/mainboard/asrock/e350m1/mptable.c
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "ASROCK ", 8);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/asrock/imb-a180/Kconfig
View File

@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_WINBOND_W83627UHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

144
src/mainboard/asrock/imb-a180/mptable.c
View File

@@ -1,144 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/asus/am1i-a/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select USE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB

109
src/mainboard/asus/am1i-a/mptable.c
View File

@@ -1,109 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
/* GPP Ports */
PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* USB */
PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]);
/* PCIe slot & Onboard NIC */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/asus/f2a85-m/Kconfig
View File

@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE

136
src/mainboard/asus/f2a85-m/mptable.c
View File

@@ -1,136 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
PCI_INT(0x0, 0x0, 0x1, 0x11);
PCI_INT(0x0, 0x0, 0x2, 0x12);
PCI_INT(0x0, 0x0, 0x3, 0x13);
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/bap/ode_e20XX/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

145
src/mainboard/bap/ode_e20XX/mptable.c
View File

@@ -1,145 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
/* PCI_SLOT 1 */
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
/* PCI_SLOT 2 */
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/biostar/a68n_5200/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_ITE_IT8728F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

144
src/mainboard/biostar/a68n_5200/mptable.c
View File

@@ -1,144 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/biostar/am1ml/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select GFXUMA
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB

145
src/mainboard/biostar/am1ml/mptable.c
View File

@@ -1,145 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
/* PCI_SLOT 1 */
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
/* PCI_SLOT 2 */
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
}
/* PCIe Lan*/
//PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/elmex/pcm205400/Kconfig
View File

@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

128
src/mainboard/elmex/pcm205400/mptable.c
View File

@@ -1,128 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
/* IDE */
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/gizmosphere/gizmo/Kconfig
View File

@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048

114
src/mainboard/gizmosphere/gizmo/mptable.c
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/gizmosphere/gizmo2/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

145
src/mainboard/gizmosphere/gizmo2/mptable.c
View File

@@ -1,145 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
/* PCI_SLOT 1 */
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
/* PCI_SLOT 2 */
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

148
src/mainboard/google/kahlee/mptable.c
View File

@@ -1,148 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <soc/southbridge.h>
#include <amdblocks/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), \
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
(intr), (apicid), (pin))
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, \
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
(((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/hp/abm/Kconfig
View File

@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_NUVOTON_NCT5104D
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192

144
src/mainboard/hp/abm/mptable.c
View File

@@ -1,144 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/hp/pavilion_m6_1035dx/Kconfig
View File

@@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES

148
src/mainboard/hp/pavilion_m6_1035dx/mptable.c
View File

@@ -1,148 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x00, 0x0, 0x10);
PCI_INT(0x0, 0x00, 0x1, 0x11);
PCI_INT(0x0, 0x00, 0x2, 0x12);
PCI_INT(0x0, 0x00, 0x3, 0x13);
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/jetway/nf81-t56n-lf/Kconfig
View File

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048

128
src/mainboard/jetway/nf81-t56n-lf/mptable.c
View File

@@ -1,128 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <drivers/generic/ioapic/chip.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
/* IDE */
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* On-board NIC & Slot PCIE. */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
}
/* On-board Realtek NIC 2. (PCIe PortA) */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/lenovo/g505s/Kconfig
View File

@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES

148
src/mainboard/lenovo/g505s/mptable.c
View File

@@ -1,148 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x00, 0x0, 0x10);
PCI_INT(0x0, 0x00, 0x1, 0x11);
PCI_INT(0x0, 0x00, 0x2, 0x12);
PCI_INT(0x0, 0x00, 0x3, 0x13);
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/lippert/frontrunner-af/Kconfig
View File

@@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME

114
src/mainboard/lippert/frontrunner-af/mptable.c
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/msi/ms7721/Kconfig
View File

@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_FINTEK_F71869AD
select BOARD_ROMSIZE_KB_8192

136
src/mainboard/msi/ms7721/mptable.c
View File

@@ -1,136 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
PCI_INT(0x0, 0x0, 0x1, 0x11);
PCI_INT(0x0, 0x0, 0x2, 0x12);
PCI_INT(0x0, 0x0, 0x3, 0x13);
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/pcengines/apu1/Kconfig
View File

@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE

119
src/mainboard/pcengines/apu1/mptable.c
View File

@@ -1,119 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
/* IDE */
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
/* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
/* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
return (unsigned long)smp_write_config_table(v);
}

1
src/mainboard/pcengines/apu2/Kconfig
View File

@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select DEFAULT_POST_ON_LPC
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select HAVE_SPD_IN_CBFS

112
src/mainboard/pcengines/apu2/mptable.c
View File

@@ -1,112 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <northbridge/amd/nb_common.h>
#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24);
ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF);
smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* SD card */
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
/* GPP0 */
PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
/* GPP1 */
PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
/* GPP2 */
PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
/* GPP3 */
PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
/* GPP4 */
PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
return (unsigned long)smp_write_config_table(v);
}