AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
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select AMD_APU_STONEYRIDGE
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select AMD_APU_PKG_FP4
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192
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select GFXUMA
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@@ -1,148 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <soc/southbridge.h>
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#include <amdblocks/amd_pci_util.h>
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
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{
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mc->mpc_length += length;
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mc->mpc_entry_count++;
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}
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static void my_smp_write_bus(struct mp_config_table *mc,
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unsigned char id, const char *bustype)
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{
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struct mpc_config_bus *mpc;
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mpc = smp_next_mpc_entry(mc);
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memset(mpc, '\0', sizeof(*mpc));
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mpc->mpc_type = MP_BUS;
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mpc->mpc_busid = id;
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memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
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smp_add_mpc_entry(mc, sizeof(*mpc));
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}
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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/*
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* By the time this function gets called, the IOAPIC registers
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* have been written so they can be read to get the correct
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* APIC ID and Version
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*/
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u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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memcpy(mc->mpc_oem, "AMD ", 8);
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smp_write_processors(mc);
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//mptable_write_buses(mc, NULL, &bus_isa);
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my_smp_write_bus(mc, 0, "PCI ");
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my_smp_write_bus(mc, 1, "PCI ");
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bus_isa = 0x02;
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my_smp_write_bus(mc, bus_isa, "ISA ");
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/* I/O APICs: APIC ID Version State Address */
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), \
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
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(intr), (apicid), (pin))
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, \
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MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
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(((dev)<<2)|(int_sign)), ioapic_id, (pin))
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/* Internal VGA */
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PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
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/* SMBUS */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* HD Audio */
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PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
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PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
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/* on board NIC & Slot PCIE. */
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/* PCI slots */
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struct device *dev = pcidev_on_root(0x14, 4);
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if (dev && dev->enabled) {
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u8 bus_pci = dev->link_list->secondary;
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/* PCI_SLOT 0. */
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PCI_INT(bus_pci, 0x5, 0x0, 0x14);
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PCI_INT(bus_pci, 0x5, 0x1, 0x15);
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PCI_INT(bus_pci, 0x5, 0x2, 0x16);
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PCI_INT(bus_pci, 0x5, 0x3, 0x17);
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/* PCI_SLOT 1. */
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PCI_INT(bus_pci, 0x6, 0x0, 0x15);
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PCI_INT(bus_pci, 0x6, 0x1, 0x16);
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PCI_INT(bus_pci, 0x6, 0x2, 0x17);
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PCI_INT(bus_pci, 0x6, 0x3, 0x14);
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/* PCI_SLOT 2. */
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PCI_INT(bus_pci, 0x7, 0x0, 0x16);
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PCI_INT(bus_pci, 0x7, 0x1, 0x17);
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PCI_INT(bus_pci, 0x7, 0x2, 0x14);
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PCI_INT(bus_pci, 0x7, 0x3, 0x15);
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}
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/* PCIe Lan*/
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PCI_INT(0x0, 0x06, 0x0, 0x13);
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/* FCH PCIe PortA */
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PCI_INT(0x0, 0x15, 0x0, 0x10);
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/* FCH PCIe PortB */
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PCI_INT(0x0, 0x15, 0x1, 0x11);
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/* FCH PCIe PortC */
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PCI_INT(0x0, 0x15, 0x2, 0x12);
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/* FCH PCIe PortD */
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PCI_INT(0x0, 0x15, 0x3, 0x13);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
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select SUPERIO_SMSC_KBC1100
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select GFXUMA
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@@ -1,114 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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/*
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* By the time this function gets called, the IOAPIC registers
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* have been written so they can be read to get the correct
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* APIC ID and Version
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*/
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u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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memcpy(mc->mpc_oem, "AMD ", 8);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &bus_isa);
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/* I/O APICs: APIC ID Version State Address */
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
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/* APU Internal Graphic Device*/
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PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
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//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* Southbridge HD Audio: */
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PCI_INT(0x0, 0x14, 0x2, 0x12);
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
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PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
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/* on board NIC & Slot PCIE. */
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/* PCI slots */
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struct device *dev = pcidev_on_root(0x14, 4);
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if (dev && dev->enabled) {
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u8 bus_pci = dev->link_list->secondary;
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/* PCI_SLOT 0. */
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PCI_INT(bus_pci, 0x5, 0x0, 0x14);
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PCI_INT(bus_pci, 0x5, 0x1, 0x15);
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PCI_INT(bus_pci, 0x5, 0x2, 0x16);
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PCI_INT(bus_pci, 0x5, 0x3, 0x17);
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/* PCI_SLOT 1. */
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PCI_INT(bus_pci, 0x6, 0x0, 0x15);
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PCI_INT(bus_pci, 0x6, 0x1, 0x16);
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PCI_INT(bus_pci, 0x6, 0x2, 0x17);
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PCI_INT(bus_pci, 0x6, 0x3, 0x14);
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/* PCI_SLOT 2. */
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PCI_INT(bus_pci, 0x7, 0x0, 0x16);
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PCI_INT(bus_pci, 0x7, 0x1, 0x17);
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PCI_INT(bus_pci, 0x7, 0x2, 0x14);
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PCI_INT(bus_pci, 0x7, 0x3, 0x15);
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}
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/* PCIe PortA */
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PCI_INT(0x0, 0x15, 0x0, 0x10);
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/* PCIe PortB */
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PCI_INT(0x0, 0x15, 0x1, 0x11);
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/* PCIe PortC */
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PCI_INT(0x0, 0x15, 0x2, 0x12);
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/* PCIe PortD */
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PCI_INT(0x0, 0x15, 0x3, 0x13);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
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select DEFAULT_POST_ON_LPC
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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@@ -1,144 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
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{
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mc->mpc_length += length;
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mc->mpc_entry_count++;
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}
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static void my_smp_write_bus(struct mp_config_table *mc,
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unsigned char id, const char *bustype)
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{
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struct mpc_config_bus *mpc;
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mpc = smp_next_mpc_entry(mc);
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memset(mpc, '\0', sizeof(*mpc));
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mpc->mpc_type = MP_BUS;
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mpc->mpc_busid = id;
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memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
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smp_add_mpc_entry(mc, sizeof(*mpc));
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}
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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/*
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* By the time this function gets called, the IOAPIC registers
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* have been written so they can be read to get the correct
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* APIC ID and Version
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*/
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u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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memcpy(mc->mpc_oem, "AMD ", 8);
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smp_write_processors(mc);
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//mptable_write_buses(mc, NULL, &bus_isa);
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my_smp_write_bus(mc, 0, "PCI ");
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my_smp_write_bus(mc, 1, "PCI ");
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bus_isa = 0x02;
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my_smp_write_bus(mc, bus_isa, "ISA ");
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/* I/O APICs: APIC ID Version State Address */
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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/* Internal VGA */
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PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
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/* SMBUS */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* HD Audio */
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PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
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PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
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||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
|
@@ -1,142 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_FINTEK_F81865F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
|
@@ -1,128 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* IDE */
|
||||
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_FINTEK_F81865F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
|
@@ -1,114 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device*/
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* Southbridge HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select SUPERIO_SMSC_LPC47N217
|
||||
|
@@ -1,142 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SOUTHBRIDGE_AMD_CIMX_SB800
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
select GFXUMA
|
||||
|
@@ -1,114 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device*/
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* Southbridge HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SB_SUPERIO_HWM
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
|
@@ -1,114 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "ASROCK ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device*/
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* Southbridge HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_WINBOND_W83627UHG
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
|
@@ -1,144 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select USE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
|
@@ -1,109 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
|
||||
/* GPP Ports */
|
||||
PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* PCIe slot & Onboard NIC */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SOUTHBRIDGE_AMD_AGESA_HUDSON
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
|
||||
|
@@ -1,136 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* IOMMU */
|
||||
PCI_INT(0x0, 0x0, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x0, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x0, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x0, 0x3, 0x13);
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
|
@@ -1,145 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
|
||||
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
|
||||
|
||||
/* PCI_SLOT 1 */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
|
||||
|
||||
/* PCI_SLOT 2 */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_ITE_IT8728F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
select GFXUMA
|
||||
|
@@ -1,144 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select GFXUMA
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
|
||||
|
@@ -1,145 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
|
||||
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
|
||||
|
||||
/* PCI_SLOT 1 */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
|
||||
|
||||
/* PCI_SLOT 2 */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
//PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_FINTEK_F81865F
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
|
@@ -1,128 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* IDE */
|
||||
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SOUTHBRIDGE_AMD_CIMX_SB800
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
|
@@ -1,114 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device*/
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* Southbridge HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_4096
|
||||
|
@@ -1,145 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
|
||||
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
|
||||
|
||||
/* PCI_SLOT 1 */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
|
||||
|
||||
/* PCI_SLOT 2 */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -1,148 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <amdblocks/amd_pci_util.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), \
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
|
||||
(intr), (apicid), (pin))
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, \
|
||||
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
|
||||
(((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_NUVOTON_NCT5104D
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
|
||||
|
@@ -1,144 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select EC_COMPAL_ENE932
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_SMI_HANDLER
|
||||
select HAVE_ACPI_TABLES
|
||||
|
@@ -1,148 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* IOMMU */
|
||||
PCI_INT(0x0, 0x00, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x00, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x00, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x00, 0x3, 0x13);
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_FINTEK_F71869AD
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
|
@@ -1,128 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* IDE */
|
||||
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* On-board NIC & Slot PCIE. */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
}
|
||||
|
||||
/* On-board Realtek NIC 2. (PCIe PortA) */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select EC_COMPAL_ENE932
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_SMI_HANDLER
|
||||
select HAVE_ACPI_TABLES
|
||||
|
@@ -1,148 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* IOMMU */
|
||||
PCI_INT(0x0, 0x00, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x00, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x00, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x00, 0x3, 0x13);
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
|
||||
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
|
||||
#select HAVE_ACPI_RESUME
|
||||
|
@@ -1,114 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device*/
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* Southbridge HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SOUTHBRIDGE_AMD_AGESA_HUDSON
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select SUPERIO_FINTEK_F71869AD
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
|
@@ -1,136 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* IOMMU */
|
||||
PCI_INT(0x0, 0x0, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x0, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x0, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x0, 0x3, 0x13);
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SOUTHBRIDGE_AMD_CIMX_SB800
|
||||
select SUPERIO_NUVOTON_NCT5104D
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_OPTION_TABLE
|
||||
|
@@ -1,119 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* IDE */
|
||||
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DEFAULT_POST_ON_LPC
|
||||
select SUPERIO_NUVOTON_NCT5104D
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select HAVE_SPD_IN_CBFS
|
||||
|
@@ -1,112 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <stdint.h>
|
||||
#include <northbridge/amd/nb_common.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/* Initialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24);
|
||||
ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* SD card */
|
||||
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
/* GPP0 */
|
||||
PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
|
||||
/* GPP1 */
|
||||
PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
|
||||
/* GPP2 */
|
||||
PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
|
||||
/* GPP3 */
|
||||
PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
|
||||
/* GPP4 */
|
||||
PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
Reference in New Issue
Block a user