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Drop ROMCC code and header guards

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Change-Id: I730f80afd8aad250f26534435aec24bea75a849c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans
2019-11-28 16:05:08 +01:00
committed by Kyösti Mälkki
parent 4f66cb9b28
commit 1cb9cd5798
35 changed files with 13 additions and 299 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/include/cpu/amd/mtrr.h
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@@ -38,7 +38,7 @@
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
#if !defined(__ASSEMBLER__)
#include <cpu/x86/msr.h>

17
src/include/cpu/x86/cache.h
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@@ -23,28 +23,11 @@
#if !defined(__ASSEMBLER__)
/*
* Need two versions because ROMCC chokes on certain clobbers:
* cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
* 0x1559920 asm Internal compiler error: lhs 1 regcm == 0
*/
#if defined(__GNUC__)
static inline void wbinvd(void)
{
asm volatile ("wbinvd" ::: "memory");
}
#else
static inline void wbinvd(void)
{
asm volatile ("wbinvd");
}
#endif
static inline void invd(void)
{
asm volatile("invd" ::: "memory");

5
src/include/cpu/x86/cr.h
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@@ -20,12 +20,7 @@
#include <stdint.h>
/* ROMCC apparently chokes certain clobber registers. */
#if defined(__ROMCC__)
#define COMPILER_BARRIER
#else
#define COMPILER_BARRIER "memory"
#endif
#ifdef __x86_64__
#define CRx_TYPE uint64_t

16
src/include/cpu/x86/msr.h
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@@ -81,21 +81,6 @@
#ifndef __ASSEMBLER__
#include <types.h>
#if defined(__ROMCC__)
typedef __builtin_msr_t msr_t;
static msr_t rdmsr(unsigned long index)
{
return __builtin_rdmsr(index);
}
static void wrmsr(unsigned long index, msr_t msr)
{
__builtin_wrmsr(index, msr.lo, msr.hi);
}
#else
typedef struct msr_struct {
unsigned int lo;
@@ -154,7 +139,6 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr)
}
#endif /* CONFIG_SOC_SETS_MSRS */
#endif /* __ROMCC__ */
/* Helpers for interpreting MC[i]_STATUS */

6
src/include/cpu/x86/mtrr.h
View File

@@ -53,7 +53,7 @@
#define MTRR_FIX_4K_F0000 0x26e
#define MTRR_FIX_4K_F8000 0x26f
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if !defined(__ASSEMBLER__)
#include <stdint.h>
#include <stddef.h>
@@ -140,9 +140,9 @@ static inline unsigned int fls(unsigned int x)
"1:" : "=r" (r) : "mr" (x));
return r;
}
#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */
#endif /* !defined(__ASSEMBLER__) */
/* Align up/down to next power of 2, suitable for ROMCC and assembler
/* Align up/down to next power of 2, suitable for assembler
too. Range of result 256kB to 128MB is good enough here. */
#define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))

3
src/include/cpu/x86/tsc.h
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@@ -28,7 +28,6 @@ static inline tsc_t rdtsc(void)
return res;
}
#if !defined(__ROMCC__)
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
* This code is used to prevent use of libgcc's umoddi3.
*/
@@ -42,7 +41,6 @@ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
}
/* Too many registers for ROMCC */
static inline unsigned long long rdtscll(void)
{
unsigned long long val;
@@ -58,7 +56,6 @@ static inline uint64_t tsc_to_uint64(tsc_t tstamp)
{
return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
}
#endif
/* Provided by CPU/chipset code for the TSC rate in MHz. */
unsigned long tsc_freq_mhz(void);