mb/system76/tgl-u: Restore old FSP configs

Re-add FSP-S configs from the 4.13 branch, which were not included when
upstreamed.

Change-Id: I5f99d088190df07213c5b615f36fde29831aad86
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/system76/tgl-u/Makefile.inc

@@ -9,5 +9,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 
 SPD_SOURCES = samsung-M471A1G44AB0-CWE

src/mainboard/system76/tgl-u/ramstage.c

@@ -3,12 +3,6 @@
 #include <mainboard/gpio.h>
 #include <soc/ramstage.h>
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	// Disable AER to fix suspend failing with some SSDs.
-	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
-}
-
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();

src/mainboard/system76/tgl-u/variants/darp7/ramstage.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// CPU RP Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+}

src/mainboard/system76/tgl-u/variants/galp5/ramstage.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// CPU RP Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+}

src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// CPU RP Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+}