Change AMD FW offsets to support 32 MiB SPI chips

Change-Id: Ie5b056c60186fe9d64d260d788b2ac19c1f5b481
2022-02-25 09:12:56 -07:00
parent 69538eaa4b
commit 22ebfff812
1 changed files with 1 additions and 1 deletions
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -346,7 +346,7 @@ typedef struct _context {
 	uint32_t current;	/* pointer within flash & proxy buffer */
 } context;

-#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
+#define RUN_BASE(ctx) (0)
 #define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
 #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
 #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))