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Change AMD FW offsets to support 32 MiB SPI chips

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Change-Id: Ie5b056c60186fe9d64d260d788b2ac19c1f5b481
This commit is contained in:
Jeremy Soller
2022-02-25 09:12:56 -07:00
parent 69538eaa4b
commit 22ebfff812
1 changed files with 1 additions and 1 deletions
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util/amdfwtool/amdfwtool.c
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@@ -346,7 +346,7 @@ typedef struct _context {
uint32_t current; /* pointer within flash & proxy buffer */ uint32_t current; /* pointer within flash & proxy buffer */
} context; } context;
#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) #define RUN_BASE(ctx) (0)
#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) #define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
#define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
#define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))