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soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0

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MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and
POSTCAR_STAGE which are used by all Xeon-SP platforms.

After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0
is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X,
POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE.

TEST=Build and boot on intel/archercity CRB

Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu
2024-04-10 01:42:06 +08:00
committed by Lean Sheng Tan
parent e2dd36c6bc
commit 2f9a579048
10 changed files with 1 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/bytedance/bd_egs/Kconfig
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@@ -5,7 +5,6 @@ if BOARD_BYTEDANCE_BD_EGS
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_65536 select BOARD_ROMSIZE_KB_65536
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_SAPPHIRERAPIDS_SP
select SUPERIO_ASPEED_AST2400 select SUPERIO_ASPEED_AST2400
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES

1
src/mainboard/ibm/sbp1/Kconfig
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@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
select IPMI_KCS select IPMI_KCS
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM select MEMORY_MAPPED_TPM
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_SAPPHIRERAPIDS_SP
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_GBE_REGION

1
src/mainboard/intel/archercity_crb/Kconfig
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@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select IPMI_OCP select IPMI_OCP
select MEMORY_MAPPED_TPM select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_SAPPHIRERAPIDS_SP
select SUPERIO_ASPEED_AST2400 select SUPERIO_ASPEED_AST2400
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES

1
src/mainboard/intel/cedarisland_crb/Kconfig
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@@ -5,7 +5,6 @@ if BOARD_INTEL_CEDARISLAND_CRB
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_65536 select BOARD_ROMSIZE_KB_65536
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_COOPERLAKE_SP select SOC_INTEL_COOPERLAKE_SP
select SUPERIO_ASPEED_AST2400 select SUPERIO_ASPEED_AST2400
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES

1
src/mainboard/inventec/transformers/Kconfig
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@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select IPMI_KCS_ROMSTAGE select IPMI_KCS_ROMSTAGE
select MEMORY_MAPPED_TPM select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_SAPPHIRERAPIDS_SP
select SUPERIO_ASPEED_AST2400 select SUPERIO_ASPEED_AST2400
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES

1
src/mainboard/ocp/deltalake/Kconfig
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@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_65536 select BOARD_ROMSIZE_KB_65536
select CONSOLE_OVERRIDE_LOGLEVEL select CONSOLE_OVERRIDE_LOGLEVEL
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_COOPERLAKE_SP select SOC_INTEL_COOPERLAKE_SP
select SUPERIO_ASPEED_AST2400 select SUPERIO_ASPEED_AST2400
select IPMI_KCS select IPMI_KCS

1
src/mainboard/ocp/tiogapass/Kconfig
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@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
select IPMI_KCS select IPMI_KCS
select IPMI_KCS_ROMSTAGE select IPMI_KCS_ROMSTAGE
select IPMI_OCP select IPMI_OCP
select MAINBOARD_USES_FSP2_0
select OCP_DMI select OCP_DMI
select SOC_INTEL_SKYLAKE_SP select SOC_INTEL_SKYLAKE_SP
select SUPERIO_ASPEED_AST2400 select SUPERIO_ASPEED_AST2400

7
src/soc/intel/xeon_sp/Kconfig
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@@ -45,15 +45,10 @@ config XEON_SP_COMMON_BASE
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select POSTCAR_STAGE
if XEON_SP_COMMON_BASE if XEON_SP_COMMON_BASE
config MAINBOARD_USES_FSP2_0
bool
default y
select PLATFORM_USES_FSP2_0
select POSTCAR_STAGE
config MAX_SOCKET config MAX_SOCKET
int int
default 2 default 2

5
src/soc/intel/xeon_sp/skx/Kconfig
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@@ -11,13 +11,8 @@ config SOC_INTEL_SKYLAKE_SP
if SOC_INTEL_SKYLAKE_SP if SOC_INTEL_SKYLAKE_SP
config MAINBOARD_USES_FSP2_0
bool
default y
config FSP_HEADER_PATH config FSP_HEADER_PATH
string "Location of FSP headers" string "Location of FSP headers"
depends on MAINBOARD_USES_FSP2_0
default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
config MAX_SOCKET config MAX_SOCKET

1
src/soc/intel/xeon_sp/spr/Kconfig
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@@ -28,7 +28,6 @@ config CHIPSET_DEVICETREE
config FSP_HEADER_PATH config FSP_HEADER_PATH
string "Location of FSP headers" string "Location of FSP headers"
depends on MAINBOARD_USES_FSP2_0
default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp" default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp"
config MAX_CPUS config MAX_CPUS