Merge remote-tracking branch 'upstream/master' into system76

2019-10-02 08:05:15 -06:00 · 2019-10-02 08:05:15 -06:00 · 3e2083ba43
commit 3e2083ba43
parent 00b6224b65 3d4923d85a
256 changed files with 1635 additions and 1222 deletions
--- a/Documentation/mainboard/amd/index.md
+++ b/Documentation/mainboard/amd/index.md
@ -0,0 +1,7 @@
+# AMD platforms documentation
+
+This section contains documentation about specific AMD mainboards.
+
+## Mainboard
+
+- [padmelon](padmelon/padmelon.md)
--- a/Documentation/mainboard/amd/padmelon/padmelon.jpg
+++ b/Documentation/mainboard/amd/padmelon/padmelon.jpg
--- a/Documentation/mainboard/amd/padmelon/padmelon.md
+++ b/Documentation/mainboard/amd/padmelon/padmelon.md
@ -0,0 +1,80 @@
+# Padmelon board
+
+## Specs (with Merlin Falcon SOC)
+
+* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
+  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
+* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
+  code is specific for Merlin Falcon SOC. Some specs will change if not
+  using Merlin Falcon.
+* One half mini PCI-Express slot on back side of mainboard
+* One PCI Express® 3.0 x8 slot
+* Two SATA3 ports with 6Gb/s data transfer rate
+* Two USB 2.0 ports at rear panel
+* Two USB 3.0 ports at rear panel
+* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
+* 6-channel High-Definition audio from Realtek ALC662 codec
+* One soldered down SPI flash with dediprog header
+
+## Mainboard
+
+![mainboard][padmelon]
+
+Three items are marked in this picture
+1. dediprog header
+2. memory dimms, address 0xA0 and 0xA4
+3. SATA cables connected to motherboard
+
+## Back panel
+
+![back panel][padmelon_io]
+
+* The lower serial port is UART A (debug serial)
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+--------------------+
+| Type                | Value              |
+=====================+====================+
+| Socketed flash      | no                 |
+---------------------+--------------------+
+| Model               | Macronix MX256435E |
+---------------------+--------------------+
+| Size                | 8 MiB              |
+---------------------+--------------------+
+| Flash programing    | dediprog header    |
+---------------------+--------------------+
+| Package             | SOIC-8             |
+---------------------+--------------------+
+| Write protection    | No                 |
+---------------------+--------------------+
+```
+
+## Technology
+
+```eval_rst
+---------------+------------------------------+
+| Fan control   | Using fintek F81803A         |
+---------------+------------------------------+
+| CPU           | Merlin Falcon (see reference)|
+---------------+------------------------------+
+```
+
+## Description of pictures within this document
+
+```eval_rst
+----------------------------+----------------------------------------+
+|padmelon.jpg                | Motherboard with components identified |
+----------------------------+----------------------------------------+
+|padmelon_io.jpg             | Back panel picture                     |
+----------------------------+----------------------------------------+
+```
+
+## Reference
+
+[Merlin Falcon BKDG][merlinfalcon]
+
+[merlinfalcon]: ../../soc/amd/family15h.md
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg
--- a/Documentation/mainboard/amd/padmelon/padmelon_io.jpg
+++ b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg
--- a/Documentation/soc/amd/family15h.md
+++ b/Documentation/soc/amd/family15h.md
@ -0,0 +1,49 @@
+# AMD Family 15h [SOC|Processors]
+
+## Abstract
+
+Family 15h is a line of AMD x86 products first introduced in 2011. The initial
+microarchitecture, codenamed "Bulldozer", introduced the concept of a "Compute
+Unit" (CU) where some parts of the processor are shared between two cores and
+some parts are unique for each core. Family 15h offerings matured into various
+models with increased performance and features targeting Enterprise, Client,
+and Embedded designs. Notice that a particular model can address more than one
+market(see models references below).
+
+## Introduction
+
+The first CU designs were 2 x86 cores with separate integer processors but
+sharing cache, code branch prediction engine and floating point processor. A die
+can have up to 8 CU. The floating point processor is composed of two symmetrical
+128-bit FMAC. Provided each x86 core is doing 128-bit floating point arithmetic,
+they both do floating point simultaneously. If one is doing 256-bit floating
+point, the other x86 core can't do floating point simultaneously. Later models
+changed how resources were shared, and introduced other performance improvements.
+
+Family 15h products range from SOCs to 3-chip solutions. Devices designed to
+contain on-die graphics (including headless) are commonly referred to as APUs,
+not CPUs.
+
+Later SOCs include a Platform Security Processor (PSP), a small ARM processor
+responsible for security related measures: For example, if secure boot is
+enabled, the cores will not exit reset until the BIOS image within the SPI
+flash is authenticated through its OEM signature, thus ensuring that only OEM
+produced BIOS can run the platform.
+
+Support in coreboot for modern AMD products is based on AMD’s reference code:
+AMD Generic Encapsulated Software Architecture (AGESA™). AGESA contains the
+code for enabling DRAM, configuring proprietary core logic, assistance with
+generating ACPI tables, and other features.
+
+While coreboot contains support for most models, some implementations use a
+separate cpu/north/south bridge directory structure. Newer products for models
+60h-6Fh (Merlin Falcon) and 70h-7Fh (Stoney Ridge) rely on modern SOC directory
+structure.
+
+## References
+
+1. [Models 00h-0Fh BKDG](https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf)
+2. [Models 10h-1Fh BKDG](https://www.amd.com/system/files/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf)
+3. [Models 30h-3Fh BKDG](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
+4. [Models 60h-6Fh BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf)
+5. [Models 70h-7Fh BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf)
--- a/Documentation/soc/amd/index.md
+++ b/Documentation/soc/amd/index.md
@ -4,5 +4,6 @@ This section contains documentation about coreboot on specific AMD SOCs.

 ## Technology

+- [Family 15h](family15h.md)
 - [Family 17h](family17h.md)

--- a/configs/config.emulation_qemu_x86_i440fx_noserial
+++ b/configs/config.emulation_qemu_x86_i440fx_noserial
@ -4,3 +4,5 @@ CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_CONSOLE_POST=y
 CONFIG_LINEAR_FRAMEBUFFER=y
 # CONFIG_CONSOLE_SERIAL is not set
+CONFIG_BOOTSPLASH=y
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
--- a/payloads/coreinfo/coreinfo.c
+++ b/payloads/coreinfo/coreinfo.c
@ -198,8 +198,13 @@ static void redraw_module(struct coreinfo_cat *cat)

 static void handle_category_key(struct coreinfo_cat *cat, int key)
 {
-	if (key >= 'a' && key <= 'z') {
-		int index = key - 'a';
+	if ((key >= 'a' && key <= 'z') || (key >= 'A' && key <= 'Z')) {
+		int index;
+		if (key >= 'A' && key <= 'Z') {
+			index = key - 'A';
+		} else {
+			index = key - 'a';
+		}
 		if (index < cat->count) {
 			cat->cur = index;
 			redraw_module(cat);
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@ -78,6 +78,7 @@ enum {
 	CB_TAG_VBOOT_WORKBUF		= 0x0034,
 	CB_TAG_MMC_INFO			= 0x0035,
 	CB_TAG_TCPA_LOG			= 0x0036,
+	CB_TAG_FMAP			= 0x0037,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@ -128,6 +128,9 @@ struct sysinfo_t {
 	uint32_t mtc_size;
 	void	*chromeos_vpd;
 	int	mmc_early_wake_status;
+
+	/* Pointer to FMAP cache in CBMEM */
+	void	*fmap_cache;
 };

 extern struct sysinfo_t lib_sysinfo;
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@ -239,6 +239,12 @@ static void cb_parse_vpd(void *ptr, struct sysinfo_t *info)
 	info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab);
 }

+static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info)
+{
+	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
+	info->fmap_cache = phys_to_virt(cbmem->cbmem_tab);
+}
+
 #if CONFIG(LP_TIMER_RDTSC)
 static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
 {
@ -412,6 +418,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_VPD:
 			cb_parse_vpd(ptr, info);
 			break;
+		case CB_TAG_FMAP:
+			cb_parse_fmap_cache(ptr, info);
+			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;
--- a/src/Kconfig
+++ b/src/Kconfig
@ -346,18 +346,6 @@ config OVERRIDE_DEVICETREE
 	  Examples: "devicetree.variant-override.cb"
 	            "variant/devicetree-override.cb"

-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	# Default value set at the end of the file
-	help
-	  This is the part of the ROM actually managed by CBFS, located at the
-	  end of the ROM (passed through cbfstool -o) on x86 and at at the start
-	  of the ROM (passed through cbfstool -s) everywhere else. It defaults
-	  to span the whole ROM on all but Intel systems that use an Intel Firmware
-	  Descriptor.  It can be overridden to make coreboot live alongside other
-	  components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
-	  binaries.
-
 config FMDFILE
 	string "fmap description file in fmd format"
 	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
@ -367,6 +355,20 @@ config FMDFILE
 	  but in some cases more complex setups are required.
 	  When an fmd is specified, it overrides the default format.

+config CBFS_SIZE
+	hex "Size of CBFS filesystem in ROM"
+	depends on FMDFILE = ""
+	# Default value set at the end of the file
+	help
+	  This is the part of the ROM actually managed by CBFS, located at the
+	  end of the ROM (passed through cbfstool -o) on x86 and at at the start
+	  of the ROM (passed through cbfstool -s) everywhere else. It defaults
+	  to span the whole ROM on all but Intel systems that use an Intel Firmware
+	  Descriptor.  It can be overridden to make coreboot live alongside other
+	  components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
+	  binaries. This symbol should only be used to generate a default FMAP and
+	  is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
+
 endmenu

 # load site-local kconfig to allow user specific defaults and overrides
--- a/src/arch/arm/include/arch/pci_ops.h
+++ b/src/arch/arm/include/arch/pci_ops.h
@ -14,16 +14,6 @@
 #ifndef ARCH_ARM_PCI_OPS_H
 #define ARCH_ARM_PCI_OPS_H

-#include <stdint.h>
-#include <device/pci_type.h>
-
-#ifdef __SIMPLE_DEVICE__
-u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
-u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
-u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
-void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val);
-void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val);
-void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val);
-#endif
+#include <device/pci_mmio_cfg.h>

 #endif
--- a/src/arch/mips/include/arch/pci_ops.h
+++ b/src/arch/mips/include/arch/pci_ops.h
@ -14,16 +14,6 @@
 #ifndef ARCH_MIPS_PCI_OPS_H
 #define ARCH_MIPS_PCI_OPS_H

-#include <stdint.h>
-#include <device/pci_type.h>
-
-#ifdef __SIMPLE_DEVICE__
-u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
-u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
-u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
-void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val);
-void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val);
-void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val);
-#endif
+#include <device/pci_mmio_cfg.h>

 #endif
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@ -161,7 +161,7 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 # The open quote in the subst messes with syntax highlighting. Fix it - ")
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
+	$(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@

--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@ -158,6 +158,7 @@ static inline unsigned int cpuid_edx(unsigned int op)

 #define CPUID_FEATURE_PAE (1 << 6)
 #define CPUID_FEATURE_PSE36 (1 << 17)
+#define CPUID_FEAURE_HTT (1 << 28)

 // Intel leaf 0x4, AMD leaf 0x8000001d EAX

@ -214,7 +215,8 @@ static inline bool cpu_is_intel(void)
 	return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON);
 }

-#ifndef __SIMPLE_DEVICE__
+#ifndef __ROMCC__
+/* romcc does not support anonymous structs. */

 struct device;

@ -258,9 +260,8 @@ static inline struct cpu_info *cpu_info(void)
 	);
 	return ci;
 }
-#endif

-#ifndef __ROMCC__ // romcc is segfaulting in some cases
+/* romcc is segfaulting in some cases. */
 struct cpuinfo_x86 {
 	uint8_t	x86;		/* CPU family */
 	uint8_t	x86_vendor;	/* CPU vendor */
--- a/src/commonlib/storage/pci_sdhci.c
+++ b/src/commonlib/storage/pci_sdhci.c
@ -12,10 +12,6 @@
 * GNU General Public License for more details.
 */

-#if ENV_RAMSTAGE
-#define __SIMPLE_DEVICE__		1
-#endif
-
 #include <arch/early_variables.h>
 #include <commonlib/sdhci.h>
 #include <device/pci.h>
@ -54,11 +50,11 @@ struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr)
 	return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr);
 }

-struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev)
+struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev)
 {
 	uint32_t addr;

-	addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0);
 	if (addr == ((uint32_t)~0)) {
 		sdhc_error("Error: PCI SDHCI not found\n");
 		return NULL;
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@ -65,7 +65,7 @@ uint64_t get_cc6_memory_size()
 	if (is_fam15h()) {
 		enable_cc6 = 0;

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 		if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
 			enable_cc6 = 1;
 #else
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@ -42,7 +42,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 	uint32_t family;
 	uint32_t model;

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
 #else
 	f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
@ -109,7 +109,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 		uint32_t f5x84;
 		uint8_t core_count;

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 		f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
 #else
 		f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@ -16,3 +16,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
+
+subdirs-y += common
--- a/src/cpu/intel/common/Kconfig
+++ b/src/cpu/intel/common/Kconfig
@ -22,4 +22,7 @@ config SET_IA32_FC_LOCK_BIT
 config CPU_INTEL_COMMON_TIMEBASE
 	bool

+config CPU_INTEL_COMMON_HYPERTHREADING
+	bool
+
 endif
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@ -1,4 +1,5 @@
-ramstage-y += common_init.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c

 ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
 bootblock-y += fsb.c
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@ -15,6 +15,8 @@
 #ifndef _CPU_INTEL_COMMON_H
 #define _CPU_INTEL_COMMON_H

+#include <stdint.h>
+
 void set_vmx_and_lock(void);
 void set_feature_ctrl_vmx(void);
 void set_feature_ctrl_lock(void);
@ -27,4 +29,9 @@ void set_feature_ctrl_lock(void);
 struct cppc_config;
 void cpu_init_cppc_config(struct cppc_config *config, u32 version);

+/*
+ * Returns true if it's not thread 0 on a hyperthreading enabled core.
+ */
+bool intel_ht_sibling(void);
+
 #endif
--- a/src/cpu/intel/common/hyperthreading.c
+++ b/src/cpu/intel/common/hyperthreading.c
@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/common/common.h>
+#include <arch/cpu.h>
+
+/*
+ * Return true if running thread does not have the smallest lapic ID
+ * within a CPU core.
+ */
+bool intel_ht_sibling(void)
+{
+	struct cpuid_result result;
+	unsigned int core_ids, apic_ids, threads;
+
+	/* Is Hyper-Threading supported */
+	if (!(cpuid_edx(1) & CPUID_FEAURE_HTT))
+		return false;
+
+	apic_ids = 1;
+	if (cpuid_eax(0) >= 1)
+		apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
+	if (apic_ids == 0)
+		apic_ids = 1;
+
+	core_ids = 1;
+	if (cpuid_eax(0) >= 4) {
+		result = cpuid_ext(4, 0);
+		core_ids += (result.eax >> 26) & 0x3f;
+	}
+
+	threads = (apic_ids / core_ids);
+	return !!(lapicid() & (threads - 1));
+}
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@ -13,7 +13,6 @@

 ramstage-y += model_406dx_init.c
 subdirs-y += ../../x86/name
-subdirs-y += ../common

 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@ -21,7 +21,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
-subdirs-y += ../common

 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*)
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*)
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@ -25,30 +25,6 @@
 static int first_time = 1;
 static int disable_siblings = !CONFIG(LOGICAL_CPUS);

-/* Return true if running thread does not have the smallest lapic ID
- * within a CPU core.
- */
-int intel_ht_sibling(void)
-{
-	unsigned int core_ids, apic_ids, threads;
-
-	apic_ids = 1;
-	if (cpuid_eax(0) >= 1)
-		apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
-	if (apic_ids < 1)
-		apic_ids = 1;
-
-	core_ids = 1;
-	if (cpuid_eax(0) >= 4) {
-		struct cpuid_result result;
-		result = cpuid_ext(4, 0);
-		core_ids += (result.eax >> 26) & 0x3f;
-	}
-
-	threads = (apic_ids / core_ids);
-	return !!(lapicid() & (threads-1));
-}
-
 void intel_sibling_init(struct device *cpu)
 {
 	unsigned int i, siblings;
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@ -17,11 +17,11 @@
 #include <stddef.h>
 #if !defined(__ROMCC__)
 #include <cbfs.h>
-#include <console/console.h>
 #else
 #include <arch/cbfs.h>
 #endif
 #include <arch/cpu.h>
+#include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
 #include <smp/spinlock.h>
@ -84,9 +84,7 @@ void intel_microcode_load_unlocked(const void *microcode_patch)

 	/* No use loading the same revision. */
 	if (current_rev == m->rev) {
-#if !defined(__ROMCC__)
 		printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n");
-#endif
 		return;
 	}

@ -104,18 +102,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch)

 	current_rev = read_microcode_rev();
 	if (current_rev == m->rev) {
-#if !defined(__ROMCC__)
 		printk(BIOS_INFO, "microcode: updated to revision "
 		    "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
 		    m->date & 0xffff, (m->date >> 24) & 0xff,
 		    (m->date >> 16) & 0xff);
-#endif
 		return;
 	}

-#if !defined(__ROMCC__)
 	printk(BIOS_INFO, "microcode: Update failed\n");
-#endif
 }

 uint32_t get_current_microcode_rev(void)
@ -180,13 +174,9 @@ const void *intel_microcode_find(void)
 		msr = rdmsr(IA32_PLATFORM_ID);
 		pf = 1 << ((msr.hi >> 18) & 7);
 	}
-#if !defined(__ROMCC__)
-	/* If this code is compiled with ROMCC we're probably in
-	 * the bootblock and don't have console output yet.
-	 */
+
 	printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n",
 			sig, pf, rev);
-#endif

 	while (microcode_len >= sizeof(*ucode_updates)) {
 		/* Newer microcode updates include a size field, whereas older
@ -194,17 +184,13 @@ const void *intel_microcode_find(void)
 		if (ucode_updates->total_size) {
 			update_size = ucode_updates->total_size;
 		} else {
-			#if !defined(__ROMCC__)
 			printk(BIOS_SPEW, "Microcode size field is 0\n");
-			#endif
 			update_size = 2048;
 		}

 		/* Checkpoint 1: The microcode update falls within CBFS */
 		if (update_size > microcode_len) {
-#if !defined(__ROMCC__)
 			printk(BIOS_WARNING, "Microcode header corrupted!\n");
-#endif
 			break;
 		}

--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@ -1,7 +1,6 @@
 ramstage-y += model_1067x_init.c
 ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
 subdirs-y += ../../x86/name
-subdirs-y += ../common
 subdirs-y += ../smm/gen1

 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*)
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@ -1,6 +1,5 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
-subdirs-y += ../common
 subdirs-y += ../smm/gen1
 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c

--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@ -8,7 +8,6 @@ subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode
 subdirs-y += ../../x86/smm
 subdirs-y += ../smm/gen1
-subdirs-y += ../common

 ramstage-y += acpi.c

--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@ -1,7 +1,6 @@
 ramstage-y += model_206ax_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
-subdirs-y += ../common

 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@ -7,3 +7,5 @@ config CPU_INTEL_MODEL_F2X
 	select SMP
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select SMM_ASEG
+	select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_HYPERTHREADING
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@ -17,6 +17,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/hyperthreading.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/x86/cache.h>

 static void model_f2x_init(struct device *cpu)
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@ -6,3 +6,5 @@ config CPU_INTEL_MODEL_F3X
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_HYPERTHREADING
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@ -17,6 +17,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/hyperthreading.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/x86/cache.h>

 static void model_f3x_init(struct device *cpu)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@ -38,9 +38,6 @@ int get_free_var_mtrr(void)
 	return -1;
 }

-#ifdef __ROMCC__
-static
-#endif
 void set_var_mtrr(
 	unsigned int reg, unsigned int base, unsigned int size,
 	unsigned int type)
--- a/src/device/device_const.c
+++ b/src/device/device_const.c
@ -24,6 +24,12 @@ DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root;
 /**
 * Given a PCI bus and a devfn number, find the device structure.
 *
+ * Note that this function can return the incorrect device prior
+ * to PCI enumeration because the secondary field of the bus object
+ * is 0. The failing scenario is determined by the order of the
+ * devices in all_devices singly-linked list as well as the time
+ * when this function is called (secondary reflecting topology).
+ *
 * @param bus The bus number.
 * @param devfn A device/function number.
 * @return Pointer to the device structure (if found), 0 otherwise.
--- a/src/device/i2c_bus.c
+++ b/src/device/i2c_bus.c
@ -16,6 +16,7 @@
 #include <console/console.h>
 #include <device/smbus.h>
 #include <device/i2c_bus.h>
+#include <commonlib/endian.h>

 struct bus *i2c_link(struct device *const dev)
 {
@ -159,3 +160,39 @@ int i2c_dev_writeb_at(struct device *const dev,
 		return -1;
 	}
 }
+
+int i2c_dev_read_at16(struct device *const dev,
+		      uint8_t *const buf, const size_t len, uint16_t off)
+{
+	struct device *const busdev = i2c_busdev(dev);
+	if (!busdev)
+		return -1;
+
+	if (busdev->ops->ops_i2c_bus) {
+		const struct i2c_msg msg[] = {
+			{
+				.flags	= 0,
+				.slave	= dev->path.i2c.device,
+				.buf	= (uint8_t *)&off,
+				.len	= sizeof(off),
+			},
+			{
+				.flags	= I2C_M_RD,
+				.slave	= dev->path.i2c.device,
+				.buf	= buf,
+				.len	= len,
+			},
+		};
+
+		write_be16(&off, off);
+		const int ret = busdev->ops->ops_i2c_bus->transfer(
+					busdev, msg, ARRAY_SIZE(msg));
+		if (ret)
+			return ret;
+		else
+			return len;
+	} else {
+		printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev));
+		return -1;
+	}
+}
--- a/src/device/pci_early.c
+++ b/src/device/pci_early.c
@ -11,64 +11,61 @@
 * GNU General Public License for more details.
 */

-#define __SIMPLE_DEVICE__
-
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 #include <delay.h>

-static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge)
+void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge)
 {
 	u16 reg16;
-
-	/* First we reset the secondary bus. */
-	reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
-	reg16 |= (1 << 6); /* SRESET */
-	pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
-
-	/* Assume we don't have to wait here forever */
-
-	/* Read back and clear reset bit. */
-	reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
-	reg16 &= ~(1 << 6); /* SRESET */
-	pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+	reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+	reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
+	pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
 }

-static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
+void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge)
+{
+	u16 reg16;
+	reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+	reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
+	pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+}
+
+void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
 {
 	/* Disable config transaction forwarding. */
-	pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
-	pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
+	pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
+	pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
 	/* Enable config transaction forwarding. */
-	pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
-	pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
+	pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
+	pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
 }

-static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
+static void pci_s_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
 {
 	u16 reg16;

 	/* Disable MMIO window behind the bridge. */
-	reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+	reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
 	reg16 &= ~PCI_COMMAND_MEMORY;
-	pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
-	pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
+	pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+	pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);

 	if (!size)
 		return;

 	/* Enable MMIO window behind the bridge. */
-	pci_write_config32(p2p_bridge, PCI_MEMORY_BASE,
+	pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE,
 		((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0));

-	reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+	reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+	pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
 }

-void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
+static void pci_s_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
 {
 	int timeout, ret = -1;

@ -79,12 +76,14 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
 	u8 dev = 0;

 	/* Enable configuration and MMIO over bridge. */
-	pci_bridge_reset_secondary(p2p_bridge);
-	pci_bridge_set_secondary(p2p_bridge, secondary);
-	pci_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);
+	pci_s_assert_secondary_reset(p2p_bridge);
+	pci_s_deassert_secondary_reset(p2p_bridge);
+	pci_s_bridge_set_secondary(p2p_bridge, secondary);
+	pci_s_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);

 	for (timeout = 20000; timeout; timeout--) {
-		u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID);
+		pci_devfn_t dbg_dev = PCI_DEV(secondary, dev, 0);
+		u32 id = pci_s_read_config32(dbg_dev, PCI_VENDOR_ID);
 		if (id != 0 && id != 0xffffffff && id != 0xffff0001)
 			break;
 		udelay(10);
@ -95,13 +94,13 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)

 	/* Disable MMIO window if we found no suitable device. */
 	if (ret)
-		pci_bridge_set_mmio(p2p_bridge, 0, 0);
+		pci_s_bridge_set_mmio(p2p_bridge, 0, 0);

 	/* Resource allocator will reconfigure bridges and secondary bus
 	 * number may change. Thus early device cannot reliably use config
 	 * transactions from here on, so we may as well disable them.
 	 */
-	pci_bridge_set_secondary(p2p_bridge, 0);
+	pci_s_bridge_set_secondary(p2p_bridge, 0);
 }

 void pci_early_bridge_init(void)
@ -112,7 +111,7 @@ void pci_early_bridge_init(void)
 	pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
 		CONFIG_EARLY_PCI_BRIDGE_FUNCTION);

-	pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
+	pci_s_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
 }

 /* FIXME: A lot of issues using the following, please avoid.
@ -123,7 +122,7 @@ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
 {
 	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
 		unsigned int id;
-		id = pci_read_config32(dev, 0);
+		id = pci_s_read_config32(dev, 0);
 		if (id == pci_id)
 			return dev;
 	}
@ -139,7 +138,7 @@ pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)

 	for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
 		unsigned int id;
-		id = pci_read_config32(dev, 0);
+		id = pci_s_read_config32(dev, 0);
 		if (id == pci_id)
 			return dev;
 	}
--- a/src/device/pci_ops.c
+++ b/src/device/pci_ops.c
@ -11,8 +11,6 @@
 * GNU General Public License for more details.
 */

-#define __SIMPLE_DEVICE__
-
 #include <stdint.h>
 #include <console/console.h>
 #include <device/pci.h>
--- a/src/drivers/i2c/at24rf08c/Kconfig
+++ b/src/drivers/i2c/at24rf08c/Kconfig
@ -1,7 +1,4 @@
-if VENDOR_LENOVO
-
-config SMBIOS_PROVIDED_BY_MOBO
+config DRIVER_LENOVO_SERIALS
 	bool
-	default y
-
-endif
+	default y if VENDOR_LENOVO
+	select SMBIOS_PROVIDED_BY_MOBO
--- a/src/drivers/i2c/at24rf08c/Makefile.inc
+++ b/src/drivers/i2c/at24rf08c/Makefile.inc
@ -1,2 +1,2 @@
-ramstage-$(CONFIG_VENDOR_LENOVO) += at24rf08c.c
-ramstage-$(CONFIG_VENDOR_LENOVO) += lenovo_serials.c
+ramstage-$(CONFIG_DRIVER_LENOVO_SERIALS) += at24rf08c.c
+ramstage-$(CONFIG_DRIVER_LENOVO_SERIALS) += lenovo_serials.c
--- a/src/drivers/i2c/lm96000/chip.h
+++ b/src/drivers/i2c/lm96000/chip.h
@ -93,6 +93,7 @@ struct lm96000_fan_config {
 };

 struct lm96000_temp_zone {
+	u8 low_temp;	/* temperature for min. duty cycle (in °C) */
 	u8 target_temp;	/* temperature for 100% duty cycle (in °C) */
 	u8 panic_temp;	/* temperature for 100% duty cycle on all fans */

@ -100,9 +101,12 @@ struct lm96000_temp_zone {
 	   with. (Datasheet clearly states the opposite, that this
 	   is tied to each PWM output so YMMV.) */
 	enum {
-		LM96000_LOW_TEMP_OFF = 0, /* turn fan off below low temp. */
-		LM96000_LOW_TEMP_MIN = 1, /* keep PWM at mininum duty cycle */
+		/* turn fan off below `low_temp - hysteresis` */
+		LM96000_LOW_TEMP_OFF = 0,
+		/* keep PWM at mininum duty cycle */
+		LM96000_LOW_TEMP_MIN = 1,
 	} min_off;
+	u8 hysteresis;
 };

 /* Implements only those parts currently used by coreboot mainboards. */
--- a/src/drivers/i2c/lm96000/lm96000.c
+++ b/src/drivers/i2c/lm96000/lm96000.c
@ -156,9 +156,9 @@ static void lm96000_configure_temp_zone(struct device *const dev,
 		{ 2, 3, 3, 4, 5, 7, 8, 10, 13, 16, 20, 27, 32, 40, 53, 80 };
 	unsigned int i;

-	/* find longest range that starts from 25°C */
+	/* find longest range that starts from `low_temp` */
 	for (i = ARRAY_SIZE(temp_range) - 1; i > 0; --i) {
-		if (temp_range[i] + 25 <= config->target_temp)
+		if (config->low_temp + temp_range[i] <= config->target_temp)
 			break;
 	}

@ -170,28 +170,36 @@ static void lm96000_configure_temp_zone(struct device *const dev,
 		      : 0);
 	lm96000_write(dev, LM96000_ZONE_TEMP_PANIC(zone),
 		      config->panic_temp ? config->panic_temp : 100);
+	lm96000_update(dev, LM96000_ZONE_SMOOTH(zone),
+		       LM96000_ZONE_SMOOTH_MASK(zone),
+		       LM96000_ZONE_SMOOTH_EN(zone) | 0); /* 0: 35s */
 	lm96000_update(dev, LM96000_FAN_MIN_OFF,
 		       LM96000_FAN_MIN(zone),
 		       config->min_off ? LM96000_FAN_MIN(zone) : 0);
+	lm96000_update(dev, LM96000_ZONE_HYSTERESIS(zone),
+		       LM96000_ZONE_HYST_MASK(zone),
+		       config->hysteresis << LM96000_ZONE_HYST_SHIFT(zone)
+			& LM96000_ZONE_HYST_MASK(zone));
 }

 static void lm96000_init(struct device *const dev)
 {
 	const struct drivers_i2c_lm96000_config *const config = dev->chip_info;
-	unsigned int i, lm_config;
+	unsigned int i;
+	int lm_config;
 	struct stopwatch sw;

 	printk(BIOS_DEBUG, "lm96000: Initialization hardware monitoring.\n");

 	stopwatch_init_msecs_expire(&sw, 1000);
 	lm_config = lm96000_read(dev, LM96000_CONFIG);
-	while ((lm_config < 0 || !(lm_config & LM96000_READY))) {
+	while ((lm_config < 0 || !((unsigned int)lm_config & LM96000_READY))) {
 		mdelay(1);
 		lm_config = lm96000_read(dev, LM96000_CONFIG);
 		if (stopwatch_expired(&sw))
 			break;
 	}
-	if (lm_config < 0 || !(lm_config & LM96000_READY)) {
+	if (lm_config < 0 || !((unsigned int)lm_config & LM96000_READY)) {
 		printk(BIOS_INFO, "lm96000: Not ready after 1s.\n");
 		return;
 	}
--- a/src/drivers/net/ne2k.c
+++ b/src/drivers/net/ne2k.c
@ -197,7 +197,8 @@ static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen)
 	eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base);
 }

-void ne2k_transmit(unsigned int eth_nic_base) {
+void ne2k_transmit(unsigned int eth_nic_base)
+{
 	unsigned int pktsize;
 	unsigned int len = get_count(eth_nic_base);

@ -226,8 +227,6 @@ void ne2k_transmit(unsigned int eth_nic_base) {
 	set_count(eth_nic_base, 0);
 }

-#if !ENV_RAMSTAGE
-
 static void ns8390_reset(unsigned int eth_nic_base)
 {
 	int i;
@ -267,24 +266,23 @@ static void ns8390_reset(unsigned int eth_nic_base)
 	set_count(eth_nic_base, 0);
 }

-int ne2k_init(unsigned int eth_nic_base) {
-
-#ifdef __SIMPLE_DEVICE__
+int ne2k_init(unsigned int eth_nic_base)
+{
 	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
 	unsigned char c;

-	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(0x10ec,
-				       0x8029), 0);
+	/* FIXME: This console is not enabled for bootblock. */
+	if (!ENV_ROMSTAGE)
+		return 0;

+	/* For this to work, mainboard code must have configured
+	   PCI bridges prior to calling console_init(). */
+	dev = pci_locate_device(PCI_ID(0x10ec, 0x8029), 0);
 	if (dev == PCI_DEV_INVALID)
 		return 0;

-	pci_write_config32(dev, 0x10, eth_nic_base | 1);
-	pci_write_config8(dev, 0x4, 0x1);
+	pci_s_write_config32(dev, 0x10, eth_nic_base | 1);
+	pci_s_write_config8(dev, 0x4, 0x1);

 	c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET);
 	outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET);
@ -302,9 +300,6 @@ int ne2k_init(unsigned int eth_nic_base) {
 	return 1;
 }

-#else
-int ne2k_init(unsigned int eth_nic_base) { return 0; } // dummy symbol for ramstage
-
 static void read_resources(struct device *dev)
 {
 	struct resource *res;
@ -333,5 +328,3 @@ static const struct pci_driver ne2k_driver __pci_driver = {
 	.vendor = 0x10ec,
 	.device = 0x8029,
 };
-
-#endif /* !ENV_RAMSTAGE */
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@ -13,8 +13,6 @@
 * GNU General Public License for more details.
 */

-#define __SIMPLE_DEVICE__
-
 #include <stdint.h>
 #include <stddef.h>
 #include <device/pci_ops.h>
@ -31,7 +29,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
 {
 	pci_devfn_t device = PCI_DEV(bus, dev, 0);

-	u32 id = pci_read_config32(device, PCI_VENDOR_ID);
+	u32 id = pci_s_read_config32(device, PCI_VENDOR_ID);
 	switch (id) {
 	case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
 		/* On this device function 0 is the parallel port, and
@ -39,7 +37,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
 		 * the UART.
 		 */
 		device = PCI_DEV(bus, dev, 3);
-		id = pci_read_config32(device, PCI_VENDOR_ID);
+		id = pci_s_read_config32(device, PCI_VENDOR_ID);
 		if (id != 0xc11b1415)
 			return -1;
 		break;
@ -56,12 +54,12 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
 		return -1;

 	/* Setup base address on device */
-	pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
+	pci_s_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);

 	/* Enable memory on device */
-	u16 reg16 = pci_read_config16(device, PCI_COMMAND);
+	u16 reg16 = pci_s_read_config16(device, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(device, PCI_COMMAND, reg16);
+	pci_s_write_config16(device, PCI_COMMAND, reg16);

 	car_set_var(oxpcie_present, 1);
 	return 0;
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@ -33,45 +33,39 @@ static struct device_operations ehci_dbg_ops;

 int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
 {
-	pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+	pci_devfn_t dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);

 	/* We only support controllers on bus 0. */
-	if (PCI_DEV2SEGBUS(dbg_dev) != 0)
+	if (PCI_DEV2SEGBUS(dev) != 0)
 		return -1;

-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev = dbg_dev;
-#else
-	struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(dbg_dev));
-#endif
-
-	u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+	u32 class = pci_s_read_config32(dev, PCI_CLASS_REVISION) >> 8;
 	if (class != PCI_EHCI_CLASSCODE)
 		return -1;

-	u8 pm_cap = pci_s_find_capability(dbg_dev, PCI_CAP_ID_PM);
+	u8 pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM);
 	if (pm_cap) {
-		u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL);
+		u16 pm_ctrl = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL);
 		/* Set to D0 and disable PM events. */
 		pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE;
 		pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK;
-		pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl);
+		pci_s_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl);
 	}

-	u8 pos = pci_s_find_capability(dbg_dev, PCI_CAP_ID_EHCI_DEBUG);
+	u8 pos = pci_s_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
 	if (!pos)
 		return -1;

-	u32 cap = pci_read_config32(dev, pos);
+	u32 cap = pci_s_read_config32(dev, pos);

 	/* FIXME: We should remove static EHCI_BAR_INDEX. */
 	u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
 	if (ehci_bar != EHCI_BAR_INDEX)
 		return -1;

-	pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
+	pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);

-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+	pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
 		PCI_COMMAND_MASTER);

 	*base = CONFIG_EHCI_BAR;
@ -125,11 +119,6 @@ void pci_ehci_read_resources(struct device *dev)

 u8 *pci_ehci_base_regs(pci_devfn_t sdev)
 {
-#ifdef __SIMPLE_DEVICE__
-	u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
-#else
-	struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(sdev));
-	u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
-#endif
+	u8 *base = (u8 *)(pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
 	return base + HC_LENGTH(read32(base));
 }
--- a/src/ec/kontron/kempld/kempld.c
+++ b/src/ec/kontron/kempld/kempld.c
@ -95,11 +95,13 @@ static void kempld_enable_dev(struct device *const dev)
 				dev->ops = &kempld_uart_ops;
 				break;
 			}
+			/* Fall through. */
 		case 1:
 			if (dev->path.generic.subid == 0) {
 				kempld_i2c_device_init(dev);
 				break;
 			}
+			/* Fall through. */
 		default:
 			printk(BIOS_WARNING,
 			       "KEMPLD: Spurious device %s.\n",
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@ -19,7 +19,6 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <console/post_codes.h>
-#include <console/vtxprintf.h>

 /* console.h is supposed to provide the log levels defined in here: */
 #include <commonlib/loglevel.h>
@ -29,6 +28,8 @@

 #ifndef __ROMCC__

+#include <console/vtxprintf.h>
+
 void post_code(u8 value);
 #if CONFIG(CMOS_POST_EXTRA)
 void post_log_extra(u32 value);
@ -93,6 +94,11 @@ int do_printk(int msg_level, const char *fmt, ...)

 int do_vprintk(int msg_level, const char *fmt, va_list args);

+#else
+
+static inline void romcc_printk(void) { }
+#define printk(...) romcc_printk()
+
 #endif /* !__ROMCC__ */

 #endif /* CONSOLE_CONSOLE_H_ */
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@ -3,7 +3,6 @@

 #include <arch/cpu.h>

-#if !defined(__ROMCC__)
 void cpu_initialize(unsigned int cpu_index);
 /* Returns default APIC id based on logical_cpu number or < 0 on failure. */
 int cpu_get_apic_id(int logical_cpu);
@ -14,13 +13,15 @@ void initialize_cpus(struct bus *cpu_bus);
 asmlinkage void secondary_cpu_init(unsigned int cpu_index);
 int cpu_phys_address_size(void);

+#if ENV_RAMSTAGE
 #define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver")))
-#ifndef __SIMPLE_DEVICE__
+#else
+#define __cpu_driver __attribute__((unused))
+#endif
+
 /** start of compile time generated pci driver array */
 extern struct cpu_driver _cpu_drivers[];
 /** end of compile time generated pci driver array */
 extern struct cpu_driver _ecpu_drivers[];
-#endif
-#endif /* !__ROMCC__ */

 #endif /* CPU_CPU_H */
--- a/src/include/cpu/intel/hyperthreading.h
+++ b/src/include/cpu/intel/hyperthreading.h
@ -3,6 +3,5 @@

 struct device;
 void intel_sibling_init(struct device *cpu);
-int intel_ht_sibling(void);

 #endif /* CPU_INTEL_HYPERTHREADING_H */
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@ -298,7 +298,14 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t de
 DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn);
 DEVTREE_CONST struct bus *pci_root_bus(void);

-/* To be deprecated, avoid using. */
+/* To be deprecated, avoid using.
+ *
+ * Note that this function can return the incorrect device prior
+ * to PCI enumeration because the secondary field of the bus object
+ * is 0. The failing scenario is determined by the order of the
+ * devices in all_devices singly-linked list as well as the time
+ * when this function is called (secondary reflecting topology).
+ */
 DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn);
 DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func);

@ -314,16 +321,9 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev)
 	devtree_die();
 }

-static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn)
+static inline DEVTREE_CONST void *config_of_soc(void)
 {
-	const struct device *dev = pcidev_path_on_root(devfn);
-	if (dev)
-		return config_of(dev);
-
-	devtree_bug(__func__, devfn);
-
-	dev = dev_find_slot(0, devfn);
-	return config_of(dev);
+	return config_of(pcidev_on_root(0, 0));
 }

 void scan_smbus(struct device *bus);
--- a/src/include/device/i2c_bus.h
+++ b/src/include/device/i2c_bus.h
@ -89,4 +89,12 @@ int i2c_dev_readb_at(struct device *, uint8_t off);
 */
 int i2c_dev_writeb_at(struct device *, uint8_t off, uint8_t val);

+/*
+ * Sends the 16-bit register offset `off` and reads `len` bytes into `buf`.
+ *
+ * Returns the number of bytes read on success, negative `enum cb_err`
+ * value on error.
+ */
+int i2c_dev_read_at16(struct device *, uint8_t *buf, size_t len, uint16_t off);
+
 #endif	/* _DEVICE_I2C_BUS_H_ */
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@ -55,11 +55,12 @@ struct msix_entry {
 	u32 vec_control;
 };

-#ifdef __SIMPLE_DEVICE__
-#define __pci_driver __attribute__((unused))
-#else
+#if ENV_RAMSTAGE
 #define __pci_driver __attribute__((used, __section__(".rodata.pci_driver")))
+#else
+#define __pci_driver __attribute__((unused))
 #endif
+
 /** start of compile time generated pci driver array */
 extern struct pci_driver _pci_drivers[];
 /** end of compile time generated pci driver array */
@ -115,16 +116,16 @@ struct msix_entry *pci_msix_get_table(struct device *dev);
 pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev);
 pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus);

-void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base,
-			   u32 mmio_size);
+void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge);
+void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge);
+void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary);
+
 int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);

-#ifndef __ROMCC__
 static inline int pci_base_address_is_memory_space(unsigned int attr)
 {
 	return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY;
 }
-#endif

 #endif /* CONFIG_PCI */

--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@ -3103,7 +3103,7 @@
 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM		0x1916
 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM		0x191B
 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM		0x191D
-#define PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM		0x193D
+#define PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM		0x193B
 #define PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM		0x5906
 #define PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2		0x5912
 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM		0x591E
@ -3176,7 +3176,7 @@
 #define PCI_DEVICE_ID_INTEL_SKL_ID_Y		0x190c
 #define PCI_DEVICE_ID_INTEL_SKL_ID_ULX		0x1924
 #define PCI_DEVICE_ID_INTEL_SKL_ID_H_2		0x1900
-#define PCI_DEVICE_ID_INTEL_SKL_ID_H		0x1910
+#define PCI_DEVICE_ID_INTEL_SKL_ID_H_4		0x1910
 #define PCI_DEVICE_ID_INTEL_SKL_ID_S_2		0x190f
 #define PCI_DEVICE_ID_INTEL_SKL_ID_S_4		0x191f
 #define PCI_DEVICE_ID_INTEL_KBL_ID_S		0x590f
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@ -39,7 +39,13 @@ static __always_inline pci_devfn_t pcidev_assert(const struct device *dev)
 }
 #endif

-#ifdef __SIMPLE_DEVICE__
+#if defined(__SIMPLE_DEVICE__)
+#define ENV_PCI_SIMPLE_DEVICE 1
+#else
+#define ENV_PCI_SIMPLE_DEVICE 0
+#endif
+
+#if ENV_PCI_SIMPLE_DEVICE

 /* Avoid name collisions as different stages have different signature
 * for these functions. The _s_ stands for simple, fundamental IO or
@ -91,7 +97,7 @@ void pci_write_config32(const struct device *dev, u16 reg, u32 val)

 #endif

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static __always_inline
 void pci_or_config8(pci_devfn_t dev, u16 reg, u8 ormask)
 #else
@ -103,7 +109,7 @@ void pci_or_config8(const struct device *dev, u16 reg, u8 ormask)
 	pci_write_config8(dev, reg, value | ormask);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static __always_inline
 void pci_or_config16(pci_devfn_t dev, u16 reg, u16 ormask)
 #else
@ -115,7 +121,7 @@ void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
 	pci_write_config16(dev, reg, value | ormask);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static __always_inline
 void pci_or_config32(pci_devfn_t dev, u16 reg, u32 ormask)
 #else
@ -127,7 +133,7 @@ void pci_or_config32(const struct device *dev, u16 reg, u32 ormask)
 	pci_write_config32(dev, reg, value | ormask);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static __always_inline
 void pci_update_config8(pci_devfn_t dev, u16 reg, u8 mask, u8 or)
 #else
@ -143,7 +149,7 @@ void pci_update_config8(const struct device *dev, u16 reg, u8 mask, u8 or)
 	pci_write_config8(dev, reg, reg8);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static __always_inline
 void pci_update_config16(pci_devfn_t dev, u16 reg, u16 mask, u16 or)
 #else
@ -159,7 +165,7 @@ void pci_update_config16(const struct device *dev, u16 reg, u16 mask, u16 or)
 	pci_write_config16(dev, reg, reg16);
 }

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PCI_SIMPLE_DEVICE
 static __always_inline
 void pci_update_config32(pci_devfn_t dev, u16 reg, u32 mask, u32 or)
 #else
@ -178,7 +184,7 @@ void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or)
 u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last);
 u16 pci_s_find_capability(pci_devfn_t dev, u16 cap);

-#ifndef __SIMPLE_DEVICE__
+#ifndef __ROMCC__
 static __always_inline
 u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last)
 {
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@ -4,9 +4,10 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pnp_def.h>
+#include <device/pnp_type.h>
 #include <arch/io.h>

-#ifndef __SIMPLE_DEVICE__
+#if !ENV_PNP_SIMPLE_DEVICE

 /* Primitive PNP resource manipulation */
 void pnp_write_config(struct device *dev, u8 reg, u8 value);
@ -18,7 +19,7 @@ void pnp_set_iobase(struct device *dev, u8 index, u16 iobase);
 void pnp_set_irq(struct device *dev, u8 index, u8 irq);
 void pnp_set_drq(struct device *dev, u8 index, u8 drq);

-#endif /* __SIMPLE_DEVICE */
+#endif

 /* PNP device operations */
 void pnp_read_resources(struct device *dev);
--- a/src/include/device/pnp_ops.h
+++ b/src/include/device/pnp_ops.h
@ -19,7 +19,7 @@
 #include <arch/io.h>
 #include <device/pnp_type.h>

-#ifdef __SIMPLE_DEVICE__
+#if ENV_PNP_SIMPLE_DEVICE

 static __always_inline void pnp_write_config(
 	pnp_devfn_t dev, uint8_t reg, uint8_t value)
@ -82,6 +82,6 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq)
 	pnp_write_config(dev, index, drq & 0xff);
 }

-#endif /* __SIMPLE_DEVICE__ */
+#endif

 #endif
--- a/src/include/device/pnp_type.h
+++ b/src/include/device/pnp_type.h
@ -20,4 +20,10 @@ typedef u32 pnp_devfn_t;

 #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))

+#if defined(__SIMPLE_DEVICE__)
+#define ENV_PNP_SIMPLE_DEVICE 1
+#else
+#define ENV_PNP_SIMPLE_DEVICE 0
+#endif
+
 #endif /* __DEVICE_PNP_TYPE_H__ */
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@ -19,9 +19,6 @@
 #include <commonlib/region.h>
 #include <commonlib/fmap_serialized.h>

-/* Locate the fmap directory. Return 0 on success, < 0 on error. */
-int find_fmap_directory(struct region_device *fmrd);
-
 /* Locate the named area in the fmap and fill in a region device representing
 * that area. The region is a sub-region of the readonly boot media. Return
 * 0 on success, < 0 on error. */
@ -48,4 +45,8 @@ ssize_t fmap_read_area(const char *name, void *buffer, size_t size);
 /* Write provided buffer into fmap area.
 * Return size written on success, < 0 on error. */
 ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size);
+
+/* Get offset of FMAP in flash. */
+uint64_t get_fmap_flash_offset(void);
+
 #endif
--- a/src/lib/bootsplash.c
+++ b/src/lib/bootsplash.c
@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <endian.h>
 #include <bootsplash.h>
+#include <stdlib.h>

 #include "jpeg.h"

--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@ -256,7 +256,6 @@ static void lb_boot_media_params(struct lb_header *header)
 	struct lb_boot_media_params *bmp;
 	struct cbfs_props props;
 	const struct region_device *boot_dev;
-	struct region_device fmrd;

 	boot_device_init();

@ -275,9 +274,7 @@ static void lb_boot_media_params(struct lb_header *header)
 	bmp->cbfs_size = props.size;
 	bmp->boot_media_size = region_device_sz(boot_dev);

-	bmp->fmap_offset = ~(uint64_t)0;
-	if (find_fmap_directory(&fmrd) == 0)
-		bmp->fmap_offset = region_device_offset(&fmrd);
+	bmp->fmap_offset = get_fmap_flash_offset();
 }

 static void lb_ram_code(struct lb_header *header)
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@ -31,7 +31,12 @@
 static int fmap_print_once CAR_GLOBAL;
 static struct mem_region_device fmap_cache CAR_GLOBAL;

-int find_fmap_directory(struct region_device *fmrd)
+uint64_t get_fmap_flash_offset(void)
+{
+	return FMAP_OFFSET;
+}
+
+static int find_fmap_directory(struct region_device *fmrd)
 {
 	const struct region_device *boot;
 	struct fmap *fmap;
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@ -55,6 +55,7 @@ chip soc/intel/skylake
 	register "PmTimerDisabled" = "0"
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "0"
+	register "PchHdaVcType" = "Vc1"

 	register "pirqa_routing" = "PCH_IRQ11"
 	register "pirqb_routing" = "PCH_IRQ10"
--- a/src/mainboard/asrock/h110m/ramstage.c
+++ b/src/mainboard/asrock/h110m/ramstage.c
@ -24,6 +24,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

 	params->CdClock = 3;
-	/* Enable Virtual Channel 1 */
-	params->PchHdaVcType = 0x1;
 }
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@ -237,13 +237,6 @@ void mainboard_romstage_entry(void)

 	enable_lapic();

-#if 0
-	/* Force PCIRST# */
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
-	udelay(200 * 1000);
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
-#endif
-
 	ich7_enable_lpc();
 	early_superio_config();

--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@ -45,16 +45,6 @@ config MAINBOARD_PART_NUMBER
 	default "Lulu" if BOARD_GOOGLE_LULU
 	default "Samus" if BOARD_GOOGLE_SAMUS

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "PAINE TEST A-A 8843" if BOARD_GOOGLE_AURON_PAINE
-	default "YUNA TEST A-A 3347" if BOARD_GOOGLE_AURON_YUNA
-	default "BUDDY TEST A-A 6186" if BOARD_GOOGLE_BUDDY
-	default "GANDOF TEST A-A 7705" if BOARD_GOOGLE_GANDOF
-	default "LULU TEST A-A 7705" if BOARD_GOOGLE_LULU
-	default "SAMUS TEST 8028" if BOARD_GOOGLE_SAMUS
-
 config DEVICETREE
 	string
 	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@ -42,15 +42,6 @@ config MAINBOARD_FAMILY
 	string
 	default "Google_Beltino"

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "X86 MCCLOUD TEST 5268" if BOARD_GOOGLE_MCCLOUD
-	default "X86 MONROE TEST 9962" if BOARD_GOOGLE_MONROE
-	default "X86 PANTHER TEST 6287" if BOARD_GOOGLE_PANTHER
-	default "X86 TRICKY TEST 4487" if BOARD_GOOGLE_TRICKY
-	default "X86 ZAKO TEST 8602" if BOARD_GOOGLE_ZAKO
-
 config MAX_CPUS
 	int
 	default 8
--- a/src/mainboard/google/cheza/Kconfig
+++ b/src/mainboard/google/cheza/Kconfig
@ -47,9 +47,4 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Cheza" if BOARD_GOOGLE_CHEZA

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "CHEZA TEST 1859" if BOARD_GOOGLE_CHEZA
-
 endif # BOARD_GOOGLE_CHEZA_COMMON
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@ -93,21 +93,6 @@ config VGA_BIOS_ID
 	  The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
 	  in soc/intel/braswell/Makefile.inc as 8086,22b1

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "BANON TEST A-A 8050" if BOARD_GOOGLE_BANON
-	default "CELES TEST A-A 5441" if BOARD_GOOGLE_CELES
-	default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN
-	default "EDGAR TEST A-A 2507" if BOARD_GOOGLE_EDGAR
-	default "KEFKA TEST A-A 5397" if BOARD_GOOGLE_KEFKA
-	default "REKS TEST A-A 3004" if BOARD_GOOGLE_REKS
-	default "RELM TEST A-A 2323" if BOARD_GOOGLE_RELM
-	default "SETZER TEST A-A 8721" if BOARD_GOOGLE_SETZER
-	default "TERRA TEST A-A 1650" if BOARD_GOOGLE_TERRA
-	default "ULTIMA TEST A-A 6017" if BOARD_GOOGLE_ULTIMA
-	default "WIZPIG TEST A-A 0597" if BOARD_GOOGLE_WIZPIG
-
 config CBFS_SIZE
 	hex
 	default 0x200000
--- a/src/mainboard/google/daisy/Kconfig
+++ b/src/mainboard/google/daisy/Kconfig
@ -58,8 +58,4 @@ config UART_FOR_CONSOLE
 	int
 	default 3

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "DAISY TEST A-A 9382"
 endif # BOARD_GOOGLE_DAISY
--- a/src/mainboard/google/dragonegg/Kconfig
+++ b/src/mainboard/google/dragonegg/Kconfig
@ -38,11 +38,6 @@ config DRIVER_TPM_SPI_BUS
 	depends on DRAGONEGG_USE_SPI_TPM
 	default 0x1

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "DRAGONEGG TEST 1394"
-
 config MAINBOARD_DIR
 	string
 	default "google/dragonegg"
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@ -58,13 +58,6 @@ config POWER_OFF_ON_CR50_UPDATE
 	bool
 	default n

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "ARCADACML TEST 2699" if BOARD_GOOGLE_ARCADA_CML
-	default "SARIENCML TEST 3111" if BOARD_GOOGLE_SARIEN_CML
-	default "DRALLION TEST 4932" if BOARD_GOOGLE_DRALLION
-
 config MAINBOARD_DIR
 	string
 	default "google/drallion"
@ -91,7 +84,7 @@ config MAX_CPUS

 config UART_FOR_CONSOLE
 	int
-	default 2
+	default 0

 config VARIANT_DIR
 	string
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@ -13,13 +13,24 @@ chip soc/intel/cannonlake
 	register "gen2_dec" = "0x00040941" # 0x940-0x947
 	register "gen3_dec" = "0x000c0951" # 0x950-0x95f

+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "HeciEnabled" = "0"
-	register "SataSalpSupport" = "1"
-	register "SataMode" = "Sata_AHCI"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsDevSlp[2]" = "1"
 	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "PchPmSlpS3MinAssert" = "3"  # 50ms
@ -32,7 +43,6 @@ chip soc/intel/cannonlake
 	register "psys_pmax" = "140"
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
-	register "satapwroptimize" = "1"
 	register "tdp_pl1_override" = "25"
 	register "tdp_pl2_override" = "51"
 	register "Device4Enable" = "1"
@ -187,16 +197,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcUsage[4]" = "8"
 	register "PcieClkSrcClkReq[4]" = "4"

-	# PCIe port 10 for M.2 2230 WLAN
-	register "PcieRpEnable[9]" = "1"
-	register "PcieClkSrcUsage[1]" = "9"
-	register "PcieClkSrcClkReq[1]" = "1"
-
-	# PCIe port 12 for M.2 3042 WWAN
-	register "PcieRpEnable[11]" = "1"
-	register "PcieClkSrcUsage[0]" = "11"
-	register "PcieClkSrcClkReq[0]" = "0"
-
 	# PCIe port 13 for M.2 2280 SSD
 	register "PcieRpEnable[12]" = "1"
 	register "PcieRpLtrEnable[12]" = "1"
@ -380,7 +380,7 @@ chip soc/intel/cannonlake
 		device pci 16.3 off end # Management Engine KT Redirection
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
+		device pci 17.0 off  end # SATA
 		device pci 19.0 on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
@ -389,7 +389,7 @@ chip soc/intel/cannonlake
 			end
 		end # I2C #4
 		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
+		device pci 19.2 off  end # UART #2
 		device pci 1a.0 off end # eMMC
 		device pci 1c.0 off end # PCI Express Port 1 (USB)
 		device pci 1c.1 off end # PCI Express Port 2 (USB)
@ -402,13 +402,13 @@ chip soc/intel/cannonlake
 		device pci 1d.0 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
 		end # PCI Express Port 9
-		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.1 off  end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 on  end # PCI Express Port 12
+		device pci 1d.3 off  end # PCI Express Port 12
 		device pci 1d.4 on
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
 		end # PCI Express Port 13 (x4)
-		device pci 1e.0 off end # UART #0
+		device pci 1e.0 on end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@ -131,7 +131,7 @@ static const struct pad_config gpio_table[] = {
 				 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
 /* DMIC_CLK0 */		PAD_NC(GPP_D19, NONE),
 /* DMIC_DATA0 */	PAD_NC(GPP_D20, NONE),
-/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
+/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */
 /* SPI1_IO3 */		PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */
 /* I2S_MCLK */		PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,
 				 EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
@ -214,7 +214,6 @@ static const struct pad_config gpio_table[] = {
 /* BATLOW# */		PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
 /* ACPRESENT */		PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
 /* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
-/* PWRBTN# */		PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
 /* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
 /* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
 /* SLP_A# */		PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
@ -250,6 +249,7 @@ static const struct pad_config early_gpio_table[] = {
 /* EMMC_DATA3 */	PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */
 /* EMMC_DATA4 */	PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */
 /* I2C2_SCL */		PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */
+/* PWRBTN# */		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
 };

 const struct pad_config *variant_gpio_table(size_t *num)
@ -286,4 +286,11 @@ void variant_mainboard_post_init_params(FSPM_UPD *mupd)
 	FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig;
 	if (fsp_m_cfg->PchIshEnable)
 		fsp_m_cfg->PchIshEnable = is_ish_device_enabled();
+
+	/*
+	 * Disable memory channel by HW strap pin, HW default is enable
+	 * 0: Enable both DIMMs, 3: Disable both DIMMs
+	 */
+	mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CH0_EN) ? 0 : 3;
+	mupd->FspmConfig.DisableDimmChannel1 = gpio_get(DDR_CH1_EN) ? 0 : 3;
 }
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
@ -28,6 +28,10 @@
 /* Sensor detection pin */
 #define SENSOR_DET_360		GPP_H5

+/* DDR channel enable pin */
+#define DDR_CH0_EN		GPP_F1
+#define DDR_CH1_EN		GPP_F2
+
 /* Memory configuration board straps */
 #define GPIO_MEM_CONFIG_0	GPP_F12
 #define GPIO_MEM_CONFIG_1	GPP_F13
--- a/src/mainboard/google/drallion/variants/drallion/memory.c
+++ b/src/mainboard/google/drallion/variants/drallion/memory.c
@ -23,8 +23,8 @@
 static const int spd_index[32] = {
 	0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0,
-	4, 3, 6, 1, 0, 0, 0, 0,
-	5, 0, 7, 2, 0, 0, 0, 0
+	0, 4, 3, 6, 1, 0, 0, 0,
+	0, 5, 0, 7, 2, 0, 0, 0
 	};

 const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
--- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
@ -417,6 +417,6 @@ chip soc/intel/cannonlake
 		device pci 1f.3 on  end # Intel HDA
 		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 on  end # GbE
+		device pci 1f.6 off end # GbE
 	end
 end
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@ -44,11 +44,6 @@ config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 64  # GPE0_DW2_00 (GPP_E0)

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "EVE TEST 1394"
-
 config IRQ_SLOT_COUNT
 	int
 	default 18
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@ -44,12 +44,6 @@ config VBOOT
 config DRIVER_TPM_SPI_BUS
 	default 0x1

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "FIZZ TEST 5997" if BOARD_GOOGLE_FIZZ
-	default "KARMA TEST 5022" if BOARD_GOOGLE_KARMA
-
 config MAINBOARD_DIR
 	string
 	default "google/fizz"
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@ -221,7 +221,7 @@ static unsigned long mainboard_write_acpi_tables(

 static void mainboard_enable(struct device *dev)
 {
-	config_t *conf = config_of_path(SA_DEVFN_ROOT);
+	config_t *conf = config_of_soc();

 	mainboard_set_power_limits(conf);

--- a/src/mainboard/google/foster/Kconfig
+++ b/src/mainboard/google/foster/Kconfig
@ -80,11 +80,6 @@ config DRIVER_TPM_I2C_ADDR
 #	string
 #	default "nyan"

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "FOSTER TEST 1184"
-
 config VBOOT_FWID_MODEL
 	string
 	default "Nvidia_Foster"
--- a/src/mainboard/google/gale/Kconfig
+++ b/src/mainboard/google/gale/Kconfig
@ -48,11 +48,6 @@ config MAINBOARD_PART_NUMBER
 	default "DK01" if BOARD_VARIANT_DK01
 	default "Gale"

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "Gale TEST 1"
-
 config DRAM_SIZE_MB
 	int
 	default 512 if BOARD_VARIANT_DK01
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@ -87,17 +87,6 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
 	default "glados_pd" if BOARD_GOOGLE_GLADOS
 	default ""

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "ASUKA TEST 2547" if BOARD_GOOGLE_ASUKA
-	default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE
-	default "CAVE TEST 9629" if BOARD_GOOGLE_CAVE
-	default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
-	default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
-	default "LARS TEST 5001" if BOARD_GOOGLE_LARS
-	default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY
-
 config UART_FOR_CONSOLE
 	int
 	default 2
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@ -115,14 +115,4 @@ config MAINBOARD_PART_NUMBER
 	default "Nefario" if BOARD_GOOGLE_NEFARIO
 	default "Rainier" if BOARD_GOOGLE_RAINIER

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "SCARLET TEST 7598" if BOARD_GOOGLE_SCARLET
-	default "BOB TEST 7422" if BOARD_GOOGLE_BOB
-	default "GRU TEST 5431" if BOARD_GOOGLE_GRU
-	default "KEVIN TEST 1422" if BOARD_GOOGLE_KEVIN
-	default "NEFARIO TEST 3735" if BOARD_GOOGLE_NEFARIO
-	default "RAINIER TEST 9752" if BOARD_GOOGLE_RAINIER
-
 endif # BOARD_GOOGLE_GRU_COMMON
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@ -69,16 +69,6 @@ config FMDFILE
 	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384
 	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "AKEMI TEST 4326" if BOARD_GOOGLE_AKEMI
-	default "DRATINI TEST 4583" if BOARD_GOOGLE_DRATINI
-	default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
-	default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS
-	default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED
-	default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU
-
 config MAINBOARD_DIR
 	string
 	default "google/hatch"
--- a/src/mainboard/google/hatch/variants/akemi/variant.c
+++ b/src/mainboard/google/hatch/variants/akemi/variant.c
@ -23,7 +23,7 @@ void variant_devtree_update(void)
 	uint32_t sku_id;
 	struct device *emmc_host;
 	struct device *ssd_host;
-	config_t *cfg = config_of_path(SA_DEVFN_ROOT);
+	config_t *cfg = config_of_soc();
 	emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC);
 	ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);

--- a/src/mainboard/google/hatch/variants/kindred/variant.c
+++ b/src/mainboard/google/hatch/variants/kindred/variant.c
@ -23,7 +23,7 @@ void variant_devtree_update(void)
 	uint32_t sku_id;
 	struct device *emmc_host;
 	struct device *ssd_host;
-	config_t *cfg = config_of_path(SA_DEVFN_ROOT);
+	config_t *cfg = config_of_soc();
 	emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC);
 	ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);

--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@ -37,14 +37,6 @@ config MAINBOARD_PART_NUMBER
 	default "Rikku" if BOARD_GOOGLE_RIKKU
 	default "Tidus" if BOARD_GOOGLE_TIDUS

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "GUADO TEST A-A 7416" if BOARD_GOOGLE_GUADO
-	default "JECHT TEST A-A 8958" if BOARD_GOOGLE_JECHT
-	default "RIKKU TEST A-A 0702" if BOARD_GOOGLE_RIKKU
-	default "TIDUS TEST A-A 0595" if BOARD_GOOGLE_TIDUS
-
 config MAX_CPUS
 	int
 	default 8
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@ -110,15 +110,6 @@ config VBOOT_VBNV_OFFSET
 config CHROMEOS
 	select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "ALEENA TEST 7281" if BOARD_GOOGLE_ALEENA
-	default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA
-	default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT
-	default "LIARA TEST 0464" if BOARD_GOOGLE_LIARA
-	default "TREEYA TEST 0307" if BOARD_GOOGLE_TREEYA
-
 config AMD_FWM_POSITION_INDEX
 	int
 	default 1
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@ -70,13 +70,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0x2

-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI
-	default "KRANE TEST 5417" if BOARD_GOOGLE_KRANE
-	default "KODAMA TEST 7122" if BOARD_GOOGLE_KODAMA
-	default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK
-	default "JACUZZI TEST 6792" if BOARD_GOOGLE_JACUZZI
-	default "JUNIPER TEST 4819" if BOARD_GOOGLE_JUNIPER
 endif
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@ -28,6 +28,7 @@
 #include <soc/gpio.h>
 #include <soc/mmu_operations.h>
 #include <soc/mtcmos.h>
+#include <soc/spm.h>
 #include <soc/usb.h>
 #include <string.h>

@ -201,6 +202,9 @@ static void mainboard_init(struct device *dev)
 	configure_emmc();
 	configure_usb();
 	configure_audio();
+	if (spm_init())
+		printk(BIOS_ERR,
+		       "SPM initialization failed, suspend/resume may fail.\n");

 	register_reset_to_bl31();
 }
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x7, 0x6, 0x0, 0xF},
-		[ODT_ON] = {0x9, 0x9, 0x0, 0xF}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} },
 		[CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0x0, 0x0},
 		[CHANNEL_B] = {0x0, 0x0}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x52, 0x52},
 		[CHANNEL_B] = {0x52, 0x52}
 	},
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x9, 0x7, 0x0, 0xF},
-		[ODT_ON] = {0xB, 0x9, 0x0, 0xE}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} },
 		[CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0x6, 0x5},
 		[CHANNEL_B] = {0x6, 0x6}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x56, 0x58},
 		[CHANNEL_B] = {0x58, 0x56}
 	},
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x9, 0x7, 0x0, 0xF},
-		[ODT_ON] = {0xA, 0x9, 0x0, 0xE}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },
 		[CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0x1, 0x1},
 		[CHANNEL_B] = {0x2, 0x2}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x56, 0x56},
 		[CHANNEL_B] = {0x58, 0x5C}
 	},
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x7, 0x6, 0x0, 0xF},
-		[ODT_ON] = {0x8, 0x9, 0x0, 0xD}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} },
 		[CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0x0, 0x0},
 		[CHANNEL_B] = {0x6, 0x6}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x56, 0x5A},
 		[CHANNEL_B] = {0x58, 0x58}
 	},
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x8, 0x7, 0x0, 0xF},
-		[ODT_ON] = {0x9, 0x9, 0x0, 0xD}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} },
 		[CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0xC, 0xC},
 		[CHANNEL_B] = {0xB, 0xB}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x58, 0x58},
 		[CHANNEL_B] = {0x56, 0x56}
 	},
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x9, 0x7, 0x0, 0xF},
-		[ODT_ON] = {0xA, 0x9, 0x0, 0xE}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },
 		[CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0x2, 0x2},
 		[CHANNEL_B] = {0x2, 0x2}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x5E, 0x5E},
 		[CHANNEL_B] = {0x5E, 0x5C}
 	},
--- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c
@ -16,19 +16,15 @@
 #include <soc/emi.h>

 struct sdram_params params = {
-	.impedance = {
-		[ODT_OFF] = {0x5, 0x7, 0x0, 0xF},
-		[ODT_ON] = {0x6, 0x9, 0x0, 0xF}
-	},
 	.wr_level = {
 		[CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} },
 		[CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} }
 	},
-	.cbt_cs = {
+	.cbt_cs_dly = {
 		[CHANNEL_A] = {0x5, 0x4},
 		[CHANNEL_B] = {0x8, 0x8}
 	},
-	.cbt_mr12 = {
+	.cbt_final_vref = {
 		[CHANNEL_A] = {0x56, 0x56},
 		[CHANNEL_B] = {0x56, 0x56}
 	},
--- a/Show More
+++ b/Show More