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mb/system76/gaze17: 3060: Fix RTD3 configs

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The gaze17, like the oryp9, ties all resets for RTD3 to BUF_PLT_RST#
instead of using dedicated lines and ties the enable GPIO to 3.3VS.

Disable RTD3 config for the CPU PCIe RP and disable L23 for the PCH SSD
slot to fix suspend with Western Digital drives.

Change-Id: Iab3796d98ce74e09e74abb48b437e74a60c7b6b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-07-21 15:17:46 -06:00
committed by Tim Crawford
parent 8f1a8f2a81
commit 4244f4c3d1
1 changed files with 13 additions and 10 deletions
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23
src/mainboard/system76/gaze17/variants/3060/overridetree.cb
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@ -14,12 +14,13 @@ chip soc/intel/alderlake
.clk_req = 0, .clk_req = 0,
.flags = PCIE_RP_LTR, .flags = PCIE_RP_LTR,
}" }"
chip soc/intel/common/block/pcie/rtd3 #chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2 # # XXX: Enable tied to 3.3VS?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST# # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ# # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
device generic 0 on end # register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
end # device generic 0 on end
#end
end end
device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp0 on end
device ref tcss_dma0 on end device ref tcss_dma0 on end
@ -46,7 +47,7 @@ chip soc/intel/alderlake
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ# register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end device generic 0 on end
end end
@ -60,7 +61,7 @@ chip soc/intel/alderlake
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
# XXX: No enable_gpio = no D3cold? # XXX: No enable_gpio = no D3cold?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ# register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end device generic 0 on end
end end
@ -83,8 +84,10 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR, .flags = PCIE_RP_LTR,
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1 # XXX: Enable tied to 3.3VS?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST# #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "disable_l23" = "true" # Fixes suspend on WD drives
register "srcclk_pin" = "1" # SSD_CLKREQ# register "srcclk_pin" = "1" # SSD_CLKREQ#
device generic 0 on end device generic 0 on end
end end