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mb/system76/gaze17: 3050: Hack around WD drive issue

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The WD drives fail to go from D3cold to D0. Disabling L23 on the PCH port
allows it to work. Disabling L23 on the CPU port causes the CPU to not
reach C10 during suspend, so just remove the entire RTD3 config.

Change-Id: I3bf27fb0fe98e5ec05bff9cc18ab2dd8ac6c66b3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-07-21 12:07:45 -06:00
committed by Tim Crawford
parent 682621fa1f
commit 8f1a8f2a81
1 changed files with 10 additions and 7 deletions
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17
src/mainboard/system76/gaze17/variants/3050/overridetree.cb
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@@ -17,13 +17,15 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "0" # SSD0_CLKREQ#
device generic 0 on end
end
#chip soc/intel/common/block/pcie/rtd3
# # XXX: Enable tied to 3.3VS?
# #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "reset_delay_ms" = "100"
# register "reset_off_delay_ms" = "100"
# register "srcclk_pin" = "0" # SSD0_CLKREQ#
# device generic 0 on end
#end
end
device ref xhci on
# USB2
@@ -51,6 +53,7 @@ chip soc/intel/alderlake
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "disable_l23" = "true"
register "srcclk_pin" = "1" # SSD1_CLKREQ#
device generic 0 on end
end