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mb/system76: TGL-U: Disable AER for CPU PCIe RP

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Fixes suspend with certain SSDs installed in the PCIe 4 slot.

Change-Id: Ib91b154963aeafe96c8118cbab89f0e70634e8bc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-05-05 11:51:11 -06:00
committed by Jeremy Soller
parent 090448674d
commit 5783ad7a65
2 changed files with 6 additions and 10 deletions
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8
src/mainboard/system76/galp5/ramstage.c
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@@ -3,11 +3,9 @@
#include <soc/ramstage.h>
#include "gpio.h"
static void mainboard_init(void *chip_info)
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
};

8
src/mainboard/system76/lemp10/ramstage.c
View File

@@ -3,11 +3,9 @@
#include <mainboard/gpio.h>
#include <soc/ramstage.h>
static void mainboard_init(void *chip_info)
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
mainboard_configure_gpios();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
};