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mb/system76/adl-p: galp6: Enable AER on CPU PCIe RP

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Change-Id: Ia9cb20a73bfc2bc8b856dbcf16d632c8640cc4bb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-12-30 14:18:18 -07:00
committed by Tim Crawford
parent 4416e2bc7a
commit 6734cf0eef
1 changed files with 1 additions and 1 deletions
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src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
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@@ -18,7 +18,7 @@ chip soc/intel/alderlake
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN