mb/system76/adl,rpl: Fix HDA codec init

Commit 2d48238618 ("soc/intel/alderlake: Set PchHdaSdiEnable for Alder
Lake") hooked up a new UPD, overriding the FSP default and causing HDA
init to break. Hook up the new UPD in the devicetree to restore HDA
functionality.

Also remove PchHdaAudioLinkHdaEnable per board romstage, as it set in
the devicetree.

Change-Id: I2533fa829fac4913308379788911339effa36d9f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2024-02-27 09:20:40 -07:00
parent 38c3eda699
commit 6ab4a7243c
5 changed files with 2 additions and 3 deletions

View File

@@ -81,6 +81,7 @@ chip soc/intel/alderlake
end
device ref p2sb on end
device ref hda on
register "pch_hda_sdi_enable[0]" = "1"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"

View File

@@ -15,7 +15,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;

View File

@@ -33,7 +33,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;

View File

@@ -30,7 +30,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;

View File

@@ -65,6 +65,7 @@ chip soc/intel/alderlake
end
device ref p2sb on end
device ref hda on
register "pch_hda_sdi_enable[0]" = "1"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"