sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/var/primus: Fix some GPIO programming

Browse Source 
After checking them against schematics, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
   GPP_B2  => non-use
   GPP_B15 => non-use (for FPR)
   GPP_D3  => non-use (Test point)
   GPP_E21 => non-use (for LCLW Detect)

BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot

Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Ariel Fang
2021-12-14 19:29:34 +08:00
committed by Felix Singer
parent 774ffe3998
commit 6dfc0aebb3
2 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/google/brya/variants/primus/gpio.c
View File

@@ -20,16 +20,20 @@ static const struct pad_config override_gpio_table[] = {
/* A22 : DDPC_CTRLDATA ==> NC */
PAD_NC(GPP_A22, NONE),
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
/* C4 : SML0DATA ==> NC */
PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> M2_SSD_PLN_L */
PAD_CFG_GPO(GPP_D3, 1, PLTRST),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> NC */
@@ -45,6 +49,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),

10
src/mainboard/google/brya/variants/primus4es/gpio.c
View File

@@ -20,16 +20,20 @@ static const struct pad_config override_gpio_table[] = {
/* A22 : DDPC_CTRLDATA ==> NC */
PAD_NC(GPP_A22, NONE),
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
/* C4 : SML0DATA ==> NC */
PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> M2_SSD_PLN_L */
PAD_CFG_GPO(GPP_D3, 1, PLTRST),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> NC */
@@ -45,6 +49,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),