mainboard/protectli/vault_ehl: Add initial structure
This patch adds base code for the Protectli VP2420. The GPIO config has been extracted with inteltool from the stock firmware and then parsed with intelp2m. As of now, the platform runs with edk2 with no apparent issues. Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit is contained in:
Kacper Stojek
Michał Żygowski
parent
e111de0752
commit
70089e9814
@ -168,6 +168,7 @@ The boards in this section are not real mainboards, but emulators.
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- [FW2B / FW4B](protectli/fw2b_fw4b.md)
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- [FW6A / FW6B / FW6C](protectli/fw6.md)
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- [VP2420](protectli/vp2420.md)
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- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
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## Roda
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BIN
Documentation/mainboard/protectli/VP2420_back.jpg
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BIN
Documentation/mainboard/protectli/VP2420_back.jpg
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BIN
Documentation/mainboard/protectli/VP2420_front.jpg
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Documentation/mainboard/protectli/VP2420_front.jpg
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After Width: | Height: | Size: 47 KiB |
BIN
Documentation/mainboard/protectli/VP2420_internal.jpg
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BIN
Documentation/mainboard/protectli/VP2420_internal.jpg
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After Width: | Height: | Size: 74 KiB |
87
Documentation/mainboard/protectli/vp2420.md
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87
Documentation/mainboard/protectli/vp2420.md
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@ -0,0 +1,87 @@
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# Protectli Vault VP2420
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This page describes how to run coreboot on the [Protectli VP2420].
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## Required proprietary blobs
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To build a minimal working coreboot image some blobs are required (assuming
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only the BIOS region is being modified).
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```eval_rst
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+-----------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+=====================+
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| FSP-M, FSP-S | Intel Firmware Support Package | Required |
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+-----------------+---------------------------------+---------------------+
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| microcode | CPU microcode | Required |
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+-----------------+---------------------------------+---------------------+
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```
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FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
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automatically by the coreboot build system and included into the image) from
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the `3rdparty/fsp` submodule.
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Microcode updates are automatically included into the coreboot image by build
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system from the `3rdparty/intel-microcode` submodule.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. Firmware can be easily
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flashed with internal programmer (either BIOS region or full image).
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### External programming
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The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
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This chip is located on the top side of the case (the lid side). One has to
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remove 4 top cover screws and lift up the lid. The flash chip is soldered in
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under RAM, easily accessed after taking out the memory. Specifically, it's a
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KH25L12835F (3.3V) which is a clone of Macronix
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MX25L12835F - [datasheet][MX25L12835F].
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## Working
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- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
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- 4 Ethernet ports
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- HDMI, DisplayPort
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- flashrom
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- M.2 WiFi
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- M.2 4G LTE
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- M.2 SATA and NVMe
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- 2.5'' SATA SSD
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- eMMC
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- Super I/O serial port 0 via front microUSB connector
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- SMBus (reading SPD from DIMMs)
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- Initialization with Elkhart Lake FSP 2.0
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- SeaBIOS payload (version rel-1.16.0)
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- TianoCore UEFIPayload
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- Reset switch
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- Booting Debian, Ubuntu, FreeBSD
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Celeron J6412 |
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+------------------+--------------------------------------------------+
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| PCH | Intel Elkhart Lake |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8613E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Useful links
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- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
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- [VP2420 Product Page](https://protectli.com/product/vp2420/)
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- [Protectli TPM module](https://protectli.com/product/tpm-module/)
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- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
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- [flashrom](https://flashrom.org/Flashrom)
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13
configs/config.protectli_vp2420
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13
configs/config.protectli_vp2420
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@ -0,0 +1,13 @@
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CONFIG_VENDOR_PROTECTLI=y
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CONFIG_CBFS_SIZE=0x900000
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CONFIG_ONBOARD_VGA_IS_PRIMARY=y
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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CONFIG_EDK2_BOOT_TIMEOUT=6
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CONFIG_BOARD_PROTECTLI_VP2420=y
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CONFIG_SMMSTORE_SIZE=0x40000
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CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
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CONFIG_PAYLOAD_EDK2=y
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CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
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CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
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CONFIG_EDK2_SD_MMC_TIMEOUT=10
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CONFIG_EDK2_SERIAL_SUPPORT=y
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49
src/mainboard/protectli/vault_ehl/Kconfig
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49
src/mainboard/protectli/vault_ehl/Kconfig
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@ -0,0 +1,49 @@
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_PROTECTLI_VP2420
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_ELKHARTLAKE
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select SUPERIO_ITE_IT8613E
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select SPI_FLASH_MACRONIX
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select INTEL_GMA_HAVE_VBT
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select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
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select MEMORY_MAPPED_TPM
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config MAINBOARD_DIR
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default "protectli/vault_ehl"
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config MAINBOARD_PART_NUMBER
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default "VP2420"
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config MAINBOARD_FAMILY
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default "Vault Pro"
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config MAX_CPUS
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default 4
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config CBFS_SIZE
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default 0x900000
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config VBOOT
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_FWMP
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select GBB_FLAG_DISABLE_LID_SHUTDOWN
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select VBOOT_ALWAYS_ENABLE_DISPLAY
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select VBOOT_NO_BOARD_SUPPORT
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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select VBOOT_SEPARATE_VERSTAGE
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config VBOOT_SLOTS_RW_A
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default y if VBOOT
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A
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endif # BOARD_PROTECTLI_VP2420
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4
src/mainboard/protectli/vault_ehl/Kconfig.name
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4
src/mainboard/protectli/vault_ehl/Kconfig.name
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@ -0,0 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_PROTECTLI_VP2420
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bool "VP2420"
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12
src/mainboard/protectli/vault_ehl/Makefile.inc
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12
src/mainboard/protectli/vault_ehl/Makefile.inc
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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ramstage-y += mainboard.c
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bootblock-y += die.c
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romstage-y += die.c
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ramstage-y += die.c
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smm-y += die.c
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6
src/mainboard/protectli/vault_ehl/board_info.txt
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6
src/mainboard/protectli/vault_ehl/board_info.txt
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Vendor name: Protectli
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Board name: VP2420
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Category: sbc
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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20
src/mainboard/protectli/vault_ehl/bootblock.c
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20
src/mainboard/protectli/vault_ehl/bootblock.c
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8613e/it8613e.h>
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#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
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#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
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void bootblock_mainboard_early_init(void)
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{
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ite_reg_write(GPIO_DEV, 0x29, 0xc1);
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ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */
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ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
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}
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void bootblock_mainboard_init(void)
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{
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}
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BIN
src/mainboard/protectli/vault_ehl/data.vbt
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BIN
src/mainboard/protectli/vault_ehl/data.vbt
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Binary file not shown.
214
src/mainboard/protectli/vault_ehl/devicetree.cb
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214
src/mainboard/protectli/vault_ehl/devicetree.cb
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@ -0,0 +1,214 @@
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chip soc/intel/elkhartlake
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#register "enable_vtd" = "1"
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register "power_limits_config" = "{
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.tdp_pl1_override = 10,
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.tdp_pl2_override = 15,
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}"
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register "SaGv" = "SaGv_Enabled"
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register "eist_enable" = "1"
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# Enable lpss s0ix
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register "s0ix_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route, i.e., if this route changes then the affected GPE
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# offset bits also need to be changed. This sets the PMC register
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# GPE_CFG fields.
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#register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32"
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#register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0"
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#register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0"
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register "tcc_offset" = "5" # TCC of 95C
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# USB 2.0 ports
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register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # Header FUSB1
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register "usb2_ports[1]" = "USB2_PORT_EMPTY"
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register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Header FUSB1
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register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # M.2 WLAN
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register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[5]" = "USB2_PORT_EMPTY"
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register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-A Upper
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register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-C
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register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-A Lower
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register "usb2_ports[9]" = "USB2_PORT_EMPTY"
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# USB 3.x ports
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Upper
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Lower
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Muxed
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register "usb3_ports[3]" = "USB3_PORT_EMPTY"
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# PCIe root ports related UPDs
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[1]" = "1"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[6]" = "1"
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register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
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register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
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register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
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register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
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register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
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register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
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# Storage (SATA/SDCARD/EMMC) related UPDs
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1" # Header
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register "SataPortsEnable[1]" = "1" # M.2 2280
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "1"
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register "PchHdaAudioLinkHdaEnable" = "1"
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register "PchHdaSdiEnable[0]" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "SkipCpuReplacementCheck" = "1"
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# Enable DDI ports A/B/C
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register "DdiPortAConfig" = "1"
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register "DdiPortBConfig" = "1"
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register "DdiPortCConfig" = "1"
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# Enable HPD for DDI ports A/B
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register "DdiPortAHpd" = "1"
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register "DdiPortBHpd" = "1"
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# Enable DDC for DDI ports A/B
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register "DdiPortADdc" = "1"
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register "DdiPortBDdc" = "1"
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 08.0 off end # GNA
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device pci 09.0 off end # CPU Intel Trace Hub
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device pci 10.0 on end # I2C6
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device pci 10.1 on end # I2C7
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device pci 10.5 on end # Integrated Error Handler
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device pci 11.0 off end # Intel PSE UART0
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device pci 11.1 off end # Intel PSE UART1
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device pci 11.2 off end # Intel PSE UART2
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device pci 11.3 off end # Intel PSE UART3
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device pci 11.4 off end # Intel PSE UART4
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device pci 11.5 off end # Intel PSE UART5
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device pci 11.6 off end # Intel PSE IS20
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device pci 11.7 off end # Intel PSE IS21
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device pci 12.0 on end # GSPI2
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device pci 12.3 on end # Management Engine UMA Access
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device pci 12.4 on end # Management Engine PTT DMA Controller
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device pci 12.5 off end # UFS0
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device pci 12.7 off end # UFS1
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device pci 13.0 off end # Intel PSE GSPI0
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device pci 13.1 off end # Intel PSE GSPI1
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device pci 13.2 off end # Intel PSE GSPI2
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device pci 13.3 off end # Intel PSE GSPI3
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device pci 13.4 off end # Intel PSE GPIO0
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device pci 13.5 off end # Intel PSE GPIO1
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device pci 14.0 on end # USB3.1 xHCI
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device pci 14.1 off end # USB3.1 xDCI (OTG)
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device pci 14.2 on end # Shared RAM
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device pci 15.0 off end # I2C0
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device pci 15.1 off end # I2C1
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device pci 15.2 off end # I2C2
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device pci 15.3 off end # I2C3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 18.0 off end # Intel PSE I2C7
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device pci 18.1 off end # Intel PSE CAN0
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device pci 18.2 off end # Intel PSE CAN1
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device pci 18.3 off end # Intel PSE QEP0
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device pci 18.4 off end # Intel PSE QEP1
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device pci 18.5 off end # Intel PSE QEP2
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device pci 18.6 off end # Intel PSE QEP3
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device pci 19.0 on end # I2C4
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device pci 19.1 off end # I2C5
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device pci 19.2 on end # UART2
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device pci 1a.0 on end # eMMC
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device pci 1a.1 off end # SD
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device pci 1a.3 off end # Intel Safety Island
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device pci 1b.0 off end # Intel PSE I2C0
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device pci 1b.1 off end # Intel PSE I2C1
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device pci 1b.2 off end # Intel PSE I2C2
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device pci 1b.3 off end # Intel PSE I2C3
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device pci 1b.4 off end # Intel PSE I2C4
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device pci 1b.5 off end # Intel PSE I2C5
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device pci 1b.6 off end # Intel PSE I2C6
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device pci 1c.0 on end # RP0 (pcie0 single VC)
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||||
device pci 1c.1 on end # RP1 (pcie0 single VC)
|
||||
device pci 1c.2 on end # RP2 (pcie0 single VC)
|
||||
device pci 1c.3 off end # RP3 (pcie0 single VC)
|
||||
device pci 1c.4 on end # RP4 (pcie1 multi VC)
|
||||
device pci 1c.5 off end # RP5 (pcie2 multi VC)
|
||||
device pci 1c.6 on end # RP6 (pcie3 multi VC)
|
||||
|
||||
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
|
||||
device pci 1d.1 off end # Intel PSE Time-Sensitive Networking GbE 0
|
||||
device pci 1d.2 off end # Intel PSE Time-Sensitive Networking GbE 1
|
||||
device pci 1d.3 off end # Intel PSE DMA0
|
||||
device pci 1d.4 off end # Intel PSE DMA1
|
||||
device pci 1d.5 off end # Intel PSE DMA2
|
||||
device pci 1d.6 off end # Intel PSE PWM
|
||||
device pci 1d.7 off end # Intel PSE ADC
|
||||
|
||||
device pci 1e.0 off end # UART0
|
||||
device pci 1e.1 off end # UART1
|
||||
device pci 1e.2 off end # GSPI0
|
||||
device pci 1e.3 off end # GSPI1
|
||||
device pci 1e.4 off end # PCH Time-Sensitive Networking GbE
|
||||
device pci 1e.6 off end # HPET
|
||||
device pci 1e.7 off end # IOAPIC
|
||||
|
||||
device pci 1f.0 on # eSPI interface
|
||||
chip superio/ite/it8613e
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.1 on # COM 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # Environment Controller
|
||||
device pnp 2e.5 off end # Keyboard
|
||||
device pnp 2e.6 off end # Mouse
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.a off end # CIR
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 hidden end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel cAVS/HDA
|
||||
device pci 1f.4 on end # SMBUS
|
||||
device pci 1f.5 on end # PCH SPI (flash & TPM)
|
||||
device pci 1f.7 off end # PCH Intel Trace Hub
|
||||
end
|
||||
end
|
||||
41
src/mainboard/protectli/vault_ehl/die.c
Normal file
41
src/mainboard/protectli/vault_ehl/die.c
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <pc80/i8254.h>
|
||||
#include <delay.h>
|
||||
#include <gpio.h>
|
||||
|
||||
static void beep_and_blink(void)
|
||||
{
|
||||
static uint8_t blink = 0;
|
||||
static uint8_t beep_count = 0;
|
||||
|
||||
gpio_set(GPP_E0, blink);
|
||||
/* Beep 12 times at most, constant beeps may be annoying */
|
||||
if (beep_count < 12) {
|
||||
beep(800, 300);
|
||||
mdelay(200);
|
||||
beep_count++;
|
||||
} else {
|
||||
mdelay(500);
|
||||
}
|
||||
|
||||
blink ^= 1;
|
||||
}
|
||||
|
||||
void die_notify(void)
|
||||
{
|
||||
if (ENV_POSTCAR)
|
||||
return;
|
||||
|
||||
/* Make SATA LED blink and use PC SPKR */
|
||||
gpio_output(GPP_E0, 0);
|
||||
|
||||
while (1) {
|
||||
beep_and_blink();
|
||||
beep_and_blink();
|
||||
beep_and_blink();
|
||||
beep_and_blink();
|
||||
delay(2);
|
||||
}
|
||||
}
|
||||
28
src/mainboard/protectli/vault_ehl/dsdt.asl
Normal file
28
src/mainboard/protectli/vault_ehl/dsdt.asl
Normal file
@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/elkhartlake/acpi/southbridge.asl>
|
||||
}
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
}
|
||||
1611
src/mainboard/protectli/vault_ehl/gpio.h
Normal file
1611
src/mainboard/protectli/vault_ehl/gpio.h
Normal file
File diff suppressed because it is too large
Load Diff
20
src/mainboard/protectli/vault_ehl/mainboard.c
Normal file
20
src/mainboard/protectli/vault_ehl/mainboard.c
Normal file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <fsp/api.h>
|
||||
#include <pc80/i8254.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
static void mainboard_final(void *chip_info)
|
||||
{
|
||||
beep(1500, 200);
|
||||
}
|
||||
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.final = mainboard_final,
|
||||
};
|
||||
53
src/mainboard/protectli/vault_ehl/romstage.c
Normal file
53
src/mainboard/protectli/vault_ehl/romstage.c
Normal file
@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <spd_bin.h>
|
||||
#include "gpio.h"
|
||||
|
||||
static const struct mb_cfg ddr4_mem_config = {
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
.dq_pins_interleaved = 0,
|
||||
.vref_ca_config = 2,
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
|
||||
|
||||
struct spd_info module_spd_info = {
|
||||
.read_type = READ_SPD_MEMPTR,
|
||||
};
|
||||
|
||||
/* The only DIMM slot is routed to Channel 1 */
|
||||
struct spd_block blk = {
|
||||
.addr_map = { 0x52 },
|
||||
};
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
|
||||
get_spd_smbus(&blk);
|
||||
dump_spd_info(&blk);
|
||||
|
||||
if (blk.spd_array[0] == NULL)
|
||||
die("No memory detected. Insert DIMM module");
|
||||
|
||||
module_spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0];
|
||||
module_spd_info.spd_spec.spd_data_ptr_info.spd_data_len = (uintptr_t)blk.len;
|
||||
|
||||
/* Set half_populated as false, because DIMM is on Channel 1 */
|
||||
memcfg_init(mem_cfg, &ddr4_mem_config, &module_spd_info, false);
|
||||
|
||||
/* Clear Channel 0 DIMM 0 SPD, as the slot is not populated */
|
||||
mem_cfg->MemorySpdPtr00 = 0;
|
||||
/* Return back to coreboot if something goes wrong */
|
||||
mem_cfg->ExitOnFailure = 1;
|
||||
|
||||
/* Disable both DIMMs at Channel 0 */
|
||||
mem_cfg->DisableDimmChannel0 = 3;
|
||||
/* Disable DIMM 1 at Channel 1 */
|
||||
mem_cfg->DisableDimmChannel1 = 2;
|
||||
|
||||
mem_cfg->Lp4DqsOscEn = 0;
|
||||
}
|
||||
38
src/mainboard/protectli/vault_ehl/vboot-rwa.fmd
Normal file
38
src/mainboard/protectli/vault_ehl/vboot-rwa.fmd
Normal file
@ -0,0 +1,38 @@
|
||||
FLASH 16M {
|
||||
SI_ALL 7M {
|
||||
SI_DESC 4K
|
||||
SI_ME
|
||||
}
|
||||
|
||||
RW_MISC 424K {
|
||||
UNIFIED_MRC_CACHE(PRESERVE) 128K {
|
||||
RECOVERY_MRC_CACHE 64K
|
||||
RW_MRC_CACHE 64K
|
||||
}
|
||||
SMMSTORE(PRESERVE) 256K
|
||||
RW_SHARED 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_NVRAM(PRESERVE) 24K
|
||||
}
|
||||
|
||||
CONSOLE 0x20000
|
||||
|
||||
RW_SECTION_A {
|
||||
VBLOCK_A 0x2000
|
||||
FW_MAIN_A(CBFS)
|
||||
RW_FWID_A 0x40
|
||||
}
|
||||
|
||||
WP_RO@0xC00000 0x400000 {
|
||||
RO_VPD(PRESERVE)@0x0 0x4000
|
||||
RO_SECTION@0x4000 0x3fc000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_FRID@0x800 0x40
|
||||
RO_FRID_PAD@0x840 0x7c0
|
||||
GBB@0x1000 0x3000
|
||||
COREBOOT(CBFS)@0x4000 0x3f8000
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user