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soc/intel/alderlake: Add check for CSE FW sync in romstage

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Some Alder Lake-N boards will use compressed ME RW blobs to obtain
savings on the SPI size (1916KB before compression, ~1132KB after
compression). So add an additional check before calling
cse_fw_sync() from romstage. When compressed blobs are used, the call to
CSE firmware update has to be in post-RAM stages.

BRANCH=firmware-brya-14505.B

Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Krishna P Bhat D
2022-04-21 12:20:44 +05:30
committed by Felix Held
parent 0a87c10f96
commit 7195cee17f
1 changed files with 1 additions and 1 deletions
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src/soc/intel/alderlake/romstage/romstage.c
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@@ -140,7 +140,7 @@ void mainboard_romstage_entry(void)
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);