soc/intel/tigerlake: Set correct PCH-H PCR_PSF3_T0_SHDW_PMC_REG_BASE

Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676
2021-06-17 13:37:24 -06:00 · 2021-06-17 13:37:24 -06:00 · 726051be69
commit 726051be69
parent 51636f7e46
1 changed files with 4 additions and 0 deletions
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@ -28,7 +28,11 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>

+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1000
+#else
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1100
+#endif
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8