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mb/system76: Don't set SaGv for H series boards

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Per the FSP integration guides, Geyserville only affects ULX/ULT CPUs.

Change-Id: I25edc19ae9d3ea949a214c04d8af11c2cc1f3082
This commit is contained in:
Tim Crawford 2021-01-27 09:35:44 -07:00 committed by Jeremy Soller
parent 8661b99e6c
commit 72bc5f2b46
7 changed files with 0 additions and 7 deletions
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1
src/mainboard/system76/addw1/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

1
src/mainboard/system76/addw2/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

1
src/mainboard/system76/gaze14/devicetree.cb
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@ -23,7 +23,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

1
src/mainboard/system76/gaze15/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

1
src/mainboard/system76/oryp5/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

1
src/mainboard/system76/oryp6/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

1
src/mainboard/system76/thelio-b1/devicetree.cb
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@ -21,7 +21,6 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
#register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)